A High-Efficiency PWM DC-DC Buck Converter
with a Novel DCM Control under Light-Load
Chu-Hsiang Chia
Department of Electrical Engineering
National Chung Hsing University,
Taichung, Taiwan
Pui-Sun Lei
Department of Electrical Engineering,
National Chung Hsing University,
Taichung, Taiwan
Abstract—this paper presents a high-efficiency PWM
DC-DC
buck
converter
with
a
novel
discontinuous-conduction mode (DCM) control under
light-load condition. It is designed by using TSMC
1.8/3.3V 0.18μm CMOS technology. The proposed PWM
buck converter with DCM operation not only can reach
high efficiency in heavy-load (over 95% at 100mA
loading), but also has great improvement in light-load
efficiency (36.14% higher than the conventional PWM
converter at 10mA loading) without using any PFM
techniques. The output accuracy and the output ripples
are better than PFM converters under light-load, and as
good as a normal PWM converter under heavy-load. The
proposed PWM converter is designed at 1.8V supply and
1V output voltage, and the maximum output power is
500mW.
I.
INTRODUCTION
High Performance DC-DC converters and high
performance power management ICs have been widely used
in cell phones, digital cameras, and personal digital assistants.
Moreover, wireless sensors and implanted sensors need high
performance power management units as well. For advanced
micro- processors, MCUs (Micro Controller Units) or DSPs,
the supply voltage is much lower than battery’s output
voltage. Thus, a step-down converter is required to transfer
from a high input voltage to an efficient and constant low
level voltage for these advanced control units. Maintain high
efficiency under a wide loading range is important in
extending the battery life. For some applications like cell
phones, the system works under heavy-load only when it is
communicating, and the system mostly works under
light-load when it is standby. Thus, it is not enough that
converters are high efficient only under heavy-load or
light-load. Several techniques were proposed to achieve this
requirement, and a dual-mode (PWM + PFM) converter is the
most widely used technique in different applications.
A conventional PWM converter has high efficiency under
heavy-load and low output ripple, but the main defect is the
poor efficiency under light-load. A conventional PFM
converter operates in discontinuous-conduction mode (DCM)
obtained high efficiency under light-load, but not under
heavy-load. The general solution of high efficiency under
wide loading range is to put these two techniques together.
According to the high design complexity and large chip
area of controller, dual-mode converters do have defects. This
paper presents a technique of high efficiency, low design
complexity and small chip area of controller. Using this
technique, a conventional PWM converter can have high
efficiency under both light-load and heavy-load without any
PFM control units.
Section II describes the controller of PWM and PFM
buck converters and their advantages and disadvantages. In
Section III, the proposed technique will be presented in detail
to show how to achieve high efficiency under light-load with
PWM controller. The post-layout simulation result of a
Robert Chen-Hao Chang
Department of Electrical Engineering,
National Chung Hsing University,
Taichung, Taiwan
converter with this technique and the comparison will be
discussed in Section IV. The conclusions are given in the
final section.
II.
A.
BUCK CONVERTERS TOPOLOGIES
Losses of PWM converters under light-load
Figure 1 shows the schematic of a basic PWM DC-DC
buck converter and the waveforms. In steady-state, the level
of inductor current (IL) will be constant. If the loading
changes, the level of IL will also changes. The PWM
controller is made to maintain the constant IL level when
steady state, and change the level when the loading changes.
But when the converter is operating under light-load, the IL
level will be lower and some part of IL will be lower than
zero. This part is a huge waste under light-load, and it is only
one of the defects that PWM converters operating under
light-load.
Fig. 1 A basic PWM DC-DC buck converter and IL waveform
The other defect under light-load is the switching
frequency. The switching frequency of a conventional PWM
converter is usually about 200KHz to 1MHz, no matter under
heavy-load or light-load. This frequency is not a problem
when the converter operates under heavy-load. But in the
case of light-load, the switching loss becomes critical and the
loss under this frequency greatly decreases the efficiency. So
the efficiency of a conventional PWM converter under
light-load is usually below 30%.
The conduction loss is also a problem when converters
operate under light-load. To solve this problem, the size of
the power MOS should be optimized under different loading,
but this is not included in the techniques presented in this
paper.
B.
Losses of PFM converters under heavy-load
Figure 2 shows a conventional PFM buck converter and
waveforms. A PFM DC-DC buck converter is usually used
when the converter only operates under light-load, because
PFM converters have DCM mode and lower switching
frequency. These two characteristics make PFM converters
pretty efficient under light-load. But if a conventional PFM
converter needs to operate under heavy-load, the output
ripple under light-load will increase because of the large
energy needed for heavy-load. Figure 3 shows the
relationship between output ripple and loading. If you want to
increase the loading range of a conventional PFM converter
from converter A to converter B, the output ripple under
light-load will increase, too. It is because the charge level of a
conventional PFM is constant. If you want a wide-range PFM
converter, the higher charge is way too more under light-load.
DCM mode also limits the output power of a conventional
PFM converter, so the conventional PFM converters are not
usually used under heavy-load condition. If used, the peak
efficiency will also be lower than a conventional PWM
converter.
like a normal PWM converter to reserve the good
characteristics of a PWM converter under heavy-load, such as
high efficiency, high accuracy, low output ripple, and stable
output voltage. The peak efficiency of this mode is about
96%.
The second mode is DCM mode. Under this mode, the
switching frequency will decrease and the IL below zero will
be canceled. By adding these two characteristics, the
efficiency under light-load will be greatly increased. The
peak efficiency under this mode is over 90%.
The schematic of proposed PWM buck converter is
shown in Figure 4. This technique needs only two more
blocks than a conventional PWM buck converter. The IL
detector detects the current through inductor L. In
steady-state, if IL is above zero, IL detector and the
Mode-control circuit will not turn on, the output of the
comparator passes Mode-control circuit. The converter works
as a normal PWM buck converter. But if IL is below zero, the
IL detector will send signals to Mode-control circuit and the
converter will works in DCM mode without adding PFM
control units.
Fig. 4 The proposed PWM buck converter
Fig. 2 Conventional PFM buck converter and IL waveform
The other benefit of this converter is the size of controller.
For a conventional converter, the common way to achieve
both CCM and DCM is to put PWM controller and PFM
controller together. The schematic of a dual-mode converter
is in Figure 5. Since the chip size of a converter is mostly
decided by power MOS, the size of the controller is about 1/3
of the whole chip size. The size of power MOS is decided by
maximum loading, but the size of controller can be decreased
by 50% using simple structures than dual-mode controllers.
The design complexity is much lower using the techniques in
this paper. This technique is suitable for almost every normal
current-mode PWM boost or buck converters.
MD
Fig. 3 Relationship between output ripple and loading
There are many techniques proposed to make PWM
converters suitable under light-load, or PFM converters
suitable under heavy-load. This paper will discuss some of
them in the final section, and compare to the work in this
paper.
III.
THE PROPOSED TECHNIQUE FOR PWM
CONVERTERS
In this paper, a PWM converter with two operating mode
is presented. First mode is CCM mode. The converter acts
PFM/PWM
Selector
Zero-current
detector
Mux
Buffer
VG
MD
L
Vout
R1
CL
ILoad
R2
Error
Amp.
Vref
Comparator
Current
sensor
MD
Vsaw
PFM
controller
Fig. 5 A conventional dual-mode buck converter
The schematics of the Mode-controller, buffer, and power
stage are shown in Figure 6. It is all made by simple digital
blocks, so the size of this schematic is much smaller than a
PFM controller and a PFM/PWM selector. The IL detector is
a comparator-based circuit. The detector only sends a
single-bit signal to the Mode-control circuit depending on IL
being below zero or not. To make this converter a better
design, the buffer utilized here are the non-overlap buffer.
The conventional inverter chain will lead a leakage when
switching. Figure 7 shows the difference between the inverter
chain and the non-overlap buffer. This improvement can
increase 5% to 10% under light-load.
Vout
Charge
level
IL
Fig. 9 Post-layout simulation result of the proposed converter
under different light-load
Fig. 6 The schematic of the Mode-control circuit, buffer, and
power stage
The post-layout simulation result of this converter
operates under heavy-load is shown in Figure 10. It just acts
like a normal PWM converter with high efficiency, high
accuracy, and low output ripple.
Both nMOS and
pMOS are on
Vin
Vgate_p = Vgate_n
Vth_p
Vth_n
t
Vgate_p
Vgate_n
nMOS off
pMOS on
Fig 7 Inverter chain versus non-overlap buffer
IV.
POST-SIM RESULTS AND COMPARISON
The proposed PWM DC-DC buck converter is
implemented using the TSMC 0.18μm CMOS 1P6M
technology. This buck converter reduces the voltage from
1.8V input voltage to 1V output voltage. The maximum
loading is 500mA and the maximum efficiency is 96.53%
under 100mA loading. The maximum efficiency in DCM is
90.99% under 10mA loading.
Figure 8 shows the layout of the proposed converter and
figure 9 shows the post-layout simulation results of this
proposed converter operating under different light-load. It
shows clearly that it operates just like a PFM converter
(DCM mode) and because it uses an error amplifier, the
charge level is not constant. Thus, the output ripple will not
increase when the loading is decreased. Therefore, the ripple
is much less than a PFM converter under light-load.
Fig. 10 The proposed converter operates from heavy-load to
light-load
Figures 11, 12, and 13 show the performances of this
converter, and the performance summary table is in Table I.
Compare to other techniques, the proposed converter is one
of the best choices. Comparison results are given in Table II.
Fig. 11 Output ripple versus loading
Fig. 12 Output versus loading
Fig. 8 The layout of the proposed converter
Fig. 13 Efficiency versus loading
Technology
Input voltage
Output voltage
Max loading
Switching freq.
Peak efficiency
V.
[1]
0.35μm CMOS
3.6V
1.8V
N/A
10MHz
85%
Table I Performance summary
Technology
TSMC 0.18μm CMOS
Input voltage
1.7V to 2V
Output voltage
0.5V to 1.5V
Max switching freq.
500KHz
Peak efficiency
96.53%
Output ripple
1.2mV
Max loading
500mA
Line regulation
14.7mV/V
Load regulation
8.3mV/A
Table II Comparison results
[2]
[3]
0.90nm CMOS
0.35μm CMOS
1.2V
5V
0.9V
3.6V
140mA
280mA
N/A
500KHz
99.9%
87.01%
(current,
not power
efficiency)
CONCLUSION
A novel DCM/CCM PWM DC-DC buck converter is
presented and designed with standard CMOS process. The
proposed buck converter verifies that the proposed DCM
technique provides an exact output voltage, low output ripple,
and high efficiency from 1mA to 500mA loading. The
proposed Mode-control circuit makes the DCM mode be
much easier to implement in a PWM DC-DC buck converter.
It also reduces the output ripple and increases the output
accuracy. The peak efficiency of a converter using this
technique is 96.53% under heavy-load, and 90.99% under
light-load. Maximum output ripple is only 1.2mV, which is
0.12% of the output voltage. The proposed converter can
enhance the performance of portable devices and effectively
extend the battery life.
ACKNOWLEDGMENT
This work was supported in part by the National Science
Council (NSC), Taiwan, R. O. C. under grant NSC 99-2221E-005-110 and in part by the ministry of education, Taiwan,
R. O. C. under the ATU plan. The authors would like to
thank the National Chip Implementation Center (CIC) of
Taiwan for technical support.
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