1
2015 Student EMC Hardware Design Competition
∗ University
Mislav Mikic∗ , Rebecca Grancaric∗ , Raul Blecic∗† , Adrijan Baric∗
of Zagreb, Faculty of Electrical Engineering and Computing, Unska 3, 10000 Zagreb, Croatia
Tel: +385 (0)1 6129547, fax: +385 (0)1 6129653, e-mail: raul.blecic@fer.hr
† KU Leuven, ESAT-TELEMIC, Kasteelpark Arenberg 10, 3001 Leuven, Belgium
Abstract—A step-down switched-mode power converter based
on the regulator MC34063A is designed. Special attention is
given to the minimization of its conducted emissions and output
voltage ripple. The selection of the components and the design
of the printed circuit board (PCB) layout are discussed in
detail. The operation of the designed converter is simulated by
SPICE simulations. The efficiency, output voltage ripple and
conducted emissions of the designed converter are measured.
A line impedance stabilization network (LISN) designed on a
separate PCB is used for the conducted emission measurements.
Index Terms—conducted emissions, electromagnetic interference (EMI), filter design, line impedance stabilization network
(LISN), switched-mode power supply (SMPS).
I. I NTRODUCTION
Switched-mode power converters are used more often than
the linear converters, primarily due to their higher efficiency.
Linear converters are regulated by a transistor that acts as a
variable resistor and dissipates power constantly in order to
adjust the output voltage level. The transistor of a switchedmode power converter constantly switches on and off and
dissipates power mainly during the transients between the two
states. The downside of switched-mode converters is the rich
spectrum of their switching waveforms which is a source of
conducted and radiated electromagnetic (EM) emissions [1].
The objective of this project is to design, construct and characterize a step-down converter with the conducted emissions
in the range of 150 kHz to 30 MHz as low as possible, and the
ripple of the output voltage as low as possible. The converter
is designed for the input voltages in the range from 6 to 12 V.
The output voltage is set to 3.3 V. The output current is set to
330 mA by the load resistor of 10 Ω. The regulator used in the
design is MC34063A [2], [3]. Other components required for
the converter and for the input and output filters are selected
on the basis of circuit analysis as well as the results obtained
by SPICE simulations. Printed circuit board (PCB) layout
has a considerable effect on the converter characteristics. The
layout is designed to minimize the propagation of the noise
on the PCB. Finally, after the designed converter is processed
and assembled, its efficiency, ripple of the output voltage and
conducted emissions are measured.
This paper is structured as follows. Section II describes the
selection of the components. Section III describes the design of
the printed circuit board layout. Section IV defines conducted
emissions. Section V shows the results of the measurements.
Section VI concludes the paper.
II. S CHEMATIC DESIGN
The schematic of the designed buck converter is shown in
Fig. 1. All components used in the design and their main
characteristics are listed in Table I. The selection of the
components is described in the following subsection.
A. Component Selection
1) External transistor: Selection of an external transistor
depends on several factors: its maximum VCE voltage, maximum output current, size and maximum power dissipation.
The external transistor is chosen to have a maximum collectoremitter voltage greater than the maximum input voltage
(VIN,max = 12 V), and the maximum collector current greater
than the maximum allowed current which will flow through the
converter. The maximum allowed output current is defined as
twice the nominal current to ensure that the converter operates
in the continuous mode all the time (IOU T,max = 660 mA).
Additionally, to achieve a higher efficiency, a transistor with
the VCE voltage drop as low as possible is selected. Since
the transistor is used in the Darlington configuration, the total
voltage drop can be calculated as:
VCE(sat) = VCE(sat),MC34063A + VBE,external ,
(1)
where VCE(sat),MC34063A is the saturation voltage of
Darlington-connected transistors integrated inside the
MC34063A regulator, and VBE,external is the voltage drop
across the external NPN transistor. To minimize VCE(sat) , a
transistor with low VBE,external is chosen.
The case of the transistor is chosen to ensure that the transistor is capable of withstanding the expected power dissipation.
In the worst case scenario, the power dissipation of the external
transistor can be calculated as:
Pexternal
=
D · VCE(sat) · IOU T
=
0.857 · 2 V · 0.33 A
=
0.57 W,
(2)
where D = 0.857 is the maximum achievable duty cycle
of the MC34063A [2], VCE(sat) is the sum of VBE,external
(approximated to 0.7 V) and the maximum value of
VCE(sat),MC34063A = 1.3 V [2], while the output current is
IOU T = 0.33 A.
2) Diode: The most important characteristics of the diode
are the blocking voltage, which has to be larger than the
maximum input voltage (VIN,max = 12 V), and the forward
current which has to be larger than the maximum allowed
INPUT FILTER
VIN
C2
47 µF
10 µF
L2
C8
C3
150 µF
C4
10 µF 10 µF
R1
0.51 Ω
U1
VCT
CT
1.1 nF
VCC
TC
CII
IPK
DRC
SWC
SWITCHING
NODE
OUTPUT FILTER
R2
Q1
SWE
33 Ω
GND
MC34063A
3.24 kΩ
R3
VCE
D1
10 µH
680 µH
VD
VOUT
L1
16 kΩ
R4
L3
C5
C6
10 µF
R5
VOUT,filtered
150 µF
C7
47 µF
9.76 kΩ
Fig. 1: Schematic of the designed step-down switched-mode power converter.
TABLE I: Bill of materials (BOM) for the designed step-down
switched-mode power converter.
Designator
U1
Q1
D1
L1
L2, L3
R1
R2
R3
R4
R5
CT
C2, C7
C3, C5
C4, C6, C8
Description
MC34063A, regulator
BJT, NPN, 30 V, 5.5 A
Schottky, 20 V, 2 A
Inductor, PWR, 680 µH, 1.3 A
10 µH, Isat = 1.7 A, 100 kHz
Resistor, 1 W, 0.51 Ω, 5%
Resistor, 33 Ω
Resistor, 3.24 kΩ
Resistor, 0.1%, 16 kΩ
Resistor, 0.1%, 9.76 kΩ
Cap, MLCC, 1100 pF, 50 V
Cap, 47 µF, 35 V, ALU ELEC
Cap, Alu Elec, 150 µF, 35 V
Cap, MLCC, 10 µF, 25 V
3) Output inductor: The output stage of the buck converter
consists of an inductor and a set of capacitors. The output
stage stores and delivers energy to the load, and smooths out
the switch node voltage to produce a constant output voltage.
The current ripple is a direct function of the output inductor.
The current ripple creates an output voltage ripple on the
impedance of the output capacitors. The minimum value of
the output inductor can be calculated as [2]:
Case Style
SOIC-8
SOT-223
SOD-123F
12.3 x 12.3 x 10 mm3
6.2 x 5.9 x 4.5 mm3
2512
0603
0603
0805
0805
0603
Radial, 6.3mm
Radial, 6.3mm
0805
L1,min
VIN,max − VCE(sat) − VOU T
· ton,max
Iripple,pp,max
12 − 2 − 3.3
· 0.857 · 25 · 10−6
=
0.66
= 217 µH,
(3)
=
where Iripple,pp,max is the maximum allowed ripple current
Iripple,pp,max = 0.66 A in the continuous mode, and ton,max
is the worst case on-time at the switching frequency of 40 kHz.
Since the objective is to design a converter with the ripple
of the output voltage as low as possible, the inductor with
higher value than the minimum calculated value is chosen (L1 = 680 µH). The selected inductor is packaged in a
shielded case to minimize the coupling to other parts of the
circuit [6].
4) Output capacitors: The ripple current creates a voltage
drop on the impedance of the output capacitance. To reduce
the ripple of the output voltage and the conducted emissions,
the ripple current has to be minimized (by selecting a large
value of the output inductance, as discussed in the previous
subsection), and the impedance of the output capacitance has
to be reduced. The output voltage ripple is a function of the
output capacitance and the equivalent series resistance (ESR)
of the output capacitor. The output voltage ripple peak-to-peak
output current (IOU T,max = 660 mA). Additionally, the
forward voltage VD has to be as small as possible to minimize
power dissipation. A Schottky diode is chosen because of
its lower voltage drop. Additionally, the reverse recovery
transients due to minority carrier injection and stored charge
can be neglected for Schottky diodes up to several MHz [4].
The capacitance of the diode in the off-state and the
inductance of the input decoupling network form a resonant
circuit [5]. The resonance presents an additional source of
EM interference from the switched-mode power converters.
Additionally, the overshoots of the currents and voltages in the
resonance can damage the devices, while the additional losses
related to the resonance reduce the efficiency. The slew-rate
control circuit is designed to limit the high-frequency spectrum
of the switching waveforms, and to limit the excitation of this
resonance.
2
value can be calculated as follows [7]:
Vripple,pp =
Iripple,pp
+ Iripple,pp · ESR.
8 · COU T · f
becomes greater than 330 mV, the current limit circuitry
provides an additional current path to charge the timing capacitor CT . This causes it to rapidly reach the upper oscillator
threshold, thereby shortening the time of the output switch
conduction and thus reducing the amount of energy stored in
the inductor [3]. The value of R1 is calculated by:
(4)
To achieve low output voltage ripple, it is desirable to
use capacitors with low ESR. In this project, two parallel
connected capacitors are used. The first one is an aluminum
electrolytic capacitor which provides high output capacitance
(C5 = 150 µF), and the other one is a ceramic capacitor with
low ESR (C6 = 10 µF).
5) Input capacitors: The objective, when selecting the input
capacitors, is to reduce the ripple voltage amplitude seen at
the input of the module. This reduces the ripple current to
a level which can be handled by bulk capacitors. Ceramic
capacitors placed at the input of the regulator reduce the
ripple voltage. The ESR of aluminum electrolytic and most
tantalum capacitors is too high to allow for effective ripple
reduction. Large input ripple voltage can cause large ripple
current to flow in the bulk capacitors, causing excessive power
dissipation in the ESR parasitic [8].
In this project, two parallel connected capacitors are placed
at the input. Low ESR ceramic capacitor (C4 = 10 µF) is
placed in parallel with aluminum electrolytic bulk capacitor
(C3 = 150 µF). These two capacitors are placed close to the
regulator MC34063A.
6) Timing capacitor: The external timing capacitor CT
defines the switching frequency. The relation used to select
its value is [2]:
CT = 4.0 · 10−5 [F/s] · ton ,
R1
=
330 mV/IOU T,max
=
330 mV/660 mA
=
0.5 Ω.
(7)
9) Slew rate control: To control the transistor base current
and voltage waveforms, the resistors R2 and R3 are placed
to the base of the external transistor. Resistor R2 is placed in
series between the base of the transistor and the MC34063A
output pin 2. Their purpose is to limit the turn-on time of the
external transistor. The resistor R3 is connected to the base of
the transistor and to the ground. It is a pull-down resistor to
define the turn-off time of the external transistor. The values
of the resistors R2 = 33 Ω and R3 = 3.24 kΩ are optimized
based on the SPICE simulations.
10) Compensation network: MC34063A is a hysteretic
regulator meaning that it does not require a compensation
network of the feedback loop [9].
11) Filter design: Two low-pass LC filters are added to
the board, one at the input and one at the output. The input
and output filters are designed based on the guidelines given
in [10]. The inductor is chosen to be Lf = L2 = L3 = 10 nH,
while the capacitor is calculated by:
2
1 10|Att|dB /40
.
(8)
Cf =
Lf
2πfs
(5)
where ton is the on-time of the converter. The actual value of
the timing capacitor CT = 1.1 nF is adjusted based on the
measurements of the designed converter to set the switching
frequency to 40 kHz.
7) Feedback loop: Two resistors are required to form a
voltage divider which is used to set the desired output voltage.
One of the resistors is placed between the MC34063A pin
number 5 and the output node, and the other one is placed
between the same pin and the ground. The relation that links
these two resistor values is [2]:
R4
,
(6)
VOU T = 1.25 · 1 +
R5
For the desired attenuation level of |Att|dB = 30, the value
of Cf = 50 µF is obtained and the electrolytic capacitors
C2 = C7 = 47 µF are chosen.
B. SPICE Simulations
The simulation domain consists of the model of
MC34063A, external transistor, diode, and passive components. It is used to analyze the operation of the designed
converter.
1) Design of slew-rate control circuit: The values of R2 and
R3 are optimized to ensure that the turn-on and turn-off times
of the transistor are low enough so that the high-frequency
spectrum of the switching voltage is reduced (R2 = 33 Ω and
R3 = 3.24 kΩ).
2) Analysis of the operation at low input voltages: The
simulations are performed to analyze the operation of the
designed converter when the input voltage is small. The
analysis is performed as follows. The rate of charging the
output inductor is proportional to the voltage on the inductor
when the transistor is on:
VIN − VCE(sat) − VOU T
dIL1
=
.
(9)
dt on
L1
The discharging rate is proportional to the voltage on the
output inductor when the transistor is off:
dIL1
VOU T + VD
=−
.
(10)
dt of f
L1
where VOU T is the output voltage, R4 is the resistor connected
to output voltage node and R5 the resistor connected to
ground.
One of the values can be chosen arbitrarily and then the
other one is calculated by (6). If the chosen value is too low,
then a high current will flow through the resistors and power
dissipation will be too large. On the other hand, if the value is
too large, then the circuit is susceptible to noise. The selected
value of R4 is 16 kΩ, while R5 is 9.76 kΩ. The tolerance
of the selected resistors is 0.1% to ensure accurate voltage
division.
8) Current limiting resistor: Current limiting is accomplished by monitoring the voltage drop across the external
sense resistor R1 . The voltage drop developed across this
resistor is monitored by the Ipk sense pin. When the voltage
3
0.4
5
3
0.2
1
−1
0
IL
0.5
−VD
1
Time, t [ms]
VOU T,f iltered
1.5
Current, I [A]
Voltage, V [V]
7
Ground
plane
Capacitor
C8
0
2
Switching
node
(a)
Feedback
trace
Voltage, V [V]
3.5
3.4
Vias
3.3
3.2
3.1
0
0.5
1
Time, t [ms]
VOU T,f iltered
VOU T
1.5
2
Fig. 3: Gerbers of the top layer of the designed converter.
(b)
Fig. 2: Simulated characteristic waveforms of the designed
converter: (a) inductor current IL , output voltage VOU T and
the switching voltage node VD , and (b) output voltage VOU T
and filtered output voltage VOU T,f iltered .
The switching node (the cathode of the diode) is rich
in high-frequency noise components and is a strong source
of noise in switched-mode power converters. To minimize
the capacitive coupling between the switching node and the
noise-sensitive traces, the switching copper area should be
minimized [11]. To provide a short return path for the highfrequency currents, the capacitor C8 = 10 µF is placed close
to the diode. Also, the switching node is placed far from the
input, output and regulator to physically separate the noise
source and other components.
Special attention is given to the design of the feedback
connection (comparator inverting input, CII). The feedback
trace is short and it is placed far from the switching node. It
is also well shielded by a large number of vias that connect
the surrounding ground planes in the top layer and the solid
ground plane in the bottom layer.
In the case when the input voltage VIN is small (e.g. around
6 V), and since LOU T and VOU T are fixed, the time needed
to charge the inductor is much larger than the time needed to
discharge it. The increased charging time is a consequence of
a large voltage drop on the Darlington-connected transistors,
which reduces the voltage drop across the output inductor
and increases its charging time significantly. Therefore, several
cycles of conduction are needed to charge it, while only one
cycle of non-conduction is needed to discharge it as shown
in Fig. 2. The output voltage reduces significantly during the
cycle of non-conduction and it is the dominant source of
the voltage ripple of the designed converter for small input
voltages.
IV. C ONDUCTED E MISSIONS
Conducted emissions are defined as the noise currents that
are transferred through the AC power cord and placed on the
common power net, where they may radiate more efficiently
because of the wires in the installation walls which represent
large antennas. That way they can cause interference with
other devices. The frequency range of conducted emissions
is from 150 kHz to 30 MHz. CISPR 22 class B conducted
emission limits and given in Table II [12] and in Fig. 4 [12].
For consistent results, conducted EMI tests are performed
using a passive device called a line impedance stabilization
network (LISN). The LISN is inserted in series between the
system power source and converter power inputs (in our case,
LISN is inserted in series between the converter output and
the load). The purpose of the capacitors C3 and C4 and the
inductors L1 and L2 is to divert external noise and to prevent
III. L AYOUT C ONSIDERATIONS
The designed printed circuit board (PCB) is a 1.5-mm thick,
2-layer board on the FR-4 substrate. The thickness of the
copper layer is 35 µm. The dimensions of the PCB are 46 mm
x 71 mm. The top layer of the designed PCB is shown in
Fig. 3.
Proper layout design can greatly reduce the emissions. The
return path of high-frequency currents should be as close as
possible to the noise source to minimize the propagation of
the noise across the board. The return paths are minimized
by a solid ground plane in the bottom layer connected by a
large number of vias to the ground planes in the top layer.
Additionally, all the components are chosen in a small-size
SMD packages to reduce their parasitic inductances.
4
TABLE II: CISPR 22 conducted emission limits for class B
digital devices [12].
Frequency (MHz)
0.15
0.5
0.5 - 5
5 - 30
dB µV QP (AV)
66 (56)
56 (46)
56 (46)
60 (50)
Measured with LISN
66
Voltage (dBµV)
µV QP (AV)
1995 (631)
631 (199.5)
631 (199.5)
1000 (316)
Fig. 6: Gerbers of the top layer of the designed LISN.
60
(QP)
56
TABLE III: Bill of materials (BOM) for LISN.
50
46
(AV)
f
150 kHz
500 kHz
5 MHz
30 MHz
Fig. 4: CISPR 22 conducted emission limits for class B digital
devices [12].
Designator
C1, C2
C3, C4
R1, R2
L1, L2
X1, X2
X3, X4
Description
MLCC, 0.1 µF, 100 V, 5%, X7R
MLCC, 1 µF, 100 V, 10%, X7S
1 kΩ
56 µH, Irms = 2.4 A, 10 MHz
Terminal block
SMA, end launch
Case Style
1206
0805
0805
12.3 x 12.3 x 6 mm3
3.5 mm pitch
SMA
V. M EASUREMENTS
The measurements of the efficiency, output voltage ripple
and conducted emissions of the designed converter are shown
in this section.
that noise from flowing through the measurement device and
contaminating the test data. The purpose of the capacitors C1
and C2 is to prevent any DC from overloading the input of
the test receiver. The resistors R1 and R2 act as static charge
paths to discharge the capacitors C1 and C2 in the event that
the 50-Ω resistors are removed. One 50-Ω resistor is the input
impedance of the test receiver (spectrum analyzer or EMI
reciever), while the other one is a 50-Ω dummy load. The
schematic of a LISN is shown in Fig. 5 [12].
A. Time-domain measurements
The time-domain measurements are performed for the input
voltages in the range from 6 to 12 V with the 1-V step. A 10-Ω
resistor is connected to the output of the converter. The input
current IIN , the input voltage VIN , the output voltage VOU T
and the ripple of the output voltage VOU T,pp are measured.
From the measurements, the input power, output power, loss
and efficiency are calculated as:
The LISN is designed on a separate PCB. The top layer is
shown in Fig. 6. The bottom layer is a solid ground plane.
The BOM for the LISN is given in Table III.
LISN
IP
Phase
L1
Product
under
test
IN
C1
IP Neutral L2
IN
C3
C2
C4
R1
50
Ω
R2
PIN
=
POU T
=
PLOSS
=
η
=
VIN · IIN
2
VOU
T
RLOAD
PIN − POU T
POU T
.
PIN
(11)
(12)
(13)
(14)
The measured and calculated results are given in Table IV.
The calculated efficiency is shown in Fig. 7, while the measured time-domain waveforms of the ripple of the output
voltage for VIN = 6 V and for VIN = 12 V are shown in
Fig. 8. The characteristic waveforms for VIN = 6 V and for
To
VIN = 12 V are shown in Fig. 9 and Fig. 11, respectively.
ac
power The characteristic waveforms at the turn-on and turn-off of the
net
external transistor for VIN = 6 V are shown in Fig. 10.
50
Ω
B. Conducted emissions measurements
Conducted emissions are measured in the frequency range
R
from 150 kHz to 30 MHz [13]. An R&S
ESRP EMI Test
Receiver is used for the measurements. The parameters of
the receiver used in the measurements are set according to
CISPR 16 [14] and are given in Table V. The conducted
Green wire
Fig. 5: The schematic of a line impedance stabilization network (LISN) [12].
5
TABLE IV: Time-domain measurements as a function of the input voltage.
VIN [V]
(meas)
6
7
8
9
10
11
12
IIN [A]
(meas)
0.28
0.24
0.20
0.18
0.16
0.14
0.13
VOU T [V]
(meas)
3.263
3.278
3.279
3.282
3.281
3.291
3.286
RLOAD [Ω]
(nominal)
10
10
10
10
10
10
10
PIN [W]
(calc)
1.680
1.680
1.600
1.620
1.600
1.540
1.560
POU T [W]
(calc)
1.065
1.075
1.075
1.077
1.077
1.083
1.080
72
8
68
66
64
VOU T,f iltered
VOU T,pp [mV]
(meas)
41.5
19.8
16.4
19.2
24.0
8.0
33.6
VIN
−VD
VCT
4
2
0
7
8
9
10
Input voltage, VIN [V]
11
−2
0
12
Fig. 7: Measured efficiency as a function of the input voltage.
0.1
0.2
0.3
Time, t [ms]
0.4
0.5
Fig. 9: Characteristic waveforms measured at VIN = 6 V.
3.32
8
3.3
6
Voltage, V [V]
Output voltage ripple, Vripple [V]
Efficiency, η [%]
(calc)
63.38
63.96
67.20
66.49
67.28
70.33
69.22
6
Voltage, V [V]
Efficiency, η[%]
70
62
6
PLOSS [W]
(calc)
0.615
0.605
0.525
0.543
0.523
0.457
0.480
3.28
3.26
3.24
3.22
0
VIN = 6 V, Vpp = 41.5 mV
VIN = 12 V, Vpp = 33.6 mV
0.5
1
4
2
0
1.5
−2
0
Time, t [ms]
Fig. 8: Output voltage ripple measured at VIN = 6 V and
VIN = 12 V.
VOU T,f iltered
1
2
3
4
Time, t [µs]
VIN
5
−VD
6
VCT
7
Fig. 10: Characteristic waveforms measured at VIN = 6 V,
zoomed to capture the turn-on and turn-off waveforms of the
external transistor. Weakly-excited resonance [5] can be seen
at the moment when the transistor turns on.
emissions are measured at the output of the converter. LISN
is connected between the output of the converter and the
10-Ω load resistor. The measurements performed using a peak
detector are well below the specified limits [13].
The measurement setup is shown in Fig. 14, while the
designed converter during measurements is shown in Fig. 15.
The metallic enclosure covers the converter during the measurements of the conducted emissions.
Fig. 12 shows measured conducted emissions. Additional
measurements in the frequency range from 9 kHz to 500
kHz are performed to capture the switching frequency and
the higher harmonics in more detail and they are shown in
Fig. 13.
VOU T,f iltered
Voltage, V [V]
12
VIN
−VD
VC T
8
4
0
0
0.1
0.2
0.3
Time, t [ms]
0.4
0.5
Fig. 11: Characteristic waveforms measured at VIN = 12 V.
6
TABLE V: Parameters of the EMI Receiver according to CISPR 16 [14] used in the measurements.
Frequency Range
9 kHz - 150 kHz
150 kHz - 30 MHz
Resolution Bandwidth (RBW)
CISPR - 200 Hz
CISPR - 9 kHz
Video Bandwith (VBW)
200 Hz
200 Hz
Detector
auto peak (max hold)
auto peak (max hold)
Sweep points
1000
1000
Conducted EMI, [dBµV]
Metallic enclosure
DC source
Measured Conducted EMI
CISPR 22, Class B, Quasi-Peak Detector
CISPR 22, Class B, Average Detector
80
60
40
20
0
150
1000
Frequency, f [kHz]
10000
30000
Conducted EMI, [dBµV]
Fig. 12: Conducted emissions in the frequency range from
150 kHz to 30 MHz (according to the CISPR 22 Class B [13])
measured at the output of the designed converter. The input
voltage is set to VIN = 6 V.
80
Designed converter
Oscilloscope
EMI receiver
Fig. 14: Measuring conducted emissions of the designed
converter.
Measured Conducted EMI
CISPR 22, Class B, Quasi-Peak Detector
CISPR 22, Class B, Average Detector
60
Load
(10 Ω)
40
20
0
9
43
86 129172
Frequency, f [kHz]
To EMI
reveiver
500
LISN
50-Ω
termination
Designed
converter
Fig. 13: Conducted emissions in the frequency range from
9 kHz to 500 kHz measured at the output of the designed
converter. The input voltage is set to VIN = 6 V. The
spectrum shows the switching frequency of 43 kHz and higher
harmonics.
Fig. 15: Measuring conducted emissions - close-up of the
designed converter.
7
VI. C ONCLUSION
[13] IEC CISPR22, “Information Technology Equipment - Radio Disturbance
Characteristics - Limits and methods of measurement,” 2006.
A step-down switched-mode power converter is designed,
analyzed and characterized. The design is based on the regulator MC34063A. The selection of the components and the
design of the PCB layout are discussed. The operation of
the converter is analyzed by SPICE simulations. The ripple
of the output voltage for small values of the input voltage
is a consequence of a large difference between the charging
time and the discharging time of the output inductor. The
difference is a consequence of a large voltage drop on the
Darlington-connected transistors, which reduces the voltage
drop across the output inductor and increases its charging
time significantly. This is the dominant source of the ripple
of the output voltage of the designed converter for small input
voltages around 6 V.
The ripple of the output voltage measured at the input
voltage of 6 V is 41.5 mV. The conducted emissions are
measured by a LISN designed on a separate PCB. The
measured conducted emissions at the input voltage of 6 V
and using a peak detector are well below the limits given by
the regulations. The 4th harmonic at 172 kHz is less than
20 dBµV.
[14] IEC CISPR16, “Specification for radio disturbance and immunity measuring apparatus and methods,” 2004.
Mislav Mikic was born in Slavonski Brod, Croatia, in 1991. He received the Mag.-Ing. degree in
electrical engineering from the University of Zagreb,
Zagreb, Croatia, in 2015. Currently, he is an embedded software engineer at the IEL d.o.o Zagreb.
His work include programming microntrollers. The
topic of his Master’s thesis was design of switching
DC-DC converters with respect to electromagnetic
compatibility.
Rebecca Grancaric was born in Zadar, Croatia, in
1993. She received the Bacc.Ing. degree in electrical
engineering from the University of Zagreb, Zagreb,
Croatia, in 2015. Currently, she is a first year graduate student at the University of Zagreb. The topic
of her undergraduate thesis was characterization of
step-down switched-mode power converter focusing
on electromagnetic compatibility.
R EFERENCES
[1] D. M. Robert W. Erickson, Fundamentals of Power Electronics. Kluwer
Academic Publishers, New York, Boston, Dordrecht, London, Moscow,
2004.
[2] MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A - 1.5
A, Step-Up/Down/Inverting Switching Regulators, ON Semiconductor,
2010.
[3] J. Alberkrack, AN920/D - Theory and Applications of the MC34063
and µA78S40 Switching Regulator Control Circuit, ON Semiconductor,
2002.
[4] ON Semiconductor, 1N5817/D - Axial Lead Rectifiers, ON Semiconductor, 2006.
[5] A. Bhargava, D. Pommerenke, K. Kam, F. Centola, and C. W. Lam, “DCDC Buck Converter EMI Reduction Using PCB Layout Modification,”
IEEE Trans. Electromagn. Compat., vol. 53, no. 3, pp. 806–813, Aug.
2011.
[6] Texas Instruments, AN-2155 Layout Tips for EMI Reduction in DC / DC
Converters, Texas Instruments, 2013.
[7] ——, SLVA630A Output Ripple Voltage for Buck Switching Regulator,
Texas Instruments, 2015.
[8] J. Arrigo, Input and Output Capacitor Selection, Texas Instruments,
2006.
[9] S. Maniktala, Technical Note TN-203, Microsemi, 2012.
[10] A. Martin, AN-2162 Simple Success With Conducted EMI from DC-DC
Converters, Texas Instruments, 2013.
[11] H. J. Zhang, Application Note 136 - PCB Layout Considerations for
Non-Isolated Switching Power Suplies, Linear Technology, 2012.
[12] C. R. Paul, Introduction to Electromagnetic Compatibility. John Wilwy
& Sons, Inc., Hoboken, New Yesey, 2006.
Raul Blecic was born in Rijeka, Croatia, in 1986. He
received the Dipl.-Ing. degree in electrical engineering from the University of Zagreb, Zagreb, Croatia,
in 2009. Currently, he is a double degree PhD
student at the University of Zagreb and KU Leuven,
Belgium. His research interests include electromagnetic compatibility of integrated circuits, integrated
circuit design and modelling of microwave structures
and components.
Adrijan Baric received the Dipl.-Ing. and M.Sc.
degrees in electrical engineering from the University
of Zagreb, Zagreb, Croatia, in 1982 and 1985, respectively, and the Ph.D. degree in electronics from
the Dublin City University, Dublin, Ireland, in 1995.
Since 1984, he has been with the University of Zagreb, where he is currently a Professor. His research
interests include semiconductor device modeling,
integrated circuit design, interconnect modeling and
electromagnetic compatibility.
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