Self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor fieldeffect transistor with Al 2 O 3 gate dielectric
D. Shahrjerdi, T. Akyol, M. Ramon, D. I. Garcia-Gutierrez, E. Tutuc, and S. K. Banerjee
Citation: Applied Physics Letters 92, 203505 (2008); doi: 10.1063/1.2931708
View online: http://dx.doi.org/10.1063/1.2931708
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APPLIED PHYSICS LETTERS 92, 203505 共2008兲
Self-aligned inversion-type enhancement-mode GaAs metal-oxidesemiconductor field-effect transistor with Al2O3 gate dielectric
D. Shahrjerdi,a兲 T. Akyol, M. Ramon, D. I. Garcia-Gutierrez,b兲 E. Tutuc, and S. K. Banerjee
Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758, USA
共Received 20 March 2008; accepted 26 April 2008; published online 21 May 2008兲
In this letter, we report fabrication of self-aligned inversion-type enhancement-mode GaAs
metal-oxide-semiconductor 共MOS兲 field-effect transistors with atomic layer deposition of Al2O3
gate dielectric directly on GaAs substrates using a simple ex situ wet clean of GaAs. Thermal
stability of the gate stack was examined by monitoring the frequency dispersion behavior of GaAs
MOS capacitors under different annealing conditions. A maximum drive current of ⬃4.5 ␮A / ␮m
was obtained for a gate length of 20 ␮m at a gate overdrive of 2.5 V. The threshold voltage and
subthreshold slope were determined to be ⬃0.4 V and ⬃145 mV/ dec from the corresponding Id-Vg
characteristics. © 2008 American Institute of Physics. 关DOI: 10.1063/1.2931708兴
The conventional scaling trend of bulk silicon complementary metal-oxide-semiconductor technology has encountered formidable challenges below the 22-nm technology
node.1 This has led to considerable research on high-mobility
channel materials, including strained Si, Ge, and III-V-based
structures. Recently, III-V-based materials have gained substantial interest as a candidate for n-channel metal-oxidesemiconductor field-effect transistors 共nMOSFET兲 due to
their superior electron transport properties. However, the
lack of a compatible native oxide has been an impediment to
realizing enhancement-mode 共e-mode兲 III-V MOSFETs due
to poor characteristics of the oxide/III-V interface. In order
to circumvent this issue, various surface passivation schemes
have been studied, primarily on GaAs-based materials. This
includes the use of amorphous Si and Ge interfacial layers2–5
and GaAs surface nitridation,6 employing an MBE-grown
Ga2O3 共Gd2O3兲 共Refs. 7–11兲 and atomic layer deposition
共ALD兲 of Al2O3.12–15 It is known that ALD offers a precise
control over the uniformity and thickness of the deposited
film through a self-limiting reaction.16 Although MOS capacitors have been extensively utilized to study physical and
electrical characteristics of high-␬/III-V interface, there have
been only few demonstrations of inversion-type e-mode
GaAs and In1−xGaxAs nMOSFETs. The first demonstrations
of e-mode GaAs and In0.53Ga0.47As MOSFETs were carried
out in Bell Labs by employing MBE-grown Ga2O3 共Gd2O3兲,
where GaAs transistors exhibited much lower drive current
than In0.53Ga0.47As MOSFETs.9,10 However, Hong et al. were
able to further improve the drive current of GaAs MOSFETs
by adopting a similar scheme.11 Also, fabrication of selfaligned e-mode GaAs MOSFETs with improved performance over the previous works has been reported by employing a-Si interfacial layer.3 In addition, inversion-type
e-mode In0.53Ga0.47As MOSFETs with relatively large drive
current has been recently demonstrated using ALD
Al2O3.13,14 Superior performance of In0.53Ga0.47As
MOSFETs can stem from much lower surface state densities
of InGaAs with respect to GaAs, deduced by evaluating surface recombination velocity at the interface of GaAs and
a兲
Electronic mail: davood@mail.utexas.edu.
Present address: Advanced Technology Development Facility 共ATDFSEMATECH兲, Austin, Texas 78741.
b兲
InGaAs with their native oxides from photoluminescence intensity data.17,18 This phenomenon indicates that surface passivation of GaAs tends to be inherently more challenging
than InGaAs. Here, we have studied thermodynamic stability
of the Al2O3 / GaAs interface by monitoring C-V characteristics of GaAs MOS capacitors at different annealing temperatures. By exploiting the excellent thermal stability of the
interface, we have demonstrated self-aligned e-mode GaAs
nMOSFETs.
Capacitor and MOSFET fabrication processes started
with surface chemical cleaning of GaAs substrates in HF
共1%兲 and 共NH4兲2S 共20%兲 at room temperature for 2 and
10 min, respectively,15 followed by deposition of 82 Å thick
ALD Al2O3 at 250 ° C. Capacitors were fabricated on 共100兲
n- and p-type GaAs substrates with a doping concentration
of 共5 – 10兲 ⫻ 1017 / cm3, while 共100兲 undoped GaAs substrates
were used for MOSFET fabrication. Postdeposition anneal
共PDA兲 was carried out at 550 ° C for 3 min in N2 ambient.
Subsequently, TaN metal gate was sputtered, followed by
patterning using standard photolithography and CF4 reactive
ion etch. Then, MOSCAP samples were capped with
⬃200 nm thick plasma-enhanced chemical vapor deposition
共PECVD兲 SiO2 prior to postmetallization anneal 共PMA兲.
Ring-FET geometry was used for MOSFET fabrication in
order to simplify the device isolation process. Next,
MOSFETs received Si implants of 50 keV with a dose of
1 ⫻ 1014 / cm2. In order to rule out degradation of GaAs during dopant activation, due to outdiffusion or sublimation of
As atoms, 200 nm thick PECVD SiO2 was deposited at
285 ° C. Source/drain 共S/D兲 dopant activation is a critical
step where the smoothness of the Al2O3 / GaAs interface
must be maintained while attempting to obtain high activation levels. Therefore, activation anneals were performed at
temperatures ranging from 780 to 850 ° C for 10– 30 s.
Then, SiO2 encapsulation layer was stripped off in buffered
oxide etch solution. Finally, S/D ohmic contacts were formed
by evaporation and subsequent lift-off of AuGe/ Ni/ Au, followed by annealing at 450 ° C for 30 s in N2 ambient.
Figure 1共a兲 illustrates frequency dispersion behavior of
GaAs MOS capacitors on p- and n-type substrates where
MOS capacitors on n-type GaAs exhibit noticeably high frequency dispersion. This difference can be attributed to the
presence of larger surface state density on n-type GaAs with
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92, 203505-1
© 2008 American Institute of Physics
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203505-2
Shahrjerdi et al.
Appl. Phys. Lett. 92, 203505 共2008兲
FIG. 1. 共a兲 The C-V characteristics of
GaAs MOS capacitors on p- and
n-type substrates. 共b兲 Frequency dispersion behavior and CET values of
p-GaAs capacitors at different annealing temperatures.
respect to p-type GaAs.19,20 Nonetheless, MOS capacitors on
p-type substrates exhibit excellent frequency dispersion behavior. Despite the significant improvement of the C-V characteristics upon employing the ex situ chemical clean and
ALD of Al2O3 using TMA, an appropriate investigation of
Fermi level pinning at the interface entails C-V characterization at elevated temperatures,21 or quasistatic C-V measurements at very slow sweep rate.22 The observed hysteresis
from the bidirectional C-V sweeps at 1 MHz was determined
to be ⬃400 and ⬃520 mV on p- and n-type substrates, respectively. In addition, a midgap interface state density of
⬃2 ⫻ 1012 cm−2 eV−1 was measured using ac-conductance
technique. Capacitance-voltage characteristics of the MOS
capacitors were monitored under different PDA and PMA
conditions in N2 ambient. The variations of frequency dispersion and capacitance equivalent thickness 共CET兲 of MOS
capacitors on p-type GaAs under different PDA and PMA
conditions are shown in Fig. 1共b兲. It is notable that the
Al2O3 / GaAs interface remains remarkably stable under different annealing conditions, as evidenced by the relatively
small increase of frequency dispersion at elevated PDA and
PMA temperatures compared to low PDA temperatures.
Considering the diminished frequency dispersion behavior of
capacitors annealed under PMA conditions with respect to
their PDA-treated counterparts, we surmise that outdiffusion
of As atoms could possibly be the major cause of this degradation. The reduction of CET at elevated temperatures
could stem from further densification of the Al2O3 gate dielectric. In addition, MOS capacitors on n-type GaAs
showed a similar trend in the improvement of CET. Therefore, the excellent thermal stability attribute of Al2O3 / GaAs
interface opens up the possibility to fabricate self-aligned
inversion-type e-mode GaAs nMOSFET.
Next, transfer and output characteristics of nMOSFETs
were probed, and a positive threshold voltage of 0.4 V was
determined by linear extrapolation technique. Furthermore,
e-mode GaAs nMOSFETs showed well-behaved transfer
characteristics, as illustrated in Fig. 2共a兲, where the subthreshold slope 共SS兲 and Ion / Ioff ratio were deduced to be
⬃145 mV/ dec and 105, respectively. The output characteristics of the MOSFET are shown in Fig. 2共b兲, where a maximum drive current of ⬃4.5 ␮A / ␮m at VGS-Vth of 2.5 V was
obtained for a gate length of 20 ␮m. From the slope of the
Id-Vd curves in the linear region, it is also evident that these
devices suffer from a relatively high S/D series resistance.
Thus, further improvement of drive current should be achievable by optimizing S/D ohmic contacts and implant/anneal
conditions. The inset of Fig. 3 illustrates the split C-V data
measured at 10 kHz, indicating the formation of an inversion
layer. Figure 3 shows the effective electron mobility extracted from the ID-VG 关Fig. 2共a兲兴, measured at a drain voltage of 50 mV, and the split C-V data, where the inversion
charge density was calculated by integrating the C-V data.
Despite the high intrinsic electron mobility of GaAs, the calculated mobility is lower than expected. The major culprit
for mobility degradation is unclear; however, the mobility
degradation can be somewhat attributed to the high density
of interface traps.
In summary, we have fabricated and characterized selfaligned inversion-type e-mode GaAs nMOSFETs using ALD
Al2O3 as the gate dielectric. The demonstration of inversiontype e-mode GaAs MOSFETs substantiates the effectiveness
of the ex situ chemical cleaning treatment of GaAs substrates
in improving high-␬ / GaAs interface. The stability of
Al2O3 / GaAs interface was examined at elevated temperatures, indicating good thermal stability of the interface. This
FIG. 2. 共a兲 ID-VGS and Gm-VG characteristics and 共b兲 ID-VDS characteristics
of an e-mode GaAs nMOSFET with a
gate length of 20 ␮m.
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203505-3
Appl. Phys. Lett. 92, 203505 共2008兲
Shahrjerdi et al.
5
FIG. 3. Effective electron mobility of the GaAs MOSFET was extracted
from the ID-VGS data shown in Fig. 2共a兲 and its corresponding split C-V data
共the inset兲. The split C-V data confirms the formation of inversion layer.
attribute of the interface rendered the fabrication of selfaligned e-mode GaAs MOSFETs possible. Despite the large
GaAs inherent electron mobility, the effective electron mobility of the MOSFET devices is small. We surmise that a
large interface state density at the Al2O3 / GaAs interface is
the primary cause of the relatively low mobility.
This work was partially supported by DARPA and Micron Foundation and NSF IGERT Grant No. DGE-054917.
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