JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
http://dx.doi.org/10.5573/JSTS.2014.14.5.625
Compact Power-on Reset Circuit Using a Switched
Capacitor
Kwang-Su Seong
Abstract—We propose a compact power-on reset
circuit consisting of a switched capacitor, a capacitor,
and a Schmitt trigger inverter. A switched capacitor
working with a clock signal charges the capacitor.
Thus, the voltage across the capacitor is increased
toward the supply voltage. The circuit provides a
reset pulse until the voltage across the capacitor
reaches the high threshold voltage of the Schmitt
trigger inverter. The proposed circuit is simple,
compact, has no static power consumption, and works
for a wide range of power-on rising times.
Furthermore, the clock signal is available while the
reset pulse is activated. The proposed circuit works
for up to 6 s of power-on rising time, and occupies a
60 ´ 30 μm2 active area.
Index Terms—Power-on reset circuit, switched
capacitor, oscillator, clock signal, power-on rising time
I. INTRODUCTION
Power-on reset (POR) is required to initialize
electronic systems or integrated circuits (ICs) when they
are turned on. The POR signal holds target circuits in the
reset state until the power supply voltage reaches a
steady-state level at which the target circuits can operate
correctly [1]. During the power-up transitional period,
memory elements in the circuits, such as flip-flops and
latches, should be properly initialized.
In [1, 2], a simple resistor-capacitor (RC) delay-type
Manuscript received Dec. 3, 2013; accepted Aug. 3, 2014
Department of Electronic Engineering, Yeungnam University, Korea
E-mail : kssung@ynu.ac.kr
POR circuit was analyzed. This simple conventional
POR circuit was built upon an RC delay element and a
Schmitt trigger inverter. The operation of the POR circuit
highly depends on the rise time of the supply voltage. If
the rise time is large compared to the RC time constant,
the reset time is not long enough to initialize target
circuits; i.e., the reset signal is inactivated before the
supply voltage reaches a desired voltage. The rise time is
on the order of tens or hundreds of milliseconds; thus, the
POR circuit requires large capacitance and resistance to
achieve proper delay. However, the large capacitance and
resistance prohibit the POR circuit from being
implemented on a chip because they require a large chip
area.
There are two approaches to solving the problem of
the conventional POR circuit. The first approach is to
increase the pulse width of the POR signal using delay
elements [1-3]. In Section II, the previous works in [1]
and [3] are described in detail. The second approach is to
generate a POR signal until the supply voltage reaches a
reference voltage that has been implemented in many
cases using bandgap reference circuits [4-6]. However,
previous approaches did not use a clock signal for
implementing POR circuits. The main purpose of a POR
circuit is to initialize memory elements such as flip-flops
and latches in the target circuits during the power-up
period. This means that a clock signal is available in the
target circuits, and the clock signal can be used to
implement a POR circuit.
In the proposed POR circuit, the property of a clock
signal is an important factor. When an oscillator is started,
it takes a finite length of time for its internal circuit
elements to reach their steady state. This start-up
transition causes oscillator period variations during the
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KWANG-SU SEONG : COMPACT POWER-ON RESET CIRCUIT USING A SWITCHED CAPACITOR
initial cycles after the oscillator is triggered [7]. A crystal
oscillator is widely used in many digital systems such as
micro-controller units (MCUs) and microprocessors.
Typically, it takes between a few milliseconds to tens of
milliseconds for a crystal oscillator to start [8]. However,
several methods have been proposed to reduce the startup time of the oscillator. For example, turn-on times were
improved to 10 μs and 250 μs in [8] and [9], respectively.
Even if a crystal oscillator has not reached its steady state
after excitation, the clock is close enough to its steadystate value to allow the system to work correctly [8]. In
Section 4, the clock signal of a commercial crystal
oscillator was observed during the power-on period. The
oscillator does not work until the supply voltage reaches
2.18 V (about 66% of the steady-state supply voltage).
After the supply voltage reaches the voltage level, the
oscillator starts to work and provides a clock signal
whose frequency is nearly the same as its steady-state
value. For these reasons, a crystal oscillator is
appropriate for the proposed POR circuit, and we assume
that the clock signal comes from a crystal oscillator.
The proposed POR circuit consists of a switched
capacitor, a picofarad-range capacitor, and a Schmitt
trigger inverter. The switched capacitor operating with a
clock signal charges the capacitor. Thus, the voltage
across the capacitor is increased toward the supply
voltage. The reset pulse is activated until the voltage
across the capacitor reaches the high threshold voltage of
the Schmitt trigger inverter. The proposed circuit is
simple, compact, and requires no static power
consumption. Furthermore, it ensures that the clock
signal is available while the POR signal is activated.
The static power consumption of a POR circuit can be
critical in battery-operated MCU applications, although
the static current is very small (as much as on the order
of a microampere). When a battery-operated low power
system is idle, the system enters into power saving mode,
wherein the clock signal is turned off to block dynamic
power consumption. If a system frequently enters into
power saving mode and the duration of the power saving
mode is quite long, the static power consumption can
greatly degrade the power performance of the system. A
typical example is an infrared (IR) remote controller that
is only used for short period of time and stays in power
saving mode most of the time.
Fig. 1 shows the timing diagram of supply voltage VDD
VDD
VDDF
Vosc
T0
Vmin
Time
Reset
TPORclk
VDDF
TPOR
Time
Fig. 1. POR timing.
and the reset signal. VDDF is the steady-state value of the
supply voltage, Vosc is the lowest supply level at which
the clock generator starts to work, and Vmin is the
minimum voltage of the supply, at which the reset switch
is turned on by the reset signal (i.e., the threshold of the
reset switch) [1]. T0 is the rising time of the supply
voltage, and TPOR is the reset time counted from the
moment when the reset switch turns on. TPORclk is the
clocked power-on reset time counted from the moment
when the oscillator starts to oscillate, and NPORclk is the
number of clock cycles in TPORclk. In this study, we will
focus on the clocked reset time TPORclk where the clock
signal is available and the supply voltage is higher than
Vosc. Thus, we can assume that the target circuits can be
properly initialized in this region.
The remainder of this paper is organized as follows.
Section II describes previous works. Section III explains
the proposed circuit and its behavior. Section IV
discusses our simulation results. Our conclusions are
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
given in Section V.
II. PREVIOUS WORKS
In this section, we review two recently published POR
circuits. In [3], a delay element for a POR circuit was
proposed. The circuit, shown in Fig. 2(a), consists of
three PMOS transistors and two capacitors. The
transistors, M1 and M2, are used during the power-on
period and M3 is used to discharge capacitors when the
power is turned off. M1 and two capacitors make M2
turned on weakly during the power-on period. Thus, M2
restricts current flowing into capacitor C2 and the circuit
has a long delay time. The strong points of this circuit are
627
that its structure is simple and compact, it has no static
power consumption, and it consumes nanowatt power
during the power-on period. However, the circuit cannot
precisely control the current flowing into capacitor C2.
Thus, the circuit only works for up to 10 ms of power-on
rising time.
In [1], a method to precisely control current flowing
into a capacitor was proposed. The POR circuit, shown in
Fig. 2(b), has a sub-nanoampere current source
consisting of three cascaded current mirrors and a current
generator. The current source charges a picofarad-order
on-chip capacitor C to achieve a long reset time. Thus,
the circuit works for up to 1 s of power-on rising time.
However, this method consumes static power. Even
though a sub-nanoampere current source is used to
charge the capacitor, the reference current IB is 1,000
times larger than the sub-nanoampere current source. The
total static current was reported as 1 μA in [1].
III. PROPOSED POR CIRCUIT
(a)
Fig. 3 shows the concept of the proposed POR circuit,
wherein switches SW0 and SW1 are mutually exclusive.
Thus, they are not turned on simultaneously. The control
signals for the switches are made from a clock signal that
comes from a crystal oscillator.
The operation of the circuit is as follows. The
capacitors are discharged to zero voltage before power is
supplied; i.e., the initial voltages of the capacitors are
zero. When the supply voltage reaches Vosc, the oscillator
starts to work, and the switched capacitor is also working.
Capacitor C0 is charged to VDD using switch SW0. Then,
the charges stored in capacitor C0 are transferred to
capacitor C1 using switch SW1. This process is repeated;
thus, the voltage of node 1 is increased toward VDDF.
(b)
Fig. 2. Previous POR circuits (a) in [3], (b) in [1].
Fig. 3. Concept of the proposed POR circuit.
628
KWANG-SU SEONG : COMPACT POWER-ON RESET CIRCUIT USING A SWITCHED CAPACITOR
signal:
TPORclk = N PORclk T .
Fig. 4. The proposed POR circuit.
The proposed POR circuit is shown in Fig. 4. The twophase clock generator makes control signals for M3 and
M2, which correspond to SW0 and SW1 in Fig. 3,
respectively. The control signals prevent switches M3 and
M2 from being switched on simultaneously. Capacitors
C0 and C1, shown in Fig. 3, were implemented using the
gate capacitances of M0 and M1, respectively. N-channel
metal oxide semiconductor (NMOS) M4 is for the rapid
discharge of capacitor C1 upon power-down. The Schmitt
trigger inverter used in [1] was adopted in this study.
Now we consider the circuit when the supply voltage
is a step function: VDD = VDDF u(t). The voltage of node 1
is expressed as Eq. (1) after the switched capacitor has
worked N times:
CV
C1
v1 ( N ) = 0 DDF +
v1 ( N - 1) .
C0 + C1 C0 + C1
(1)
The solution of Eq. (1) with the initial condition v1(0)
= 0 V is expressed as
N
æ æ C
ö
1
v1 ( N ) = ç1 - ç
÷
ç è C0 + C1 ø
è
ö
÷ VDDF .
÷
ø
(2)
The voltage of node 1 increases from zero toward VDDF
as N is increased. Here, NPORclk, shown in Eq. (3), is
defined as the lowest value satisfying v1(NPORclk) ≥ VTH
where VTH, the high threshold voltage of the Schmitt
trigger inverter, is expressed as VTH = kVDDF.
é
ù
ln(1 - k )
N PORclk = ê
ú.
ln(
C
/
(
C
+
C
))
1
0
1 ú
ê
(3)
Thus, the clocked power-on reset time TPORclk is
expressed as Eq. (4), where T is the duration of the clock
(4)
Our analysis results show that the clocked reset time is
determined by the ratio of the capacitances of the two
capacitors and the high threshold value of the Schmitt
trigger inverter. For example, if k = 0.8 and C0/C1 = 0.01,
then NPORclk becomes 162. This means that the reset
signal is valid for 162 clock cycles after the oscillator
starts to work; i.e., the clock signal and reset pulse are
simultaneously provided to the flip-flops and latches to
initialize them for 162 clock cycles. Thus, the memory
elements can be properly initialized in a synchronous
manner.
Eq. (4) can be approximately expressed as Eq. (5) with
the assumption that the ration of C0/C1 is very small,
where T/C0 is the effective resistance of the switched
capacitor and τ is the time constant of the circuit. Eq. (5)
shows that TPORclk is proportional to the time constant of
the circuit. Cases in which the rise time of the supply
voltage is not zero were analyzed using simulation in
Section 4.
TPORclk = N PORclk T » - ln(1 - k )
C1
T
C0
(5)
= - ln(1 - k )C1 Reff = - ln(1 - k )t .
The proposed method consumes a small amount of
dynamic power during the power-on period to charge
capacitor C1 using the switched capacitor. However, a
power-on event is very rare. Thus, the power
consumption during the power-on period is not a big
problem. The POR circuit also consumes a very small
amount of dynamic power in the steady state due to the
operation of the two-phase clock generator and the
switched capacitor if the clock signal is activated.
However, the POR circuit is not used as a stand-alone
system but used as a part of a digital system such as an
MCU or microprocessor. The dynamic power
consumption of the POR circuit is usually negligible
compared to the total power consumption of the digital
system. Static power consumption is an important factor
when a system is operated using a battery and is in power
saving mode, as mentioned in Section 1. The proposed
POR circuit is useful for battery-operated applications,
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
such as an IR remote controller, due to its zero static
power consumption.
IV. SIMULATION RESULTS
In the proposed POR circuit, the property of a clock
signal is an important factor as described in Section 1.
Before describing the simulation results of the proposed
POR circuit, the output of a commercial crystal oscillator
was observed during power-on period,
Fig. 5 shows the output of a 10 MHz commercial
crystal oscillator with a 3.3 V supply during the poweron period. The blue line is the output of the oscillator.
The yellow line is the supply voltage with a 10 ms rise
time. The oscillator does not work until the supply
voltage reaches 2.18 V (about 66% of the steady-state
supply voltage). After the supply voltage reaches the
voltage level, the oscillator starts to work and provides a
clock signal whose frequency is 10.01MHz, which is
nearly the same as its steady-state value. The property of
the crystal oscillator is suitable for the proposed POR
circuit, and we assumed that a crystal oscillator is used as
a clock source.
Now we will describe the simulation results of the
proposed POR circuit. The layout of the proposed circuit
was drawn using 0.35 μm CMOS technology as shown in
Fig. 6, and the post layout simulations were performed
for several different supply voltage rise times. The size of
the layout occupies 60 ´ 30 μm2. The size of M0 in Fig. 4,
whose gate capacitance corresponds to C0 in Fig. 3, was
set to the smallest size to make the ratio C0/C1 low. The
size of M1, whose gate capacitance corresponds to C1,
was set to 2 pF. The operating frequency of the clock
signal was set to 1 MHz, and the minimum voltage for
the oscillator to work, Vosc, was set to 0.7VDDF. The high
threshold voltage of the Schmitt trigger inverter, VTH, was
set to 0.81VDDF.
Fig. 7 shows the simulated transient response of the
circuit (shown in Fig. 4) with a power-on event, wherein
the power supply voltage VDD increases from 0 to 3.3 V
with a rising time of T0 = 2 ms. The initial voltages of
node 0 and node 1 were assumed to be fully discharged
at GND. The voltage of node 1 remains nearly zero until
the oscillator starts to work. After the supply voltage
reaches Vosc, the oscillator starts to work and provides a
clock signal to the circuit. The switched capacitor,
Fig. 5. Output of crystal oscillator during power-on period.
Fig. 6. Layout of the proposed POR circuit (60 ´ 30 μm2).
Fig. 7. Simulation results for T0 = 2 ms.
629
630
KWANG-SU SEONG : COMPACT POWER-ON RESET CIRCUIT USING A SWITCHED CAPACITOR
Clocked power-on reset time TPORclk (ms)
550
V. CONCLUSION
500
We propose a compact power-on reset circuit using a
switched capacitor that replaces the resistor in a RC
delay-type POR circuit. The proposed circuit works for
up to 6 s of power-on rising time and occupies a 60 ´ 30
450
400
350
300
250
200
150
100
50 1
10
2
10
3
4
10
μm2 active area. The circuit can be especially useful for a
battery-operated low cost micro-controller unit (MCU),
such as an infrared remote controller, due to its zero
static power consumption, compact size, and wide
power-on rise time response range.
10
Power-on rising time T0 (ms)
REFERENCES
Fig. 8. TPORclk versus the rise time of the supply.
[1]
Table 1. Performance summary and comparisons
Proposed circuit
Process
[1]
[3]
CMOS 0.35 μm CMOS 0.18 μm CMOS 0.5 μm
Supply (V)
3.3
1.8
1.8 to 5.0
Power-on rising
time (ms)
≤ 6,000
≤ 1,000
≤ 10
Static power
No
1 μA
No
Brown-out
detection
No
Yes
No
Active size (μm2)
60 ´ 30
120 ´ 100
[2]
35 ´ 35
[3]
working with the clock signal, charges node 1 from zero
toward VDDF. The reset pulse is activated until the voltage
of node 1 reaches 2.67 V, corresponding to the high
threshold voltage of the Schmitt trigger inverter.
Fig. 8 shows the clocked power-on reset time TPORclk
with respect to the rise time of the supply. As the value of
TPORclk is directly related to NPORclk as described by Eq. (4),
we can also directly obtain NPORclk from Fig. 8. The
proposed POR circuit provides enough clocked power-on
reset time when the rise time is short. However, the
clocked reset time decreases as the rise time is increased
due to the leakage current flowing into capacitor C1. The
proposed circuit works for up to 6 s of power-on rising
time. However, TPORclk decreased to 56 μs, which
corresponds to 56 clock cycles of NPORclok when T0 is 6 s.
A performance summary and comparisons are
provided in Table 1. The proposed method is compact,
works across a wide range of power-on rising times, and
has no static power consumption.
[4]
[5]
[6]
[7]
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[8]
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631
Kwang-Su Seong received the B.S.
degree in electronic engineering from
Hanyang University, Seoul, Korea in
1990, and the M.S. and Ph.D.
degrees in electrical engineering
from the Korea Advanced Institute of
Science and Technology (KAIST),
Daejeon, Korea, in 1992 and 1997, respectively. He is
currently an Associate Professor with the Department of
Electronic Engineering, Yengnam University, Gyeongbuk,
Korea. His current research interests include capacitive
sensors, MCU design, and wireless power transmission
for mobile devices.