LECTURE SUPPLEMENT #3
PN Junction Diode
Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
213–740–7581 [USC Fax]
818–384–1552 [Cell]
johnc@usc.edu
PRELUDE:
The fundamental physical properties, volt-ampere characteristics, and circuit level models of the
PN junction diode comprise the subject matter of this chapter. While PN junction diodes are
commonly fabricated in either silicon or germanium semiconductor technologies, most of the
disclosures in this chapter focus on silicon diodes. Also discussed are a few practical applications of the diode, including half wave and full wave rectifiers, logarithmic amplifiers, and
limiters.
February 2008/January 2011
Lecture Supplement #3
PN Junction Diode
J. Choma
2.1.0. INTRODUCTION
The semiconductor PN junction diode is the simplest of solid state circuit elements. Its
simplicity belies its critical importance to the state of the electronics art since an understanding
of the physical properties and operational mechanisms of a junction diode facilitates engineering
comfort with the operation and general behavior of more complex electronic devices, such as the
bipolar junction transistor (BJT) and the metal-oxide-semiconductor field effect transistor
(MOSFET). However, the diode is more than a mere stepping stone to more complex electronics
in that it boasts utility in numerous practical applications. Included among these applications are
stable voltage references that sustain reasonably constant voltages in the face of temperature increases and power supply variations. Yet another common application of the diode entails the
conversion of periodic voltage waveforms having zero average values to unidirectional energy
exuding nonzero average voltage levels. This conversion capability is foundational to the necessity of having to transform the alternating line voltages supplied to private and commercial
establishments by local power companies to the constant voltages required for biasing electronic
systems.
Figure (2.1a) is a simplified physical representation of a PN junction diode, while Figure (2.1b) depicts its electrical schematic symbol. The diode is seen as a homogeneous physical
structure formed by p-type and n-type semiconductor crystals, such that at the common physical
boundary of these crystal volumes, which is termed the semiconductor junction, an almost
abrupt transition from p-type -to- n-type semiconductor is formed. The p-type region is doped
with acceptor impurities at an average concentration of NA (in units of atoms -per- cm3), while
the n-type volume has an average donor impurity concentration of ND. Although the impurity
concentration profiles in either diode region are rarely constant, independent of position variable
x in the diagram, the salient features of diode operation can be gleaned by assuming that these
doping concentrations are constant at their respective average values, or at least at some
appropriately corrected average values. The thickness of the p-region is noted as Wp, while that
of the n-type crystal is Wn. On the other hand, dimensions L and H define the cross section junction area, say Ae, as Ae = LH. This metric is the area of the junction cross section pierced orthogonally by the diode current, id(t), which flows in response to an applied diode voltage, vd(t).
Note that id(t) is postured as a positive current that flows from the p-type region to the n-type region, while vd(t) is considered a positive voltage when it raises the potential of the p-side of the
junction above that of the n-side.
Assuming complete ionization of both impurity dopants, the concentration of free, and
therefore mobile, hole charge on the p-side of the junction is qNA, where q is the magnitude of
electron charge. On the n-side of the junction, the concentration of mobile electron charge is
−qND. When the diode in question is connected into a circuit that renders vd(t) > 0, the diode is
said to be forward biased. Under this biasing condition, the injection of free electrons from the
n-type region, across the semiconductor junction, and into the p-type volume is encouraged.
Since the time rate of change of charge through a cross section constitutes a current and since
electrons carry negative charge, this electron injection manifests a positive diode current; that is
a current whose direction of flow mirrors that of the indicated diode current, id(t). Simultaneously, free holes from the p-type volume are transported across the junction into the n-type crystal. The positive nature of transported hole charge therefore gives rise to a diode current whose
direction matches the current ramifications of electron transport across the semiconductor junction. In short, a diode that operates in its forward bias regime can conduct potentially large currents because of the simultaneous injection of majority charge (charge due to electrons from the
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PN Junction Diode
J. Choma
n-type region and charge due to holes from the p-type volume) across the device cross section
identified as the diode junction.
+ vd (t) −
Junction
tal
Me tact
n
Co
H
L
id (t)
x
−Wp
0
Wn
(a).
id (t)
+ vd (t) −
(b).
Figure (2.1). (a). Physical abstraction of a PN junction semiconductor diode. (b). Electrical schematic symbol of the PN junction diode.
In contrast to forward diode biasing, the reverse biased diode, which is tantamount to
vd(t) < 0, moves free electrons further away from the junction and toward the metal contact at the
end of the n-type region. The negative diode voltage also attracts free holes away from the junction and toward the metal contact at the end of the p-type volume. Reverse biasing is therefore
seen as inhibiting majority charge injection across the semiconductor junction, thereby ensuring
ideally zero current conduction through the diode. In practice, the reverse biased diode current,
id(t), is not quite zero and is actually nominally constant at the negative value, −Io, where Io is
known as the diode saturation current. The latter current parameter is alternatively referred to
as the diode leakage current, which correctly intimates the desirability of zero current conducted
by a reverse biased junction diode. In short, diode current id(t) is nonzero and specifically, id(t) ≈
−Io for values of reverse biased diode voltage that are reasonable in the sense that they do not exceed device breakdown limitations.
In contrast to the forward biasing current resulting from the injection of majority charge
across the semiconductor junction, the reverse biased current addressed in the preceding paragraph is precipitated by the injection of minority charge across the junction. This is to say that
vd(t) < 0 supports the injection across the junction of electrons from the p-type region to the ntype domain, as well as the injection of holes from the n-type volume to the p-type region.
While the preponderance of mobile charge in the p-type region of the diode derives from free
holes, the concentration of electrons, which are the minority charge carriers in the p-type region,
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is assuredly not zero. A minority charge concentration prevails since the product of free hole
and free electron concentrations is the square of the intrinsic carrier concentration, say ni, which
a constant, dependent only on regional temperature. This constant product of hole and electron
concentrations implies that a progressively larger free hole population begets a proportionately
smaller free electron concentration and vice versa. Similarly, the injection of holes across the
junction from the n-type region is promoted by diode reverse biasing [meaning vd(t) < 0], with
the understanding that the concentration of these minority carriers is inversely proportional to the
concentration of free electrons on the n-side of the junction.
2.2.0. PN JUNCTION DIODE FUNDAMENTALS
The reader may recall that his or her initial foray into the wonderful world of electrical
circuits likely initiated with a stipulation of Ohm’s law, which effectively defined the voltampere characteristics of a simple two terminal resistor. Coalescing this trivial volt-ampere
relationship with a few fundamental circuit theory concepts, such as the Kirchhoff laws and
superposition theory, enabled the reader to compute the branch currents and voltages established
by one or more energy sources applied to memoryless networks; that is, circuit structures that are
architecturally divorced of capacitances and inductances. In somewhat of an analogous fashion,
the reader’s introduction into the magical world of electronic circuits is a disclosure of the low
frequency volt-ampere properties of the semiconductor PN junction diode. This volt-ampere
characteristic equation is more complex than is Ohm’s law, if for no other reason than the junction diode is an inherently nonlinear branch element. When coupled with classic circuit theories
and such fundamental semiconductor concepts and issues as the junction depletion region, junction transition capacitance, diode diffusion capacitance, built-in junction potential, and charge
transport and injection, the diode volt-ampere model enables the creative exploitation of the PN
junction diode in numerous applications, inclusive of those circuits and systems boasting memory elements. It also helps to forge an insightful understanding of basic semiconductor principles.
2.2.1. VOLT-AMPERE CHARACTERISTIC
If the diode depicted in either of the two diagrams of Figure (2.1) is inserted in a network that is excited by only low frequency voltages or currents, the diode current, id(t), relates to
the diode voltage, vd(t), in accordance with the nonlinear expression,
id (t) = I o ⎡ evd (t) nVT − 1⎤ ,
(2-1)
⎣
⎦
where the current, Io, is the diode saturation current introduced earlier in the context of diode reverse biasing. Note, in fact, that if vd(t) is strongly negative, (2-1) projects id(t) ≈ −Io, as discussed previously. In (2-1), parameter n, which is known as the junction injection coefficient, is
ideally one and rarely larger than about 1.2. Moreover, the Boltzmann voltage, VT, is
kT
VT =
,
(2-2)
q
where k = 1.38(10−23) joules/°K is Boltzmann’s constant, T is the absolute temperature (measured in degrees Kelvin) of the semiconductor junction, and q = 1.6(10−19) coulombs is the
magnitude of electron charge. At T = 27 °C = 300.16 °K, VT = 25.89 mV, or about 26 mV. A
temperature of 27 °C is traditionally adopted as the reference temperature for electronic circuit
analyses. It is often referred to as “room temperature,” even though 27 °C is equivalent to a very
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PN Junction Diode
J. Choma
warm room held at a temperature of about 81 °F. It can be argued, however, that the internal
junction of a diode, which endures the power dissipation stress imposed by high current densities, operates at temperatures of at least 10 °F -to- 15 °F above room ambient.
2.2.1.1. Static Volt-Ampere Model
Under static (“DC”) or low signal frequency operating conditions, the time dependence
of the diode voltage, vd(t), in (2-1) can be represented by simply a time-invariant voltage, Vd.
Correspondingly, the diode current, id(t), can be supplanted by the constant current notation, Id.
Accordingly,
)
(
I d = I o eVd nVT − 1 ,
(2-3)
50
Germanium
Diode
Diode Current, Id (mA)
40
Silicon
Diode
30
20
10
0
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Diode Voltage, V d (volts)
Figure (2.2). The room temperature volt-ampere characteristics of representative PN junction diodes fabricated in silicon and germanium solid state technologies. Both diodes have
an injection coefficient of n = 1. The silicon diode has a room temperature saturation
current of 2 fA, while its germanium companion has a saturation current of 1 μA.
which is plotted in Figure (2.2) for representative silicon and germanium PN junction diodes
operated at 27 °C. The saturation current, Io, of the silicon diode in Figure (2.2) is 2 fA, while the
corresponding saturation current for the germanium unit is 1 μA. For both diodes, parameter n is
taken to be unity. The huge disparity between Io values of silicon and germanium diodes is not
unusual. Commonly, parameter Io for a germanium PN junction diode whose geometric and
dopant characteristics are comparable to a given silicon diode is eight to ten orders of magnitude
larger than the silicon diode Io value. Observe that in both the silicon and germanium samples,
the diode current remains essentially zero despite positive, but small, values of the diode voltage.
For the subject germanium device, significant current is not observed until its diode voltage
reaches a level of nominally 200 mV, which might be interpreted as a “turn on” voltage, say Von,
for the device. On the other hand, about 700 mV of forward bias turn on is required to effect
significant current flow in the silicon unit. These differences in the diode voltage commensurate
with observable current flow can be attributed directly to the drama prevailing with respect to
differences in the respective saturation current values of the two diodes.
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J. Choma
Observe further that large diode currents do not require diode voltages that are significantly larger than their turn on levels. For example, Figure (2.2) confirms that the difference in
voltage of the silicon diode biased at nominally 1 mA and then operated at roughly 50 mA is less
than 100 mV, or only about 14% of the 1 mA value of forward diode voltage. In other words, minutely small increases in diode voltage result in significant increases in diode current, which is to
say that the diode current is a sensitive function of forward biasing diode potential. Arguably,
the forward diode voltage can therefore be viewed as remaining essentially constant at its turn on
value for reasonably significant increases in diode current. In an idealized sense, it might be suggested that the electrical behavior of a forward biased PN junction diode approximates the voltampere characteristics of a battery whose potential is the diode turn on voltage, Von. For both
forward and reverse biases, the situation at hand is reminiscent of the biased electrical switch
diagrammed and characterized in Figure (2.3). In particular, the switch in the subject figure is
open, whence switch current Isw is zero, for Vsw ≤ Von, while Isw ≥ 0 for Vsw = Von.
Von
−
+
Isw = 0
Isw
Vsw ≤ Von:
Switch Open
+ Vsw −
Von
−
+
Isw ≥ 0
Vsw = Von:
Switch Closed
+ Vsw −
Von
Vsw
Figure (2.3). Biased switch emulation of the volt-ampere characteristics of a PN junction diode.
The switch emulation posited in the preceding paragraph can be refined to account, albeit to first order, for the finite slope of the diode forward characteristic. To this end, consider
Figure (2.4), which depicts a typical volt-ampere characteristic of a diode, regardless of the
semiconductor technology exploited in its fabrication. Assume that the diode in question is inserted into a circuit that allows a nominal, or perhaps maximum, diode current of Idm to flow.
From (2-3), this current corresponds to a forward diode voltage, Vdm, in concert with
(
)
I dm = I o eVdm nVT − 1 ≈ I o eVdm nVT ,
(2-4)
where the approximation reflects the fact that the exponential term in the bracketed quantity is
significantly larger than unity when the diode is forward biased. Let a straight line be passed
through the coordinate, (Idm, Vdm), such that the subject line is tangent to the diode characteristic
at (Idm, Vdm). This slope, which has units of conductance or equivalently, inverse resistance, can
logically be designated by the inverse resistance notation, 1/rdm. Returning to (2-3),
1
rdm
dI d
I eVd nVT
I eVdm nVT
I
= o
= o
≈ dm ,
dVd V =V
nVT
nVT
nVT
Vd =Vdm
d dm
(2-5)
whence
nVT
.
(2-6)
I dm
The diode resistance in (2-6) is nominally inversely proportional to the diode current. It therefore becomes progressively smaller as diode currents increase. Indeed, it is quite small for both
rdm ≈
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moderately large and relatively small currents owing to the fact that the numerator term, nVT, on
the right hand side of (2-6) is only about 26 mV at room temperature. Physically, it represents
the ratio of an incrementally small change, ΔVd, in the diode voltage -to- an incrementally small
perturbation, ΔId, in corresponding diode current in the immediate neighborhood of the voltampere coordinate, (Idm, Vdm).
Diode Current
Actual Diode
Characteristic
I dm
Piecewise Linear
Characteristic
Diode Voltage
V on
V dm
Figure (2.4). Piecewise linear approximation of the forward PN junction diode volt-ampere
characteristic.
It follows that the equation of the straight line passed through the aforementioned voltampere coordinate is
1
I d = I dm +
(2-7)
(Vd − Vdm ) .
rdm
The straight line intersects the horizontal axis in Figure (2.4) at Vd = Von, which in concert with
the preceding discussion about modeling a diode with a biased switch, can be viewed as a
meaningful quantification of the turn on voltage of the diode. Since Id = 0 in the present context
of Vd = Von, (2-7) and (2-6) provide
Von = Vdm − rdm I dm ≈ Vdm − nVT .
(2-8)
Note that the turn on voltage differs from the operating voltage, Vdm, of interest by a mere 26 mV
or so at room temperature, which attests further to the pronounced sensitivity of diode current to
forward diode voltage.
It should be understood that (2-7) is a meaningful approximation of the volt-ampere
characteristics of a PN junction diode only if the diode voltage, Vd, is at least as large as the voltage, Von, given by (2-8). Otherwise, the diode current is taken to be zero, which is an analytical
tack that ignores the small diode currents that flow for small positive values of diode voltage, as
well as the leakage current manifested when the diode is reverse biased. These pronouncements
lead to the piecewise linear approximation sketched in Figure (2.4), wherein a zero slope line,
coincident with the voltage axis, intersects a second line, defined analytically by (2-7), at Vd =
Von. Specifically, the piecewise linear diode curve approximation is
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0, for Vd ≤ Von
Id ≈
.
(2-9)
1
I dm +
(Vd − Vdm ) , for Vd ≥ Von
rdm
Since each constituent of (2-9) is a linear equation, each postures a linear equivalent circuit for
the diode undergoing study. The equivalent circuit for the case of Vd ≤ Von is trivial in that it is
merely an open circuit, as shown in Figure (2.5a). With Vd ≥ Von, a constant current source, a
constant voltage source, and a resistance are required as diagrammed in the topology offered as
Figure (2.5b).
Id = 0
Vd ≤ Von
+ Vd −
+ Vd −
Id
Vd ≥ Von
+ Vd −
rdm
+
−
Id
Idm
(a).
Vdm
Id
+ Vd −
(b).
Figure (2.5). Piecewise linear model of the PN junction diode. (a). The piecewise linear
model corresponding to a diode voltage that is at most equal to the turn on
voltage of the device. (b). The piecewise linear model for a diode voltage
that is at least the diode turn on voltage.
EXAMPLE #2.1:
In the simple circuit of Figure (2.6a), the PN junction diode, D, is fabricated in silicon technology and operates at room temperature. Its static
volt-ampere curve is characterized by a junction injection coefficient of n
= 1.03 and a saturation current of Io = 4.2 fA. The battery voltage applied
to the circuit is Vdd = 3 V, while the load resistance is Rl = 150 Ω. Use the
piecewise linear model of a diode to calculate the diode current, Id, the diode voltage, Vd, and the load voltage, Vl.
SOLUTION #2.1:
(1).
The polarization of the supply voltage, Vdd, serves to forward bias the diode in the circuit at hand. Accordingly, the model of record is the structure in Figure (2.5b), which
supplants diode D in the circuit of Figure (2.6a) to forge the network given in Figure
(2.6b). The use of this model begins with an estimation of the maximum current, Idm,
which the diode in Figure (2.6a) conducts. A reasonable first guess of this maximum
current is Vdd/Rl, which effectively is the current that would flow if the diode were to
behave as a short circuit; that is, a diode boasting zero turn on voltage and infinitely
large slope of the forward volt-ampere characteristic curve. But PN junction diodes
have a nonzero turn on voltage commensurate with the conduction of measurable current. In silicon, a reasonable approximation of the diode turn on voltage is Von = 700
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Idm
mV. Thus, a better second guess as to the maximum current the circuit of Figure
(2.6a) is capable of conducting is
Vdd
+
Vd
−
Rl
−
Vl
+
Vdd
rdm
−
+
−
+
Id
Vl
Vdm
D
Id
Rl
+ Vd −
(a).
(b).
Figure (2.6). (a). Circuit addressed in Example (2.1). (b). The piecewise linear model for the
circuit in (a).
Vdd − Von
(E1-1)
= 15.33 mA .
Rl
The diode voltage, Vdm, corresponding to this estimated maximum current is, from (24),
⎛I
⎞
Vdm = nVT ln ⎜ dm + 1 ⎟ = 771.32 mV .
(E1-2)
⎝ Io
⎠
The unity term within the parenthesized factor on the right hand side of the last equation can be ignored comfortably in that Idm >> Io. Finally, (2-6) gives for the series
diode resistance, rdm,
nVT
(E1-3)
rdm =
= 1.74 Ω .
Im
I dm =
(2).
Kirchhoff’s current law applied to the equivalent circuit in Figure (2.6b) yields a diode current, Id, which satisfies
V − Vdm − Rl I d
(E1-4)
I d = I dm + dd
,
rdm
whence
⎛ rdm ⎞
Vdd − Vdm
= 14.86 mA .
Id = ⎜
(E1-5)
⎟ I dm +
rdm + Rl
⎝ rdm + Rl ⎠
The load voltage, Vl, follows as
Vl = Rl I d = 2.23 V ,
(E1-6)
while the diode voltage, Vd, is necessarily
Vd = Vdd − Vl = 770.51 mV .
(E1-7)
COMMENTS: Two noteworthy points surface from this example. The first is that while
the piecewise linear model is an approximation in that it effectively supplants the forward bias diode volt-ampere curve by a straight line, it
nonetheless is capable of reassuringly accurate computations. In the present case, a computer-based simulation of the network in Figure (2.6a)
reveals a diode voltage of 770.49 mV, which implies that the computed result is larger by a scant 0.002%. The same simulation confirms that the
computed current is high by only 0.015%. These errors are orders of
magnitude smaller than the response errors accruing from the
ramifications of routine processing vagaries and manufacturing tolerances.
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mate adopted for the current, Idm. In particular, the closer Idm is to the actual diode current, the more accurate are the computed results. Equation
(2-7) supports the last contention, for in the limit if Idm is estimated to be
the actual diode current, Id, Vdm follows as the actual diode voltage, Vd.
The second point is that the obviously nonlinear electronic circuit at hand
has been analyzed accurately with the help of only a linear, albeit approximate, circuit model. The lesson herewith is that traditional linear circuit
theory and analytical techniques are crucially important to an analytical
assessment of electronic networks. Specifically, once a meaningful model
is contrived for the active, nonlinear element (or elements in more complicated networks), electronic circuit investigations collapse to sophomoric
circuit analysis.
2.2.1.2. Diode Saturation Current
The saturation current parameter, Io, embodies at least two important properties that
influence design practices for electronic networks exploiting BJT, MOSFET, and, of course, diodes. The first of these characteristics is that Io is directly proportional to the area, Ae, of the
semiconductor junction. Thus, if the same voltage, vd(t), is applied across two PN junction
diodes that are identical, save for the fact that the junction cross section area of one device is larger than that of the other by a factor of K, the larger diode necessarily conducts K-times the current that flows through the smaller diode. This declaration presumes that the passive series resistances (generally termed ohmic resistances) associated with the doped p-type and n-type layers
incur potential drops that are significantly smaller than the observed diode voltage.
In Figure (2.7), for example, a constant voltage source, Vdd, drives a simple circuit comprised of the series interconnection of resistance R and the shunt connection of two PN junction
diodes, D1 and D2. Because the two diodes are connected in parallel with one another, they
share the same forward biasing voltage, vd(t) = Vd, where the time dependence notation of diode
voltage (as well as diode current) is dropped to reflect the exclusively static nature of the applied
voltage, Vdd. If the junction area of D2 is K-times larger than that of diode D1, the current conducted by D2 is KId1, where Id1 is the indicated static current flowing through D1. Consequently,
the steady state current conducted by resistance R and the supply voltage is (K+1)Id1, which
keeps Kirchhoff content.
R
(K+1)Id1
+
Vd
D1
Vdd
−
D2
xK
Id1
KId1
Figure (2.7). Simple circuit involving two PN junction diodes
connected in shunt with one another. The junction area of diode D2 is K-times larger than the
junction cross section area of diode D1.
The linear dependence of saturation current on diode junction area boasts design utility
in situations for which reasonably accurate control of diode current is mandated. Attempts at setting the diode current predictably and reproducibly through adjustments in diode voltage are
fraught with peril. The problem at hand is the previously observed extreme sensitivity of diode
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current to diode voltage. As a demonstration of this pronounced sensitivity, assume a diode having Io = 1.5 fA, n = 1, and a room temperature value of Boltzmann voltage VT. Then for Vd/nVT
= 30, which corresponds to forward biasing in the nominal amount of 777 mV, (2-3) delivers Id =
16.03 mA. On the other hand, for Vd/nVT = 31, which increases the forward bias voltage by a
mere 3.33% to about Vd = 802.6 mV, Id = 43.57 mA. This current calculation reflects an
astonishing 171.8% increase in current!
Fortunately, the junction area of a monolithic PN junction diode is a designable
parameter, thereby affording convenient controllability of diode current. This fact and the linear
dependence of parameter Io on junction area conveniently allows for setting the relative currents
conducted by two identically biased diodes through suitable constraints imposed on the junction
areas of the two devices. Apart from convenience, this design tack also renders relative currents
highly predictable for despite routine processing vagaries, relative junction areas in monolithic
processes can be typically controlled to better than ±5%.
In contrast to the design-oriented advantage of saturation current proportionality to
junction area, Io exudes a troublesome temperature sensitivity that is the bane of integrated circuit designers. Current Io is, in fact, the leakage current that flows through a reverse biased diode. This leakage derives from minority charge carriers injected across the diode junction.
Because the concentration of these injected minority carriers is directly proportional to the
square of the intrinsic carrier concentration, which rises dramatically with increases in junction
operating temperature, the leakage current is itself strongly dependent on junction operating
temperature. Accordingly, diode currents exude a positive temperature coefficient; that is, these
currents tend to increase over temperature, because of the dependence of current parameter Io on
junction temperature.
To first order, the mathematical nature of the temperature dependence of Io can be addressed empirically by the expression,
T −To ) 10 ⎤
I o (T) ≈ I o (To ) ⎡ P (
,
(2-9)
⎢⎣
⎥⎦
where To is a reference temperature that is generally taken to be 27 °C, Io(T) is the leakage current at temperature T, Io(To) is the leakage current at the reference temperature, and P is an
empirical temperature parameter in the range of 2 -to- 5 for silicon devices. Equation (2-9) asserts that the leakage current can be expected to increase by a factor of nominally P for every 10
°C rise in junction operating temperature. Thus, for example, if P = 3.5, the leakage or saturation current, Io(T), at a temperature that is 50 °C above room temperature is a factor of 525.2 larger than its reference temperature value. In the context of the circuit in Figure (2.7), suppose that
the voltage, Vd, is maintained constant over a 50 °C temperature increase. The resultant current
conducted by resistance R would increase by a factor of 525.2, which means that the supply voltage, Vdd, and thus the power it must supply to the circuit, would need to be increased commensurately over temperature to sustain the desired reference temperature value of diode voltage.
The disconcerting aspect of the foregoing example is that while a 50 °C rise in junction
temperature is large, it is a common increase when small geometry devices are compelled to conduct moderately large currents, albeit for brief intervals of time. In particular, the high current
densities experienced by small profile diodes incur substantive self-heating of their respective
junctions. This state of affairs compels the use of relatively large geometry diodes when
correspondingly large currents must be conducted. In particular, larger cross section areas reduce current densities, which in turn mitigate rapid junction temperature rises incurred by
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unavoidable self heating. Just as a high gauge (small cross section area) extension cord becomes
dangerously hot when it connects a power hungry appliance, such as a toaster or space heater, to
a power source, small geometry diodes conducting large currents can likewise be damaged by
the internal heat deriving from the junction power dissipation associated with large current densities.
A casual inspection of (2-3) suggests the need of appropriately decreasing the diode
voltage to compensate for temperature-induced increases in the saturation, or leakage current
parameter, Io. In order to ascertain the amount of requisite voltage decrease that sustains nominally constant diode current, assume a PN junction diode energized by a static voltage that
secures strongly forward biased operation. In this case, the exponential term on the right hand
side of the subject relationship overpowers the unity term in the bracketed quantity so that at
temperature T,
I d (T) ≈ I o (T)eVd (T) nVT ,
while at reference temperature To,
(2-10)
I d (To ) ≈ I o (To )eVd (To ) nVTo ,
(2-11)
where
kTo
(2-12)
q
is the reference temperature value of the Boltzmann voltage. Since the goal of the present exercise is to determine the amount by which the forward bias diode voltage, Vd(T), must change
from its reference value, Vd(To), to ensure that the diode current at temperature T is the same as
the current at temperature To, Id(T)/Id(To) = 1. Accordingly, the division of (2-10) by (2-11) and
subsequent use of (2-3) delivers
⎡V (T) Vd (To ) ⎤
(2-13)
1 = P ΔT 10 exp ⎢ d
−
⎥,
nVTo ⎦
⎣ nVT
where
ΔT T − To
(2-14)
is the temperature change of interest. Equations (2-12) and (2-13) and a bit of algebra invoked
on the bracketed term on the right hand side of (2-13) allows (2-13) to be rewritten in the form,
⎧⎪⎛ 1 ⎞ ⎡
⎤ ⎫⎪
ΔT
1 = P ΔT 10 exp ⎨⎜
Vd (To )⎥ ⎬ ,
(2-15)
⎟ ⎢ ΔVd −
To
⎦ ⎭⎪
⎩⎪⎝ nVT ⎠ ⎣
VTo =
(
)
(
)
with
ΔVd Vd (T) − Vd (To )
(2-16)
understood to represent the requisite change in diode voltage. Upon taking the natural logarithm
of both sides of (2-15),
ΔVd
V (T )
= d o − nVT ln P 1 10
(2-17)
ΔT
To
is readily demonstrated.
(
)
The quotient, ΔVd/ΔT, in (2-17) can be interpreted to be the average temperature rate at
which diode voltage Vd must change to preserve constant diode current over the temperature
range, ΔT. Observe that even if P = 1, which implies that saturation current Io(T) is not influenced by temperature, ΔVd is not zero and is indeed a positive number for ΔT > 0. This situation
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reflects the simple fact that for progressive increases in junction temperature, the Boltzmann
voltage, VT, in (2-2) increases linearly with temperature, thereby mandating a proportional increase in diode voltage if constant diode current is to be sustained. For P > 1, the second term
on the right hand side of (2-15) is invariably larger than the first term so that ΔVd/ΔT is a negative number in units of volts -per- °C. The typical magnitude of this voltage sensitivity for silicon PN junction diodes is in the range of 1.5 mV/°C -to- 5 mV/°C.
Figure (2.8) portrays the pronounced temperature sensitivity of the static volt-ampere
characteristic of a PN junction diode. The curves displayed plot (2-3) for a 27 °C saturation current value of Io(To) = 2 fA, a junction injection coefficient of n = 1, and a temperature parameter
of P = 3.5. The plot clearly conveys the necessity of a decrease in junction voltage, Vd, if the diode current, Id, is to be maintained constant in the face of increasing junction temperature.
100
90
80
Diode Current, Id (mA)
70
60
50
T = 125 °C
T = 75 °C
40
30
20
T = 27 °C
10
0
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Diode Voltage, V d (volts)
Figure (2.8). The volt-ampere characteristic of a PN junction diode for three values of junction
temperature. The considered diode has n = 1, a reference temperature (27 °C)
saturation current of 2 fA, and P = 3.5.
EXAMPLE #2.2:
In the circuit of Figure (2.7), diode D1 has a saturation current, Io, of 5 fA
at room temperature. Diode D2 is identical to D1 except that its junction
area is 5-times larger than that of D1. Both diodes have a junction injection coefficient of n = 1 and a temperature factor of P = 4. The applied
voltage, Vdd, is 6 volts and supplies 18 mA of current to the circuit. What
is the required value of resistance R, and what is the average rate at which
Vdd must decrease if the current supplied by Vdd is to remain 18 mA when
the diodes operate at 100 °C. Assume that temperature-induced changes
in the value of circuit resistance are negligible.
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SOLUTION #2.2:
(1).
If the supply voltage provides 18 mA of current to the circuit of Figure (2.7), and if diode D2 has a junction area that is 5-times the area of D1 (K = 5), diode D1 must conduct a current of Id1 = 18 mA/(K+1) = 18 mA/6 = 3 mA. From (2-3), the voltage,
Vd(To), developed across either diode is, for Id1(To) = 3 mA, Io(To) = 5 fA, n = 1, and
To = 27 °C,
⎛ I (T )
⎞
(E2-1)
Vd (To ) = nVTo ln ⎜ d 1 o + 1 ⎟ = 702.11 mV .
⎝ I o (To )
⎠
(2).
Kirchhoff’s voltage law applied to the lone circuit loop in the subject figure yields
V − Vd ( To )
(E2-2)
R = dd
= 294.33 Ω .
( K + 1 )I d 1(To )
(3).
Since resistance R boasts zero temperature coefficient, the decrease in supply voltage
must match the decrease in the diode voltage commensurate with maintaining constant current supplied by the voltage source. With Vd(To) = 702.11 mV, P =4, To =
300.16 °K, and a maximum operating temperature of T = 100°C = 373.16 °K, (2-17)
provides
ΔVdd
ΔVd
V (T )
(E2-2)
≡
= d o − nVT ln P 1 10 = − 2.123 mV/°C .
ΔT
ΔT
To
This computation implies that over the temperature range of 27 °C -to- 100 °C, the
supply voltage must diminish by (−2.123)(100 − 27) = 154.96 mV, which amounts to
a decrease of 2.58%.
(
)
COMMENTS: The bad news is that diode currents are strongly sensitive functions of
junction operating temperatures. And the good news is that diode currents
are strongly sensitive functions of diode voltages to which they are
exponentially dependent. Since a diode current is impacted by temperature largely through the saturation current parameter on which a diode current is directly proportional, only small changes in diode voltage are
necessary to compensate for the deleterious effects of temperature. In the
present example, less than a 2.6% drop in applied voltage stabilizes the
current supplied by the power supply in the circuit of Figure (2.7). The
real engineering problem, however, is designing the voltage source so that
it can sense temperature-induced current changes and track with requisite
changes in diode voltage.
2.3.0. PHYSICAL CONSIDERATIONS IN THE PN JUNCTION
In addition to having presented the salient features of the volt-ampere characteristics of
the PN junction diode, several engineering issues surrounding these characteristics have been addressed. Included among these issues are diode turn on requirements, a circuit level assessment
of the effects exerted by temperature on diode characteristics, and a piecewise linear model that
allows for the systematic analysis of circuits that exploit diodes operated under forward bias
conditions. Armed with an understanding of these matters and their concomitant mathematical
tools, the reader is arguably prepared to analyze networks that utilize PN junction diodes and
perhaps even to design simple diode subcircuits that support particular system performance
requirements. But a prerequisite for insightful analyses and innovative design of all circuits, and
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particularly integrated circuits that utilize semiconductor elements, requires considerably more
expertise than that associated with an awareness of only fundamental device characteristics and
features. In effect, such awareness has provided the reader with only the training wheels that can
initiate only guarded travel along the road to innovative and creative design. These trainers can
ultimately be discarded when circuit analysis succeeds in meaningfully delineating the performance attributes, as well as the operating shortfalls, of considered circuits. While many of the
performance features of electronic circuits may indeed depend on only the engineering
fundamentals of semiconductor devices and peripheral branch elements, performance
shortcomings invariably derive from the electrical effects of second order, and generally undesirable, phenomena that rarely surface in discussions limited to only basic volt-ampere characteristics. At a minimum, a consideration of these higher order effects adds realism to the fruits of basic analysis and in many instances, their creative exploitation can mitigate at least some of the
perceived shortfalls. An examination of the higher order phenomena pervasive of PN junction
diodes boasts the additional advantage of facilitating an understanding of the operation of more
complicated electronic devices.
The discovery of relevant higher order phenomena compels a discussion of the physical
characteristics of the semiconductor diode. In an attempt to forestall introversion on the part of
readers who are adamantly and perhaps myopically focused on electronic circuits, as opposed to
physical electronics, the discussion that follows exploits only the essential mathematics that
quantify the physics of semiconductor device operation. These mathematical considerations are
complemented by engineering discourse focused on the circuit level impact of relevant physical
phenomena.
2.3.1. PN JUNCTION AT EQUILIBRIUM
The discussion commences with a study of the PN junction diode at equilibrium; that
is, the diode in Figure (2.1) is operated with no voltage, light, or other form of external energy
applied to it. The diode is effectively open circuited and as a consequence, zero diode current,
id(t), prevails. As alluded to earlier in this chapter, diode current is comprised of a superposition
of currents precipitated by hole and electron injection across the PN junction. Recall that holes
injected from the p-type region to the n-type layer and electrons injected in the opposite direction
from the n-type region to the p-type layer both give rise to a current flowing from the p-side of
the junction to the n-side. Accordingly, equilibrium demands that the current components due to
both hole and electron injection across the junction be zero.
The hole current, say Idp, is, in turn, a superposition of drift and diffusion components,
which are denoted herewith as Ipdrif and Ipdiff, respectively. In particular,
(2-18)
I dp = I pdrif + I pdiff
where the hole drift current is
I pdrif = Ae qp(x)μ p (x)E (x),
(2-19)
and the hole diffusion current component is
dp(x)
.
I pdiff = − Ae qVT μ p (x)
(2-20)
dx
In the last two expressions, Ae, q, and VT are the previously introduced junction cross section
area, electron charge magnitude, and Boltzmann voltage, respectively. Moreover, p(x) is the
concentration of mobile holes as a function of position x in Figure (2.1a), μp(x) symbolizes hole
mobility (in units of cm2/volt-sec), and E(x) is the electric field intensity prevailing at position x
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in the subject diagram. The hole mobility (as well as the electron mobility) is dependent on position x by virtue of the fact that mobility is a function of carrier concentration, which varies with
position x. Since the hole current component is zero at equilibrium, (2-18), (2-19), and (2-20)
confirm a requisite internal electric field intensity of
dln [ p(x)]
.
E (x) = VT
(2-21)
dx
In other words, a nonzero electric field must prevail to establish equilibrium, and this field is
proportional to both junction temperature and the slope of the natural logarithm of hole
concentration. As is demonstrated subsequently, the subject electric field is dominantly confined
to the immediate neighborhood of the junction.
In analogous fashion, the electron component, Idn, of diode current is expressible as
(2-22)
I dn = I ndrif + I ndiff ,
where the drift constituent of electron current is
I ndrif = Ae qn(x)μn (x)E (x) ,
(2-23)
and its diffusion component is
dn(x)
.
I ndiff = Ae qVT μn (x)
(2-24)
dx
In (2-23) and (2-24), n(x) represents the free electron concentration, while μn(x) is the positiondependent electron mobility. These three relationships confirm that zero electron current commands an electric field intensity of
dln [ n(x)]
.
E (x) = − VT
(2-25)
dx
The last result and (2-21) combine to stipulate that diode equilibrium is achieved when the slopes
of the logarithmic profiles of the hole and electron concentrations adjust to satisfy the constraint,
dln [ p(x)]
dln [ n(x)]
.
= −
(2-26)
dx
dx
2.3.1.1. Junction Transition Region
The simplicity of the equilibrium condition in (2-26) masks important engineering
questions as to how an electric field that is internal to the PN junction diode can be formed,
despite the lack of any energy applied extrinsically to the diode. Addressing this question is best
initiated by examining the nature of the free carrier profiles in the PN junction device of Figure
(2.1a). To this end, assume that the p-type region is doped uniformly to an acceptor carrier
concentration that is nominally NA. It follows that on the p-side of the junction and sufficiently
removed from said junction, p(x) ≈ NA, assuming complete ionization of the introduced acceptor
impurity atoms. But on the n-side of the junction, where holes are minority carriers, p(x) ≈
ni2/ND for large x, where ni is, of course, the intrinsic carrier concentration. The resultant hole
profile is sketched in Figure (2.9a), which clearly shows that in the vicinity of the junction, the
hole concentration transitions in a reasonably abrupt fashion from the large value evidenced for x
< −Xpo to its substantively smaller value of ni2/ND for x > Xno. Although the transitional curve in
Figure (2.9a) conforms approximately to a straight line, its mathematical nature is generally an
error or Gaussian function, depending on the nature of the doping methodology adopted during
the actual fabrication process. The boundaries of the junction transition region defined by −Xpo ≤
x ≤ Xno are also dependent on the device fabrication scenario but in general, the equilibrium
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width, Wo, of the transition region is rarely more than a half micron or so. This declaration, coupled with the fact that NA commonly exceeds ni2/ND by at least ten to twelve orders of magnitude
implies that the magnitude of the slope for the transitional hole profile is enormous. It follows
from Figure (2.9a) and (2-21) that the electric field, E(x), commensurate with the establishment
of diode equilibrium is reasonably large and negative near the junction and is essentially zero far
enough away from the junction. A large electric field derives from the steepness of the free hole
profile in the junction transition region, while a negative field, which implies a field directed
from the n-side of the junction to the p-side, accrues because of the obviously negative slope of
the hole profile.
100
90
80
Diode Current, Id (mA)
70
60
50
T = 125 °C
T = 75 °C
40
30
20
T = 27 °C
10
0
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Diode Voltage, V d (volts)
Figure (2.8). The volt-ampere characteristic of a PN junction diode for three values of junction
temperature. The considered diode has n = 1, a reference temperature (27 °C)
saturation current of 2 fA, and P = 3.5.
Analogously, the free electron profile, which is sketched in Figure (2.9b), varies from a
constant of ni2/NA for x < −Xpo to a high value of approximately ND for x > Xno. As in the case of
the free hole curve, a straight line is adopted for the electron profile in the transitional region.
Since the slope of the indicated straight line is large and positive, (2-25) suggests a proportionately large and negative equilibrium electric field in the neighborhood of the junction, while the
field in regions removed from the junction approach zero.
In order that a negative electric field, E(x), be established in the neighborhood of the PN
junction to sustain the equilibrium condition, a positive charge must prevail to the right of the
junction, and a negative charge must be observed to the left of the junction. This contention
stems from the elementary picture of field lines emanating from positive charges and terminating
on negative counterparts. On either end of the semiconductor outside of the transition region abstracted in Figure (2.9), the net charge must be zero because in equilibrium, the hole and electron
densities are constant, thereby forcing zero electric field in these domains at equilibrium.
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In general, the net charge, say ρ(x), is comprised of free holes, free electrons, ionized
donor atoms, and ionized acceptor atoms. This is to say that
ρ(x) = q [ p(x) − n(x) + N D − N A ] .
(2-27)
Since ρ(x) = 0 outside the transition region at equilibrium,
(2-28)
p(x) + N D = n(x) + N A for x < − X po and x > X no
But on the p-side of the junction where −Xpo ≤ x ≤ 0, there are no donor impurities, and the
concentration of electrons, which are the minority carriers in the p-side of the junction, is miniscule in comparison to the concentration of ionized acceptor impurities. On the other hand, no
acceptor impurities reign, and the concentration of minority holes is far smaller than the
concentration of ionized donor impurity atoms on the n-side of the transition layer. Accordingly,
q [ p(x) − N A ] , − X po ≤ x ≤ 0
ρ(x) =
.
(2-29)
q [ N D − n(x)] ,
0 ≤ x ≤ X no
From Figure (2.9), it should be noted that p(x) < NA in the transition region to the left of the junction, while in the transition region to the immediate right of the PN junction, ND > n(x). This
observation is important for it confirms the existence of a net negative charge immediately to the
left of the junction and a net positive charge to the right of said junction. In turn, these negative
and positive charges provide the electrostatic foundation to support the transition region negative
electric field (meaning that field lines are directed from the n-side of the junction to the p-side)
that is required to sustain diode equilibrium.
2.3.1.2. Deletion Approximation
On the p-side of the junction transition region, the observed charge is now merely negative; it is, in fact, a very good approximation of a constant (independent of position x) negative
charge. Similarly, the charge to the immediate right of the PN junction is a very good
approximation of a constant positive charge. These contentions are deduced from the fact that on
the p-side of the junction, the concentration, p(x), of free holes drops dramatically from its high
value of NA to its significantly smaller (by many orders of magnitude) value of ni2/ND over a
transition region width, Wo, that is of the order of only a micron or so. Moreover, on the n-side
of the transition region, the concentration of free holes, n(x), likewise falls precipitously as the
junction is neared from the right. These observations, coupled with (2-29), strongly suggest the
feasibility of approximating the charge population on the p-side of the transition region exclusively by the charge associated with ionized acceptor impurity atoms while on the n-side, the
charge population might be represented as only the charge associated with ionized donor impurities. Formally, the depletion approximation reflects the presumptions, p(x) << NA and n(x) <<
ND, so that (2-29) simplifies to
− qN A , − X po ≤ x ≤ 0
ρ(x) ≈
.
(2-30)
qN D ,
0 ≤ x ≤ X no
The ramifications of (2-30) are abstracted in Figure (2.10), which depicts a PN junction
transition layer that is completely divorced of mobile charge carriers under equilibrium conditions. Specifically, the transition region to the left of the junction is filled with the negative
charges associated with ionized acceptor atoms, while the transition layer to the right of the junction is a sea of positive charges that derive from ionized donor impurities. The depletion
approximation is obviously suspect at each of the two transition layer boundaries; that is, at x =
−Xpo and x = Xno. Suspicions are justifiably aroused as well at the origin, x = 0, where the
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charge distribution model of (2-30) produces a charge profile changing abruptly from −qNA at x
= 0− to +qND at x = 0+. Misgivings notwithstanding, Figure (2.10) conveys an elegantly
understandable picture of the equilibrium condition. In particular, the negative ionic charge to
the left of the junction repels any free electrons that may be motivated to cross the junction from
right to left, thereby nullifying any electron component of diode current. Similarly, the positive
ionic charges to the right of the PN junction inhibit hole injection from the p-side to the n-side,
whereupon the hole component of diode current is held to zero. This simple picture encourages
the view that the width, Wo, of the transition layer defined over the closed interval, −Xpo ≤ x ≤
Xno, is just wide enough to accommodate a sufficient concentration of negative ionic charge on
the left of the junction and positive ionic charge on the right side to impede the injection of mobile charge carriers across the junction. When one side of the junction is doped more intensely
than is the other side, the intrusion of the ion-charged transition layer into the more lightly doped
side must be commensurately deeper to insure a sufficient volume for the ionic charge needed to
repel the injection of mobile charge from the strongly doped side. As it materializes, PN junction diodes are commonly fabricated with an n-side doped more strongly than the p-side, which
therefore gives rise to a depletion region that intrudes further into the p-side of the junction than
into the n-side. One reason for this device fabrication tack is that for a given impurity concentration, electron mobility exceeds hole mobility. Accordingly, increased current response speeds to
rapidly applied voltage excitations are facilitated.
Acceptor
Donor
Ions Junction Ions
−
−
−
−
−
−
−
−
id (t)
=0
−Wp
−Xpo
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
x
Wo
0
Xno
Wn
Transition Region
Figure (2.10). Abstraction of a PN junction diode in equilibrium, wherein the depletion approximation is invoked over the junction transition region. The only charges prevailing within
the transition volume are those associated with immobile ionized impurity atoms.
2.3.1.3. Electric Field And Potential In The Depletion Layer
The simple charge model evoked by (2-30) and Figure (2.10) enables a convenient
quantification of the electric field intensity and corresponding potential distribution associated
with the equilibrium condition. To this end, Figure (2.11a) portrays the subject charge distribution as a function of position x in Figure (2.1). Gauss’ law relates the electric field intensity,
E(x), to charge distribution ρ(x) in accordance with[1]
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ρ(x)
qND
−Xpo
0
Xno
x
−qNA
(a).
E(x)
−Xpo
0
Xno
x
E(0)
(b).
Figure (2.11). (a). Depletion approximation of the charge profile
in a PN junction operated at equilibrium. (b). The
electric field corresponding to the charge profile in
(a). The electric field intensity, E(0), at the junction is given by (2-37).
d E (x)
ρ(x)
=
,
(2-31)
dx
εs
where εs is the dielectric constant of the semiconductor under consideration. For silicon, εs =
1.05 pF/cm. In the region, −Xpo ≤ x ≤ 0, where ρ(x) = −qNA, (2-31) implies
E (x)
∫
E (-X po )
qN A
d E (x) = −
εs
x
∫
(2-32)
dx ,
− X po
or
(
)
qN A
x + X po ,
(2-33)
εs
where use is made of the previously disclosed fact that at equilibrium, the electric field is null
outside of the transition region; specifically, E(−Xpo) = 0. On the n-side of the junction,
E (x) = −
E (X no )
∫
E (x)
qN D
d E (x) =
εs
X no
∫
dx ,
(2-34)
x
which produces, with E(Xno) = 0,
qN D
E (x) =
( x − X no ) .
εs
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Consistency at x = 0 between the two electric field solutions in (2-33) and (2-35) mandates
(2-36)
N A X po = N D X no ,
which analytically confirms a previous supposition to the effect that the transition layer about the
PN junction intrudes deeper into the lighter doped side of the junction. The results postured by
(2-33), (2-35), and (2-36) give rise to the field plot shown in Figure (2.11b), where it is understood that the electric field intensity, E(0), at the actual junction is
qN A X po
qN D X no
= −
.
E (0) = −
(2-37)
εs
εs
Note that the electric field is negative throughout the transition region, which is to say that it is
always directed from the n-side of the junction, which houses positive ionic charge in the depletion region, to the p-side of the junction where negative ionic charge reigns. A maximum magnitude of field intensity is observed at the actual junction of the PN structure, while zero field prevails in the charge neutral regions outside of the transition region.
Poisson’s equation teaches that the presence of an electric field, E(x), implies the existence of a potential, V(x), such that
dV(x)
E (x) = −
.
(2-38)
dx
This fundamental relationship can be gainfully exploited to discern the potential, V(−Xpo), at the
p-side boundary of the transition/depletion layer for a diode in equilibrium, and V(Xno), the corresponding potential at the n-side boundary of the transition layer. These two voltage metrics allow for the evaluation of the junction built-in potential, say Vj, which is the potential difference,
V j = V ( X no ) − V − X po ,
(2-39)
(
)
that effectively supports the electric field plotted in Figure (2.11b).
Return to (2-21), which delineates the requisite electric field commensurate with zero
hole current. Combining (2-38) with (2-21),
dV (x) = − VT dln [ p(x)] ,
(2-40)
which can be integrated over potential from an arbitrary reference potential of V(Xi) to the potential, V(x) at any position x to stipulate
V (x)
∫
V (X i )
ln [p(x)]
dV (x) = − VT
∫
dln [ p(x)] .
(2-41)
ln [p(X i )]
Upon carrying out the integration mechanics in this expression, the potential, V(x), is seen to satisfy
⎡ p(x) ⎤
V (x) = V ( X i ) − VT ln ⎢
(2-42)
⎥.
p
X
(
)
i ⎦
⎣
The traditional reference convention sets V(Xi) to zero with the understanding that Xi is the position at which the free carrier concentration, p(Xi) in this case, attenuates to the intrinsic
semiconductor concentration, ni. Thus, V(Xi) = 0 when p(Xi) = ni, whence (2-42) becomes
⎡ p(x) ⎤
(2-43)
V (x) = −VT ln ⎢
⎥.
n
⎣ i ⎦
With reference to Figure (2.9a), (2-43) identifies the equilibrium potential, measured with respect to the potential at which the hole concentration profile degrades to its intrinsic value, as a
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PN Junction Diode
J. Choma
function of position x on the p-side of the junction. At x = −Xpo, p(−Xpo) = NA, which results in
a potential, V(−Xpo), at the p-side boundary of the PN junction transition layer of
⎡N ⎤
(2-44)
V − X po = − VT ln ⎢ A ⎥ .
⎣ ni ⎦
(
)
Equations (2-43) and (2-44) derive from (2-21), which sets the condition for zero hole
current in a PN junction diode. On the other hand, (2-25) delineates the requirement underlying
zero electron current. If the preceding analysis is repeated, but premised on (2-25), the reader
can verify that
⎡ n(x) ⎤
(2-45)
V (x) = VT ln ⎢
⎥,
⎣ ni ⎦
and
⎡N ⎤
(2-46)
V ( X no ) = VT ln ⎢ D ⎥ .
⎣ ni ⎦
Equation (2-45) defines the potential, referenced to the potential at the position where the free
electron concentration is its intrinsic value, ni, on the n-side of the PN junction diode. Equation
(2-46) gives the potential at the n-side boundary of the equilibrium transition layer. Upon insertion of this result and (2-44) into (2-39), the junction built-in potential, Vj, manifested in concert
with diode equilibrium is found to be
⎛N N ⎞
(2-47)
V j = V ( X no ) − V − X po = VT ln ⎜ A D ⎟ .
⎜ n2 ⎟
i
⎝
⎠
(
)
The built-in voltage, Vj, is a positive number since the dopant concentrations on both
the p-side and the n-side of the PN junction diode are assuredly larger than the semiconductor
intrinsic carrier concentration. This voltage, which is generally of the order of 800 mV to 1 volt,
is therefore polarized positive at the n-side transition layer boundary and negative at the p-side
transition layer boundary. Strangely enough, this relatively large internal voltage is established
in a diode that is not connected into a network that features a source of energy. In an attempt to
thwart perceptions of premature author senility, the background physical issues that spawn this
built-in potential are worthy of review. First, a diode in equilibrium conducts zero current,
which requires that both the hole and electron components of diode current be zero. Zero hole
and electron components require that an electric field be established in the transition layer. This
field is proportional to the logarithmic slopes of the hole and electron concentrations in the
immediate neighborhood of the junction. The electric field in question is directed from the nside of the PN junction to the p-side, which in turn requires a concentration of positive charge in
the n-side transition region and a concentration of negative charge on the p-side of the transition
layer. These charge concentrations support the subject built-in junction potential, whose
polarization effectively serves to reverse bias the PN junction diode. The potential, Vj might
therefore be thought of as the requisite level of reverse biasing that is just large enough to preclude hole and electron injection, and therefore null current conduction, through the junction
under equilibrium conditions.
2.3.1.4. Contact Potential
Adding to the puzzling nature of the built-in equilibrium junction potential, Vj, is the
fact that its direct measurement in a laboratory setting is impossible. A somewhat cavalier
Minh Hsieh Department of Electrical Engineering
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Lecture Supplement #3
PN Junction Diode
J. Choma
explanation of this measurement dilemma is that any attempt to connect a voltmeter, oscilloscope, or other measurement apparatus around a non-energized diode inherently destroys the
equilibrium condition that corresponds to the establishment of the built-in potential. A more
satisfying rationale is offered by the concept of contact potentials. A contact potential is an
unavoidable voltage difference established between two dissimilar materials that are in electrical
contact with one another. These contact voltage drops are precipitated by differences in the
potential energies of mobile electrons on either side of the contact. Consider, for example, the
resistively shunted diode in Figure (2.12), in which the metal contacts at either end of the diode
structure are expressly delineated. Because these metal contacts, which are typically formed of
copper or aluminum, differ materially from the physical properties of the semiconductor diode,
contact potentials, Vpm and Vnm are explicitly established, as shown in the extended diode diagram. In particular, a contact potential of Vpm is forged from the p-type semiconductor to the
metal contact on the left of the device, while a contact potential, Vnm, is analogously formed from
the n-type semiconductor to the metal contact on the right. The charge neutral regions of both
the p- and n-sides of the junction support zero voltage drops because of the zero current equilibrium condition. Even if diode current were to flow, these voltage drops remain near zero because the heavily doped p- and n-sides of the diode give rise to very small ohmic resistances in
charge neutral sectors. Using Kirchhoff’s voltage law,
Vpm
−
Vnm
+
−
0
id (t)
=0
+−
−
−
−
−
−
−
−
−
Metal
Contact
+−
Vj
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
+
+
+
+
+
+
+
+
R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
0
+
+
−
+
+
+
+
+
+
+
+
Metal
Contact
Figure (2.12). PN junction diode at equilibrium and connected in shunt with a resistance, R. The
metal contacts at either end of the diode are expressly highlighted, as are the
corresponding semiconductor-metal contact potentials, Vpm and Vnm.
id (t)R = − Vnm + V j + V pm .
(2-48)
Since the built-in potential, Vj, precludes the flow of diode current, the contact potentials must
neutralize Vj; that is,
(2-49)
Vnm − V pm = V j .
If (2-49) is not satisfied, a nomination for a Nobel is appropriate for otherwise, current is made to
flow through, and thus energy is delivered to, a resistance without any energy applied to the entire diode-resistance system. It should be noted that (2-49) implies that contact potentials
necessarily track with doping concentrations, and hence semiconductor material properties, since
the built-in potential given by (2-47) is sensitive to impurity concentrations.
Minh Hsieh Department of Electrical Engineering
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Lecture Supplement #3
PN Junction Diode
J. Choma
2.3.1.5. Transition Layer Width And Depletion Capacitance
Equation (2-38) can be applied directly to the junction transition region, −Xpo ≤ x ≤ Xno,
which is graphically highlighted in Figures (2.9) through (2.11). On the p-side of the junction,
(2-38) and (2-33) give
dV(x)
qN A
−
= −
x + X po ,
(2-50)
dx
εs
which in turn delivers
(
V (x)
∫
V (-X po )
)
qN A
dV(x) =
εs
x
∫ ( x + X po ) dx .
(2-51)
− X po
The integration of both sides of this expression produces a potential, V(x), on the p-side of the
junction transition layer of
2
qN A
V (x) = V − X po +
x + X po ,
(2-52)
2εs
which predicts a potential, V(0), at the actual junction, referenced to the potential evidenced at
the position where the free carrier concentration reduces to intrinsic level, of
(
(
)
)
V(0) = V − X po +
(
2
qN A X po
2εs
)
.
(2-53)
On the n-side of the junction, (2-38) and (2-35) combine to offer
V (X no )
−
∫
V (x)
qN D
dV(x) =
εs
X no
∫
( x − X no ) dx
,
(2-54)
x
whence
qN D
(2-55)
( x − X no ) 2 .
2εs
The last result promotes a junction potential of
2
qN A X no
(2-56)
V (0) = V ( X no ) −
.
2εs
This potential at the diode junction must align with the junction potential defined by (2-53). If
(2-53) is subtracted from (2-56) and if use is made of (2-39) and (2-36), such connectivity of
potential at the junction forms the basis for positioning the actual boundaries of the transition region, subject, of course, to the depletion approximation invoked earlier. In particular,
2εsV j ⎛ N D ⎞
X po =
(2-57)
⎜
⎟
qN A ⎝ N A + N D ⎠
and
2εsV j ⎛ N A ⎞
⎛N ⎞
X no = ⎜ A ⎟ X po =
(2-58)
⎜
⎟ .
qN D ⎝ N A + N D ⎠
⎝ ND ⎠
It follows that the equilibrium width, Wo, of the junction transition layer is
V (x) = V ( X no ) −
Minh Hsieh Department of Electrical Engineering
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USC Viterbi School of Engineering
Lecture Supplement #3
PN Junction Diode
(
)
Wo = X no − − X po =
J. Choma
2εsV j
,
qN AD
where NAD is the effective impurity concentration,
N AN D
N AD =
.
N A + ND
(2-59)
(2-60)
The positive charge prevailing on the n-side of the transition region in the PN junction
diode in Figure (2.10), the extant negative charge on the p-side transition volume of the junction,
and the finite, nonzero width, Wo, which separates the boundaries of the charge transition layer
combine to conjure visions of an effective parallel plate capacitance that straddles the junction.
The “plates” of this perceived capacitance are not metallic, as is the norm in traditional
capacitance realizations. Instead, they are the heavily doped, and thus low resistivity, p-type and
n-type charge neutral regions to which electrical contact is made for ultimate circuit applications
of the diode structure. In concert with the parallel plate capacitance vision, the capacitance, say
Cjo, associated with the charge embedded in the transition volume of a PN junction diode is
Aε
qεs N AD
C jo = e s = Ae
.
(2-61)
Wo
2V j
This capacitance is commonly referred to as the equilibrium, or zero bias, depletion capacitance
of the PN junction. Observe that the capacitance at hand is directly proportional to the area of
the junction, which correctly hints that diodes earmarked for high-speed circuit applications must
be sufficiently small to avoid significant charge storage at the junction. Its value is also largely
limited by the impurity concentration of the lightly doped side of the junction. The latter
observation is synergistic with engineering intuition in that the depletion capacitance straddling
the entire transition layer can be viewed as the series interconnection of two capacitances. One
of these series capacitances appears from the p-side boundary of the junction transition layer to
the actual PN junction, while the second of the two series capacitances effectively connects from
the junction to the n-side boundary of the transition layer.
EXAMPLE #2.3:
A certain silicon diode boasts a PN junction injection area of 80 μm2, an
approximately constant p-side dopant concentration of 1016 atoms/cm3,
and an approximate n-side dopant concentration of (6.5)(1018) atoms/cm3.
For equilibrium and room temperature conditions, calculate the built-in
potential of the junction, the width of the junction transition layer, the
maximum magnitude of electric field internal to the junction, and the zero
bias value of the junction capacitance. Assume the validity of the depletion approximation and take the intrinsic carrier concentration at room
temperature to be (1.5)(1010) atoms/cm3.
SOLUTION #2.3:
(1).
At 27 °C, or 300.16 °K, the Boltzmann voltage is, by (2-2), VT = 25.89 mV. From (247), the built-in potential with NA = 1016 atoms/cm3, ND = (6.5)(1018) atoms/cm3, and
ni = (1.5)(1010) atoms/cm3 follows as
Minh Hsieh Department of Electrical Engineering
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Lecture Supplement #3
PN Junction Diode
⎡N N ⎤
V j = VT ln ⎢ A D ⎥ = 862.02 mV .
⎢⎣ ni2 ⎥⎦
(2).
J. Choma
(E3-1)
Using (2-60), the effective diode impurity concentration is
N AN D
(E3-2)
N AD =
= (9.985)(1015 ) atoms/cm 3 .
N A + ND
With Vj = 862.02 mV, a silicon dielectric constant of εs = 1.05 pF/cm, and an electron
charge magnitude of q = (1.6)(10−19) coulomb, (2-59) delivers an equilibrium depletion layer width of
2εsV j
Wo =
= (3.37)(10 -5 ) cm = 0.337 μm .
(E3-3)
qN AD
In arriving at this disclosure, use is made of the fact that one micron (μm) converts to
10−4 centimeter (cm).
(3).
For an emitter junction area of Ae = 80 μm2 = (80)(10−8) cm2, (2-61) yields an equilibrium transition region capacitance of
Aε
(E3-4)
C jo = e s = 24.95 fF .
Wo
Since the junction area of an integrated PN junction diode is a designable parameter
selected in accordance with appropriate system considerations, this capacitance is often expressed as a capacitance density. This density is the metric, Cjo/Ae, which happens to be 31.19 nF/cm2 in this particular case.
(4).
From (2-57), the intrusion of the junction transition layer into the p-side of the junction is
X po =
2εsV j ⎛ N D ⎞
⎜
⎟ = 0.3361 μm .
qN A ⎝ N A + N D ⎠
(E3-5)
For the n-side intrusion, (2-58) provides
⎛N ⎞
(E3-6)
X no = ⎜ A ⎟ X po = 0.000517 μm = 0.517 nm .
⎝ ND ⎠
Appealing to (2-37), the maximum magnitude of the electric field intensity, which is
observed at the actual PN junction, is
qN A X po
qN X
E (0) = −
(E3-7)
= − D no = 51.22 kVolt/cm .
εs
εs
COMMENTS: A notable aspect of this numerical example is the significant electric field
intensity established at the equilibrium junction of the considered diode.
The field of better than 50 kV/cm is comparable to the electric field established by a 12-volt automobile battery cable whose positive and negative
leads are separated by two and a third microns of insulation. As might be
expected, the field in question is accompanied by a correspondingly sizeable built-in potential whose magnitude in this case exceeds typical turn
on voltages for silicon diodes by better than 160 mV. Finally, observe that
most of the depletion layer extends into the p-side of the junction, which is
doped significantly lighter than is the n-side. Indeed, only 0.267% of the
net equilibrium width of the depletion layer materializes on the n-side of
the junction.
Minh Hsieh Department of Electrical Engineering
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Lecture Supplement #3
PN Junction Diode
+ vd(t) −
−
−
−
−
−
−
−
−
−
id (t)
=0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
<0
−Wp
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
x
Wo
0
Xno
Wn
(a).
+ vd(t) −
−
id (t)
+
Vj
−Xpo
−Wp
J. Choma
−
−
−
−
−
−
−
−
−Xp
+
Vj + V
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
x
W > Wo
0
Xn
Wn
+
−
V
(b).
Figure (2.13). (a). PN junction diode under equilibrium conditions for which no diode current
flows. (b). Reverse biased PN junction diode. A small amount of negative diode
current flows in response to the applied reverse biasing voltage, V, owing to injection across the junction of the minority carriers on either side of the junction.
2.3.2. PN JUNCTION AT NON-EQUILIBRIUM
A PN junction diode operated under non-equilibrium circumstances has energy applied
to it to effect either reverse bias or forward bias operation. The diode equilibrium conditions
studied in the preceding section of material serve as an excellent backdrop for studying nonequilibrium junction dynamics. This contention derives from earlier assertions to the effect that
the equilibrium width, Wo, of the junction depletion region is just wide enough to house just the
right density of positive and negative impurity ions to repel the injection of holes and electrons
across the junction. Equivalently, these ionized impurities within the depletion layer establish an
electric field that supports a built-in potential, Vj, which serves effectively to reverse bias the
Minh Hsieh Department of Electrical Engineering
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Lecture Supplement #3
PN Junction Diode
J. Choma
intrinsic junction at precisely the level commensurate with the preclusion of free carrier injection
across the PN junction. In a word, the magnitude and polarization of the built-in junction potential guarantees zero diode current in the equilibrium state. The gravitas of this operational state
of affairs is overviewed in Figure (2.13a).
2.3.2.1. Reverse Biased PN Junction Diode
Figure (2.13b) shows the PN junction diode cross section of Figure (2.13a) under the
condition of a reverse bias voltage, V, applied across the diode terminals. In this non-equilibrium
state, the measurable diode terminal voltage, vd(t), is vd(t) = −V in that the very small reverse
bias current manifested by voltage V incurs negligible potential drop in the ohmic, charge neutral
p-type and n-type volumes. Resultantly, the built-in junction potential increases from its equilibrium value of Vj to its reverse biased value of (Vj + V). Several ramifications of this effectively
increased built-in potential are immediately apparent. First, since Vj is the value of the intrinsic
junction reverse bias that is just sufficient to preclude the transport of mobile charge carriers
across the junction, an increase of Vj by the amount, V, serves to attract minority carrier electrons
from the p-side of the junction to the n-side. Similarly, the increased intrinsic junction potential
corresponds to an increased density of ionic charge within the depletion layer to encourage
minority carrier holes from the n-side to traverse the PN junction.
The second effect of the applied reverse bias is to increase the equilibrium width, Wo,
of the depletion layer to the value, W, delineated in Figure (2.13b). From (2-59), this revised
value of depletion layer width can be deduced as
(
2εs V j + V
)
V
v (t)
= Wo 1 − d
.
(2-62)
qN AD
Vj
Vj
Because of the enhanced depletion layer width, the zero bias depletion capacitance in (2-61) can
be expected to decrease from its original value of Cjo to its biased value, say Cj, such that
C jo
Ae εs
Cj =
(2-63)
=
;
V
vd (t)
Wo 1 +
1−
Vj
Vj
W =
= Wo 1 +
that is, the junction depletion capacitance decreases with increasing reverse bias, largely because
of the increased depletion layer width (or thickness of the parallel plate capacitance fantasized
earlier) incurred by this reverse bias.
A third consequence of the applied reverse bias is increased electric field intensity at
the junction. Referring to (2-37) and (2-57), the revised (reverse biased) junction electric field
intensity, say Er(0), is
Er (0) = −
(
2qN AD V j + V
εs
)
v (t)
= E (0) 1 − d
.
Vj
(2-64)
This increased field intensity is a concern in that the zero bias field intensity is, as demonstrated
in Example #2.3, already surprisingly large. As a result, field-induced voltage breakdown is a
distinct possibility if the applied reverse bias, V, exceeds the reverse bias voltage rating of the device[2]. Such breakdown, which manifests potentially appreciable negative diode current, does
not necessarily imply a catastrophic device failure. Indeed, special purpose diodes known as
Zener diodes, are commonly manufactured to operate expressly in breakdown mode where they
Minh Hsieh Department of Electrical Engineering
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Lecture Supplement #3
PN Junction Diode
J. Choma
deliver significant negative diode currents at a virtually constant reverse bias voltage that is commonly referenced as a Zener voltage. Zener diodes therefore enjoy utility in regulator applications for which the system requirement is a nominally constant load voltage in the face of
perturbations in line voltages and effective load resistance. More information regarding voltage
regulation is provided later in this text.
In summary, the immediate effects of a reverse bias applied to a PN junction diode is
increased junction field intensity, decreased depletion capacitance, and increased equilibrium
value of the transition layer width. From (2-64), (2-63), and (2-62), the modulations associated
with these effects are conveniently coalesced as
C jo
v (t)
Er (0)
W
V
.
=
=
= 1+
= 1− d
(2-65)
E (0)
Cj
Wo
Vj
Vj
Because (2-65) is premised on the depletion approximation, which while reasonable, is suspect at
the junction and at the edges of the transition region, (2-65) is traditionally adjusted in accordance with
mj
m
j
⎛
vd (t) ⎞
= ⎜1 −
.
(2-66)
⎟
⎜
V j ⎟⎠
⎝
In (2-66), mj is an empirically determined grading coefficient whose numerical value spans the
range, 0.25 ≤ mj ≤ 0.5. In general, mj tends toward 1/2 if the observed charge profile closely
approximates the abrupt change at the junction that is diagrammed in Figure (2.11a). On the
other hand, mj is of the order 1/3 if the charge profile at the junction exudes a relatively shallow
gradient.
⎛
C jo
W
V ⎞
Er (0)
=
=
= ⎜1 +
⎟
⎜
Cj
Wo
V j ⎟⎠
E (0)
⎝
2.3.2.2. Forward Biased PN Junction Diode
Figure (2.14) diagrams the state of affairs pertinent to forward biasing a PN junction diode. Specifically, Figure (2.14a) compares the equilibrium state to the structure in Figure
(2.14b), which exemplifies the effects of a forward biasing voltage applied across the diode
terminals. In this case, observe that the applied voltage, V, which is the actual diode voltage,
vd(t), is polarized to counteract the built-in potential, Vj. The voltage resultantly developed
intrinsically across the transition region reduces to (Vj − V). Since the establishment of a built-in
voltage of Vj corresponds to an equilibrium transition region width of Wo, a potential reduced by
the amount, V, affords a correspondingly smaller transition layer width, W. Accordingly, the
transition volume houses a reduced density of immobile ions, which ostensibly promotes injection of mobile charge carriers across the junction. This disclosure synergizes with the fact that
since Vj is the built-in voltage required to preclude mobile carrier injection across the junction,
an effectively reduced built-in potential bodes increased carrier injection, thereby giving rise to a
positive diode current, id(t).
It should be understood that the applied voltage, V, can neither equal nor exceed the
original built-in potential, Vj. If V were to equal Vj, the PN junction diode effectively emulates a
short circuit between its external terminals because of the resultant zero voltage drop across the
junction transition region and the negligible ohmic drops in the charge neutral p- and n-sides of
the junction. If V were to exceed Vj, the curious and inexplicable case of a transition region
boasting negative width arises. It is therefore reasonable to postulate that Vj represents the maximum possible forward bias that can be sustained across a PN junction diode without incurring a
Minh Hsieh Department of Electrical Engineering
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USC Viterbi School of Engineering
Lecture Supplement #3
PN Junction Diode
J. Choma
diode short circuit and the likely catastrophic failure spawned by the large short circuit currents
conducted by the diode.
+ vd(t) −
Vj
+
−
id (t)
=0
−Wp
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
>0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
x
Wo
−Xpo
0
Xno
Wn
(a).
+ vd(t) −
Vj − V +
−
id (t)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
x
W < Wo
−Xp
Xn
Wn
V
−
0
+
−Wp
(b).
Figure (2.14). (a). PN junction diode under equilibrium conditions for which no diode current flows. (b). Forward biased PN junction diode. Majority carrier injection
across the junction, and thus a positive diode current, id(t), is promoted by the
partial collapse of the junction transition layer width.
A subtle, but enormously important, impact of diode forward biasing is that the junction transition region depicted in Figure (2.14b) is no longer a depletion forum. To be sure,
immobile ionized charges, and therefore a depletion capacitance component, persist in this region because the width of the transition layer never collapses to zero. But immersed in this
density of ionic charges are densities of mobile charges in that the injection of p-side holes
across the junction is encouraged, as is the injection of free electrons from the n-side to the pside. Equation (2-66), which presumes complete depletion of the transition layer, therefore no
longer proscribes accurate disclosures of relevant junction dynamics. Since the forward bias apMinh Hsieh Department of Electrical Engineering
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PN Junction Diode
J. Choma
plied to a PN junction diode differs negligibly from the junction turn on voltage, Von, even for
relatively large forward diode current perturbations, the depletion capacitance expression postured by (2-66) can be supplanted by the approximation,
C jo
≈
C jf .
(2-67)
Cj
mj
vd (t)>0
⎛
V ⎞
⎜⎜ 1 − on ⎟⎟
Vj ⎠
⎝
The argument in favor of the last result, which advances a constant depletion capacitance under
forward bias conditions, is that for vd(t) ≤ Von, very few mobile charge carriers traverse the PN
junction, while large forward diode currents can prevail even when the observed diode voltage
only slightly exceeds Von.
The junction depletion capacitance, Cjf, approximated by (2-67) is not the only capacitance indicative of a forward biased PN junction, nor is it necessarily the dominant component of
the total diode capacitance. In the course of traversing the junction from the p-side to the n-side,
a hole necessarily spends a nonzero amount of time within the junction transition region. Similarly, a free electron requires nonzero time to diffuse across the transition layer en route from the
n-side of the junction to the p-side. For the average amount of time that these holes and electrons spend within the transition volume, the charge therein obviously increases above the zero
current charge level set by the density of ionic charge. Consequently, the hole-electron charge
population that briefly resides in the transition volume under forward bias conditions increases
the effective junction capacitance above the depletion capacitance level established solely by
immobile ionic charges residing within the layer. This enhanced mobile charge, say Qd(t), which
might properly be viewed as an excess hole-electron charge in the sense of comparing it to the
background ionic charge within the transition layer, is foundational to the steady state diode current defined by the right hand side of (2-1). Indeed, this steady state diode current is nonzero if
and only if Qd(t) is nonzero, for diode current in the steady state arises exclusively from the
continual transport of holes and electrons across the transition layer that straddles the PN junction. It is therefore reasonable to proffer that the excess junction charge, Qd(t), is proportional to
diode current in accordance with the simple relationship,
Qd (t) = τd I o ⎡ evd (t) nVT − 1⎤ ,
(2-68)
⎣
⎦
where the proportionality constant, τd, is termed the average lifetime of free charge carriers.
More specifically, τd physically reflects the average time spent by injected holes and electrons
within the transition layer of a PN junction diode. For relatively small feature size diodes destined for high-speed signal processing applications, τd is of the order of a few to a few tens of
picoseconds. For larger diodes earmarked for use in power system applications, τd can be hundreds and even several thousands of picoseconds.
68) is
The diffusion capacitance, Cd, associated with the excess transition region charge of (2-
dQd (t)
τ I
τ i (t)
= d o evd (t) nVT ≈ d d ,
(2-69)
d vd (t)
nVT
nVT
where (2-1), in which the unity term is discarded in comparison to the exponential term on the
bracketed right hand side, is used. Recalling (2-67), it follows that the total capacitance, say CT,
associated with a forward biased PN junction diode is
Cd =
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⎛
τ i (t)
V ⎞
CT = Cd + C jf ≈ d d + C jo ⎜ 1 − on ⎟
⎜
nVT
V j ⎟⎠
⎝
J. Choma
−m j
.
(2-70)
Cjf
CT
Cd
id (t)
id (t)
+ vd (t) −
>0
Q d(t)/τd
+ vd (t) −
(a).
Cj
id (t)
id (t)
+ vd (t) −
<0
Io
+ vd (t) −
(b).
Figure (2.15). (a). Approximate circuit model of a forward biased PN junction diode. The charge
function, Qd(t), and the capacitances, Cd and Cjf, are given respectively by (2-68), (269), and (2-67). (b). Approximate circuit model of a reverse biased PN junction
diode. The current, Io, is the saturation current of the subject diode, while the junction capacitance, Cj, derives from (2-65).
The foregoing results combine to infer that the forward biased PN junction diode can be
represented electrically by the model in Figure (2.15a). On the other hand, Figure (2.15b) is the
pertinent model for reverse biasing, wherein the diffusion capacitance is null since no free holes
or electrons are injected across the junction. Accordingly, the only capacitance across a reverse
biased PN junction is the depletion component, Cj, as specified by (2-66). Finally, the steady
state diode current stipulated by (2-1) is supplanted in the latter model by the very small diode
saturation/leakage current, Io.
2.4.0. CIRCUIT CONSIDERATIONS FOR THE PN JUNCTION
The models in Figure (2.15) and the physical and engineering concepts on which these
structures are premised enable a meaningful, albeit approximate, analytical discourse of response
characteristics and properties that are indigenous to circuits utilizing PN junction diodes. Among
the most important of these issues are switching time delays observed in diode networks that are
driven by voltage excitations that emulate step functions in the time domain. An understanding
of these switching transients and an ultimate mitigation of their dominant effects in high-speed
signal processors often comprise pivotal design considerations in diode, as well as in more advanced semiconductor circuits. A second critical circuit issue is the concept of small signal response, wherein diodes (and eventually transistors) in a given network are biased in their forward
regimes and continue to function for all time in a restrictive neighborhood of their respective
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quiescent operating points. Small signal analysis concepts are particularly germane to electronic
networks that are designed to achieve nominally linear input/output signal processing despite the
inherent nonlinearities that prevail within the diodes and other semiconductor devices embedded
in them.
2.4.1. PN JUNCTION DIODE SWITCHING TRANSIENTS
The voltage, vi(t), applied to the series resistance-diode circuit of Figure (2.16) is
switched at time t = 0 from a positive voltage of VF to a negative voltage of −VR. The resultant
time domain depiction of this input port voltage is as drawn in Figure (2.17a). It is assumed that
the circuit has settled into steady state operation immediately prior to the voltage switching at
time t = 0, and it is further assumed that voltage VF exceeds the turn on threshold of the PN junction diode. Using the simple diode switch model of Figure (2.3), the diode current, id(0−),
immediately prior to input voltage switching is
V − Von
IF .
id (0− ) = F
(2-71)
R
t
=0
+
VF
−
R
vi(t)
SW
+
−
+
VR
−
vd(t)
id (t)
Figure (2.16). Circuit used to evaluate the current switching
response speed of a PN junction diode driven
in the time domain by a voltage step.
If the simple diode model of Figure (2.3) continues to be invoked subsequent to the indicated input voltage switching, the diode current vanishes instantly at time t = 0+. It follows that the diode current resulting from the input voltage step is ostensibly the response delineated in Figure
(2.17b).
Unfortunately, the idealized response projected by Figure (2.17b), which is premised on
only a simplistic first order diode model, is unrealistic for at least two reasons. First, it inherently ignores the fundamental fact that charge cannot be displaced instantaneously and second, it
is oblivious to the voltage discharge properties of the junction depletion capacitance. In particular, an excess charge, comprised of mobile holes and electrons, is stored in the junction transition
region immediately prior to input voltage switching. This charge underpins the initial diode current, IF, given by (2-71) and the corresponding approximate forward biased diode voltage, Von.
Zero current is conducted by the diode only when the junction transition region is returned to its
depleted state; that is, the aforementioned stored excess charge within the region must be removed as a prerequisite to zero current flow in the steady state. During the time interval in
which excess charge remains in the transition area, and as is suggested by Figure (2.17c), a
substantial current in the amount of IR flows effectively the wrong way through the diode
immediately after the input voltage switching. The current flows the wrong way because free
electrons remaining within the transition layer are repulsed by the potential, −VR, which is
incident with the p-side of the junction. On the other hand, holes within the layer are attracted to
the p-side by said negative potential. Since the diode voltage, Von, is associated with the excess
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junction charge that awaits removal, it too is sustained for time t > 0, thereby manifesting a
“wrong way” current of
vi(t)
VF
t
0
−VR
(a).
id(t)
IF
t
0
(b).
id(t)
IF
−VR /10 R
ts
0
ts + tc
t
−IR
toff
(c).
Figure (2.17). (a). The voltage applied to the input port of the dioderesistance circuit shown in Figure (2.16). (b). Idealized
diode current response to the input port excitation shown
in (a). (c). A more realistic depiction of the diode current response to the input port excitation shown in (a).
V + Von
− IR .
id (0+ ) = − R
R
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The conduction of this diode current is prolonged until the indicated time, ts, at which the junction transition region is wiped clean of excess charge. In effect, the diode does not begin to turn
off until time t = ts, which might properly be referred to as the charge storage time of the diode.
At t = ts, the diode voltage remains Von, which means that the junction depletion capacitance is
charged to Von; specifically, vd(ts+) = Von. Zero diode current is ultimately achieved only when
this capacitance charges from voltage Von to nearly the time t > 0 input voltage of −VR.
With reference to the diagram in Figure (2.17c), the effective turn off time, toff, of the
diode is the superposition of the storage time, ts, and the junction capacitance charging time, tc;
that is,
(2-73)
toff = ts + tc .
It is understood herewith that Qd(ts) = 0, and tc is the additional time (above time ts) required for
the diode depletion capacitance to charge to the somewhat arbitrarily imposed level of vd(ts + tc)
= −0.9VR. Observe that the diode current, id(ts + tc), corresponding to vd(ts + tc) = −0.9VR is
V
id (ts + tc ) = − R .
(2-74)
10R
2.4.1.1. Switching Transient Analysis
An analytical substantiation of the foregoing, largely qualitative, predictions of the diode current response in the circuit of Figure (2.16) begins with the observation that at time t =
0− (immediately prior to throwing switch SW), the circuit operates in the steady state, and the diode current is given by (2-71). Using (2-68), this current gives rise to an excess charge, Qd(0−),
at t = 0− of
Qd (0− ) = τd I F ≈ τd Io ⎡ eVon nVT − 1⎤ ,
(2-75)
⎣
⎦
where in the interest of consistency with the current expression in (2-68), the diode voltage,
vd(0−), at time t = 0− has been approximated as the diode threshold voltage, Von. As explained
in the preceding subsection, the diode remains forward biased immediately after switch SW is
thrown so that the pertinent diode equivalent circuit in the neighborhood of t = 0+ is the structure of Figure (2.15b).
Since the diode current, id(t), is −IR, as per (2-72), for as long as the diode remains forward biased, the model at hand delivers
Q (t)
d v (t)
d vd (t)
− I R = d + Cd d + C jf
.
(2-76)
τd
dt
dt
In the interest of analytical simplicity and tractability, the depletion capacitance component of
diode current, which is the last term on the right hand side of (2-76), can be ignored. This
simplification is reasonable in view of the fact that depletion capacitance Cjf is rarely the dominant capacitance implicit to a forward biased PN junction. Moreover, the diode voltage, vd(t),
changes only minimally under forward bias operating circumstances. Since
dQd (t)
dQd (t) d vd (t)
d v (t)
=
×
= Cd d
,
(2-77)
dt
d vd (t)
dt
dt
where (2-69) is invoked, (2-76) reduces to the form,
dQd (t) Qd (t)
−IR ≈
+
.
(2-78)
dt
τd
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A laudable attribute of the last result is that it is a first order linear differential equation in the excess charge function, even though the charge function itself depends nonlinearly on the diode
voltage. In view of (2-75) and the fact that the differential equation at hand predicts a steady
state charge value of Qd(∞) = −τdIR, the solution follows forthwith as
Qd (t) = − τd I R + τd ( I R + I F ) e − t τd , t > 0.
(2-79)
While (2-79) is the solution of (2-78), (2-78) itself applies only to the time interval, 0+ ≤ t ≤ ts
where the diode remains in its forward biased operating regime. At the diode charge storage
time, t = ts, Qd(ts) = 0, and the diode enters its reverse biased regime. Equation (2-79) predicts
this storage time as
⎛
⎛
I ⎞
V − Von ⎞
(2-80)
ts = τd ln ⎜ 1 + F ⎟ ≈ τd ln ⎜ 1 + F
⎟ .
IR ⎠
VR + Von ⎠
⎝
⎝
vi(t)
R
−
Cj
VR
+
+
−
vd(t)
id (t)
Figure (2.18). Equivalent circuit for the network in
Figure (2.16) for the case in which the
PN junction diode is reverse biased.
At t = ts, the diode voltage, vd(ts), remains at barely the diode threshold level, Von. At
time ts+ and beyond, the depleted nature of the transition region forces the diode into a reverse
bias state so that the applicable diode model is the topology offered in Figure (2.15b). Ignoring
the extremely small saturation current, Io, in this model, the applicable equivalent circuit of the
network in Figure (2.16) for t ≥ 0+ is the topology shown in Figure (2.18), where, of course, Cj
represents the depletion capacitance defined by (2-65). Clearly,
d v (t)
−VR = RC j d + vd (t) for t ≥ to + .
(2-81)
dt
A closed form solution of this equation is impossible owing to the nonlinear dependence of capacitance Cj on diode voltage vd(t). Although (2-81) can be solved numerically with
readily available software, it should be noted that the expression is premised on several simplifying modeling and circuit approximations that render dubious the engineering value of exact
numerical answers. Most importantly, the reader is reminded that the purpose of circuit analysis
is rarely the generation of precise results. Indeed, precise and consistently reproducible circuit
performance results can rarely be generated in electronics because of unavoidable device
processing vagaries, uncertainties in the numerical values of key physical device parameters, and
nonzero circuit manufacturing tolerances. Rather, the purpose of circuit analysis is the generation of approximate, but nonetheless meaningful, disclosures that insightfully bracket
performance results in such a way as to encourage and facilitate design innovation.
In the present case, it is likely that a supremely accurate delineation of diode turn off
time is unnecessary in the vast majority of high-speed system applications. Instead, a worst case
(largest) switching time might prove practicable. To this end, a large time constant, RCj, inherently slows the turn off transient and thus, replacing Cj by its largest possible value, which is the
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zero bias depletion capacitance, Cjo, arguably reflects engineering prudence. With Cj = Cjo, a
constant capacitance, a closed form solution to (2-81) is indeed possible and is, in fact,
(t − t )
RC
s
jo
vd (t) ≈ − VR + (VR + Von ) e
for t ≥ ts + .
(2-82)
As postulated earlier, the diode current collapses to zero at time t = (ts + tc), where the diode
voltage, vd(t), rises, and thus the diode depletion capacitance charges, to about 90% of (−VR).
Using (2-82) it is readily shown that
⎡ ⎛ V ⎞⎤
tc = RC jo ln ⎢10 ⎜ 1 + on ⎟ ⎥ ≈ 2.3 RC jo ,
(2-83)
VR ⎠ ⎦
⎣ ⎝
where the additional liberty of presuming Von << VR is exploited. The overall diode turn off time
is therefore seen to be
⎡ ⎛ Von ⎞ ⎤
⎛
V − Von ⎞
toff ≈ τd ln ⎜ 1 + F
⎟ + RC jo ln ⎢10 ⎜ 1 +
⎟⎥
VR + Von ⎠
VR ⎠ ⎦
⎝
⎣ ⎝
(2-84)
⎛
VF ⎞
≈ τd ln ⎜ 1 +
⎟ + 2.3 RC jo .
VR ⎠
⎝
Equation (2-84) suggests that engineering efforts directed toward reducing the diode
turn off time must be directed toward reducing both the charge storage time, which is given by
the first term on the right hand side of either form of the expression, and the charging time,
which is highlighted by the last terms on the right hand sides. Both of these time components are
minimized through deployment of minimal geometry diodes since capacitance Cjo is directly
proportional to cross section junction area and lifetime τd decreases progressively as device feature sizes decrease. The storage component of the turn off transient is seen as approaching zero
if VF << VR. Since voltage VF must be at least as large as the diode threshold voltage in order to
ensure diode forward biasing in the steady state, this optimization procedure is tantamount to
requiring suitably large VR. In effect, large VR can be thought of as a vehicle for energetically
removing the excess charge stored in the junction transition region, thereby promoting a reduced
storage time component. But care must be exercised when adopting this design tack since voltage VR ultimately reverse biases the PN junction diode and must therefore be smaller than the diode breakdown voltage. On the other hand, the charging time component is reduced through use
of a small current limiting resistance, R. Once again, however, design care is required in that too
small a value of resistance R gives rise to large forward and “wrong way” currents that may incur
significant self heating in the diode (which tends to increase lifetime τd and capacitance Cjo) or
even outright thermally-induced device damage.
2.4.1.2. Compensation Of The Switching Transient
The foregoing discussion of the turn off effectiveness of a large applied reverse voltage,
VR, provides a clue as to how the circuit in Figure (2.16) might be compensated to achieve reduced turn off time. In particular, a large VR motivates the exodus of stored excess charge from
the junction transition layer if the input voltage, (−VR), can be applied promptly across the diode
terminals. Unfortunately, the current limiting resistance, R, acting in concert with the diffusion
capacitance associated with the excess charge, serves to delay this vigorous reverse biasing for at
least as long as the storage time, ts. But if a so-called speedup capacitance, C, is appended as a
shunting element across resistance R, as suggested in the modified circuit diagram of Figure
(2.19), any sudden change in the input port voltage, vi(t), is instantly transmitted to the diode
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terminals. Such instant transmission derives from the inability of a capacitance to change its
terminal voltage instantaneously when said capacitance conducts finite current. In particular, at
time t = 0−, vi(0−) = VF, and the diode voltage, vd(0−), is approximately Von. This latter voltage
supports the steady state diode current, IF, defined by (2-71). The indicated circuit speedup
capacitance, C, is accordingly charged initially to a voltage, (VF − Von). This voltage is sustained
at time t = 0+ when the input voltage changes abruptly to the level, vi(0+) = −VR. Consequently, the diode voltage swings instantly from Von at time t = 0− to (Von − VR) at time t = 0+.
To the extent that VR is suitably large, but not so large as to cause reverse bias voltage breakdown of the PN junction, the diode is effectively reverse biased at the instant that switch SW in
the circuit is thrown. In principle therefore, most of the storage and charging times can be eliminated, and a turn off time of theoretically zero is possible. However, a reality check properly infers that zero storage and charging times can be achieved only within the ivy-covered confines of
a university classroom. The shortfall of the foregoing qualitative arguments is that the internal
impedances associated with both input voltage levels are never zero, thereby incurring an
unavoidable nonzero delay between the input port of the network and the diode terminals.
Nonetheless, the turn off time of the indicated diode switching network can be reduced, possibly
significantly, by the capacitance compensation technique advanced herewith.
The development of an analytical basis to the proposed compensation strategy begins
by observing in Figure (2.19) that the diode current, id(t), which in general can be approximated
by the right hand side of (2-78), satisfies
dQd (t) Qd (t)
v (t) − vd (t)
d
id (t) ≈
+
= i
+ C [ vi (t) − vd (t)] .
(2-85)
dt
τd
R
dt
At time t = 0+, vi(0+) = −VR, vd(0+) remains approximately fixed at the threshold level, Von, and
the first term on the far right hand side of (2-85) is resultantly −IR, as stipulated by (2-72).
Moreover, vi(t) changes abruptly at time t = 0, which means that its time derivative, dvi(t)/dt, for
t ≥ 0 is the impulse function, −VRδ(t). Accordingly,
dQd (t) Qd (t)
d v (t)
+
+C d
≈ − I R − CVR δ(t) for t ≥ 0,
(2-86)
dt
τd
dt
C
t
VF
=0
+ −
vc(t)
R
vi(t)
SW
+
+
−
−
+
VR
−
vd(t)
id (t)
Figure (2.19). Turn off time compensation of the switching
network in Figure (2.16) through incorporation of a capacitance, C, across the current
limiting resistance, R.
which should lay to rest any inclined reader belief that the infamous “delta function” is little
more than mere theoretic fodder. The last result applies for all positive time for which the diode
sustains a net positive excess stored charge, Qd(t) and thus remains forward biased. Since the diMinh Hsieh Department of Electrical Engineering
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ode voltage, vd(t), modulates only minimally while the diode is forward biased, the current
component, Cdvd(t)/dt, can be ignored tacitly. It follows that
dQd (t) Qd (t)
+
≈ − I R − CVR δ(t) for t ≥ 0,
(2-87)
dt
τd
for which the charge solution is readily confirmed to be
Qd (t) = − τd I R + ⎡⎣ τd ( I R + I F ) − CVR ⎤⎦ e −t τd , t > 0.
(2-88)
The storage time, ts, which is defined such that Qd(ts) = 0, now follows as
⎛
I
CVR ⎞
(2-89)
ts = τ d ln ⎜ 1 + F −
⎟ ,
I
τ
I
R
d R⎠
⎝
which is assuredly smaller than the uncompensated charge storage time posited by (2-80). Equation (2-89) suggests selecting capacitance C in accordance with
τ I
Q (0 − )
C = d F = d
,
(2-90)
VR
VR
where (2-75) has been recalled. The application of (2-90) theoretically causes zero storage time,
but the reader is once again reminded of the tacit neglect of Thévenin impedances associated
with the voltage levels, VF and VR. Impedances notwithstanding, (2-90) suffices as a pragmatic
design guideline for reducing the charge storage time, and thus the overall switching time of a
PN junction diode.
2.4.2. SMALL SIGNAL DIODE OPERATION
In numerous electronic system applications, a PN junction diode and/or the PN
junctions implicit to more advanced semiconductor devices are called upon to deliver nominally
linear current or voltage responses to applied time varying input signals. In these applications, a
necessary condition for satisfactorily linear system operation is that the diode be biased in its
forward regime where its static volt-ampere characteristic curve approximates current versus
voltage linearity for suitably constrained variations in the diode current. Specifically, this
requirement mandates two prerequisites whose fulfillment lies within the purview of the circuit
designer. First, consider the special case for which all time varying input signals applied to the
considered network are set to zero, but all static sources employed for biasing purposes remain
activated. Such a condition establishes the quiescent operating state of the considered network;
that is, the network is “quiet” in the sense that no time varying signals surface for electrical or
electronic processing. In effect, the network in question operates in a standby mode, awaiting
the eventual application of input signals. The only observed branch currents and node voltages
in standby are accordingly static, time invariant variables whose values are functionally
dependent on the topology of the quiescent network and, of course, the applied static sources.
The sole and essential purpose of these static energy sources is to pin the quiescent operating
point, or Q-point, defined by [id(t), vd(t)] = (IdQ, VdQ) of a subject PN junction diode in a
reasonably linear region of its static volt-ampere characteristic curve. Second, the network
responses generated exclusively by the applied time varying input signals must closely emulate
linearity, which implies that the resultant perturbations induced in the Q-points of all active
devices embedded in the considered circuit must be nominally linear functions of the applied
input signals. In addition to requiring that the Q-points of all active devices reside in a nominally
linear sector of their static characteristic curves, devices capable of emulating linearity
necessarily direct that the aforementioned signal-induced perturbations be sufficiently small to
inhibit instantaneous operating point excursions into substantively nonlinear regimes. This
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constraint on signal responses is the basis for the ubiquitously encountered electronic system
lexicon of small signal operation, which is often referred to as linearized operation.
2.4.2.1. Small Signal Operating Concepts
An analytical expansion of the concepts articulated in the preceding section commences
with a consideration of the electronic network example in Figure (2.20a). As is indicated in this
diagram, a signal source voltage, vs(t), together with its Thévenin resistance, Rs, is applied to the
network input terminals, 1 and 2, one of which can be the network ground. Voltage vs(t) has no
static component. More than one signal source may be used in conjunction with a given
electronic network but in this initial foray into small signal environments, no loss of analytical
generality arises from presuming the presence of only one signal source. A single PN junction
diode, whose current is id(t) and whose corresponding terminal voltage is vd(t), is incident with
terminals 3 and 4, where once again, one of the latter two terminals can be system ground. In
order to bias the junction diode in its forward volt-ampere regime, a supply voltage, VBB, is
applied between the fifth network terminal and ground. No static voltages are embedded within
the electronic network itself.
+VBB
RT
5
Rs
+
+
Linear
Network
vs(t)
−
2
3 id (t)
+
3 id (t)
1
−
vT (t)
+
−
+
vd(t)
−
Vkk
vd(t)
−
4
4
(a).
(b).
Figure (2.20). (a). Linear network driven by a time varying signal source, vs(t), whose Thévenin
resistance is Rs, applied between terminals 1 and 2. Biasing for the indicated diode is
arranged by the supply voltage, +VBB. (b). Equivalent circuit showing the effective
static voltage, Vkk, the effective Thévenin signal voltage, vT(t), and the Thévenin resistance, RT, witnessed by the diode at terminals 3 and 4.
If the network undergoing scrutiny behaves linearly in the neighborhood of its
quiescent operating point, it can be supplanted by a Thévenin equivalent circuit that drives the
diode branch. In the Thévenin representation of Figure (2.20b), Vkk is a purely static voltage
whose value is null when VBB is set to zero. Moreover, vT(t), the pertinent Thévenin signal
voltage that excites the diode, is directly proportional to the applied signal voltage, vs(t), while RT
represents the Thévenin, or output, resistance at terminals 3 and 4. In the event that more than
one input signal is applied, vT(t) becomes a linear superposition of the effects of all applied input
signal voltages or currents. In the interest of completeness, the mathematical computation of
signal voltage vT(t) derives from Figure (2.21a) as the open circuit voltage (meaning that the
diode branch is removed) developed between terminals 3 and 4 under the condition of VBB = 0.
On the other hand, RT is the ratio, Vx/Ix, in Figure (2.21b) with Ix representing an independent
current of arbitrary value and both VBB and vs(t) clamped to zero.
In Figure (2.20b),
Vkk + vT (t) = RT id (t) + vd (t) ,
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5
Rs
1
+
3
Linear
Network
vs(t)
−
5
Rs
2
1
+
Linear
Network
vT (t)
−
4
3
2
+
Vx
−
Ix
4
(a).
(b).
Figure (2.21). (a). Computation of the Thévenin signal voltage, vT(t), that effectively drives the PN
junction diode in the network of Figure (2.20). This voltage is the open circuit signal
voltage established between terminals 3 and 4 when the power supply voltage, VBB, is
supplanted by a short circuit to ground. (b). Computation of the Thévenin resistance, RT,
associated with signal vT(t) in (a). This resistance is the voltage to current ratio, Vx/Ix,
with both the input signal and the power supply voltage set to zero.
with the implicit understanding that (2-1) defines the low frequency relationship of diode current
id(t) to diode voltage vd(t). This relationship is plotted for a representative diode in the id(t)-vd(t)
Cartesian plane of Figure (2.22) as the “diode characteristic curve.” Under quiescent signal
conditions, the input signal, vs(t), and hence the Thévenin signal voltage, vT(t), is zero, whence
(2-91) implies
Figure (2.22). Graphical interpretation of the first order electrical dynamics of the PN junction diode in the network of Figure (2.20).
v (t) V
id (t) = − d + kk .
(2-92)
RT
RT
When plotted in the aforementioned id(t)-vd(t) plane, this expression is a straight line whose slope
is −1/RT, whose vertical (current) axis intercept is Vkk/RT, and whose horizontal (voltage) axis
intercept is vd(t) = Vkk. This straight line is plotted as the load line in Figure (2.22). In effect, (292) and (2-1) comprise a system of two independent equations in the diode current and voltage
variables, id(t) and vd(t), respectively. Their simultaneous solution, which is the intersection of
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the load line with the diode characteristic curve, uniquely defines the quiescent operating point
of the considered PN junction diode; namely, [id(t), vd(t)] = (IdQ, VdQ), as marked in the figure of
interest. Of course, the Q-point, (IdQ, VdQ), can be discerned by substituting (2-1) into (2-92) and
thence solving iteratively for the diode voltage, vd(t) = VdQ, which supports the Q-point diode
current, IdQ, in accordance with
V
nV
I dQ = I o ⎡ e dQ T − 1⎤ .
(2-93)
⎢⎣
⎥⎦
Alternatively, the piecewise linear diode model of Figure (2.5b) can be exploited to arrive at an
accurate estimate of the diode operating point.
The quiescent operating point defined herewith is merely a single volt-ampere solution
of (2-91) that corresponds exclusively to all times for which the quiescent operating
circumstance of zero input signal is mirrored. When signal is applied, the corresponding diode
current and voltage vary with time in a manner that is reflective of the time variance proscribed
by the Thévenin signal voltage, vT(t). Assume for the moment that the variation of vT(t) is
constrained in the time domain to the closed and not necessarily symmetric interval, −V2 ≤ vT(t)
≤ V1. Since voltage vT(t) merely superimposes with the static voltage, Vkk, in (2-91), the
immediate impact of nonzero signal is witnessed as a variation of Vkk from a maximum level of
(Vkk + V1), through the Q-point circumstance implicit to Vkk, to a minimum level of (Vkk − V2).
This variation is effected without altering the series resistance, RT, in the circuit and hence, the
slope of the originally deduced load line. Resultantly, the load line plotted in Figure (2.22) is
displaced, parallel unto itself, from the line labeled “load line for maximum input signal” to the
line branded “load line for minimum input signal.” The resultant time domain solutions for the
diode current and diode voltage, which necessarily reside on the diode characteristic curve in the
subject figure, lie on the emboldened diode curve segment traced by the intersection of the
perturbed load line and the diode characteristic curve. This segment is labeled in Figure (2.22)
as “locus of Q-point excursion.” In the present case, the diode current is seen as varying from a
maximum value of Id1, corresponding to vT(t) = V1, to a minimum of Id2, which is the result of
vT(t) = −V2. The diode voltage perturbation accompanying these current changes is minimal, as
is indicated in Figure (2.22), owing to the near vertical stature of the diode characteristic curve.
This observation reflects the profound and previously espoused diode current sensitivity to diode
voltage in the forward bias domain.
2.4.2.2. Small Signal Diode And Network Model
The locus of Q-point excursion in Figure (2.22) suggests viscerally that for sufficiently
small V1 and V2, the observed current change, (Id1 − Id2), about the quiescent current, IdQ, is likely
to converge to a linear function of the corresponding, and necessarily small, diode voltage
perturbation about its Q-point, VdQ. The need for suitably constrained input voltages is
underscored by a casual consideration of the effect of large V2. In particular, large V2 shifts the
original load line downward to such an extent that the intersection of the perturbed load line with
the diode characteristic curve lies conceivably on the obviously nonlinear knee of the curve,
thereby rendering the presumption of linearity between current and voltage changes
unreasonable. The figure at hand also suggests that the constrained locus of Q-point excursion,
which effectively embraces an immediately proximate region about the diode Q-point, is tailor
made for a Taylor series expansion of the diode characteristic curve about the Q-point (pun
intended). In particular,
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2
3
did
1 d 2 id
1 d 3 id
vd − VdQ +
vd − VdQ +
vd − VdQ + … , (2-94)
2
3
d vd Q
2! d v
3! d v
d Q
d Q
(
)
(
)
(
)
where the time domain notation appended to the diode current and voltage has been dropped in
favor of symbolic simplicity. Moreover, it is important to understand that each derivative on the
right hand side of this relationship is evaluated at the diode Q-point; that is, at [id(t), vd(t)] ≡ (id,
vd) = (IdQ, VdQ). Therefore, the coefficient of (vd − VdQ)n, for n = 1, 2, 3, … is a constant,
independent of diode current and diode voltage, id and vd, respectively.
While the infinite power series of (2-94) appears foreboding, its insightfully interpreted
implications are crucial to the computationally efficient analysis of electronic networks that are
properly biased and driven by suitably small signals. To wit, the voltage difference, (vd − VdQ),
represents the positive or negative perturbation of diode Q-point voltage that is incurred
exclusively by the applied input signal. This voltage difference is meaningfully symbolized as
the signal-induced voltage change, Vsig; namely,
Vsig vd − VdQ .
(2-95)
An analogous substitution can be promulgated for the signal induced change, (id − IdQ), in the
drain current; that is,
I sig id − I dQ .
(2-96)
Equation (2-94) can therefore be cast into the form,
d id
1 d 2 id
1 d 3 id
2
3
I sig =
Vsig +
Vsig +
Vsig
+….
(2-97)
2
3
d vd Q
2! d v
3! d v
d Q
d Q
In light of the constant nature of each derivative term in this expression, (2-97) advances a signal
component of diode current that is dependent, albeit nonlinearly, on only the signal component
of diode voltage. Now, if the peak, root mean square, or instantaneous value of the signalinduced component, Vsig, of diode voltage is small, the square of Vsig is smaller, the cube of Vsig is
smaller yet, and in general, all non-unity powers of Vsig converge toward insignificant
proportions. But in addition to small Vsig, or perhaps in lieu of adequately small Vsig, a nominally
linear diode characteristic in the neighborhood of the Q-point generates a derivative did/dvd,
which is virtually constant even prior to numerically evaluating this derivative at the Q-point. In
turn, the second and all higher order derivatives of the diode current with respect to the diode
voltage approach zero (prior to their evaluation at the Q-point) if the current versus voltage
slope, did/dvd, is almost constant. Thus, for small Vsig and/or for reasonable linearity of the diode
characteristic curve in the immediate neighborhood of the diode Q-point, (2-97) collapses to
di
I sig ≈ d Vsig ,
(2-98)
d vd Q
which comprises little more than an elementary reflection of Ohm’s law. Specifically, for
sufficiently small signal voltages and/or nominal linearity of the diode characteristic curve in the
neighborhood of the diode Q-point, the signal component, Isig, of the diode current relates to the
signal component of diode voltage, Vsig, in accordance with the classic Ohm’s law relationship,
Vsig
I sig ≈
.
(2-99)
rd
In (2-99), parameter rd is termed the small signal resistance of the subject PN junction diode.
Since
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d id
1
=
,
(2-100)
rd
d vd Q
rd is clearly the inverse of the slope of the diode characteristic curve at the Q-point. Recalling
(2-1) or (2-3),
nVT
nVT
(2-101)
≈
.
rd =
VdQ nVT
I dQ
Ioe
Observe in the last result that progressively larger diode Q-point currents breed correspondingly
smaller diode resistances. Accordingly, PN junction diodes operated at large quiescent currents
emulate short circuits for small applied signals. This contention synergizes with the observation
in Figure (2.22) that the diode voltage changes garnered for relatively significant diode current
changes are very small. Indeed, if the slope of the diode characteristic curve in the forward bias
regime were vertical in Figure (2.22), the diode voltage change for any change in diode current is
zero, as is rd in (2-100).
Before proceeding further, it should be noted that resistance rd in (2-100) or (2-101) is
merely a special case of the resistance, rdm, introduced in (2-6) in conjunction with the piecewise
linear model of a PN junction diode. In particular, rdm, as introduced earlier, is the inverse of the
slope of the static diode characteristic curve evaluated at an arbitrary volt-ampere coordinate,
(Idm, Vdm). In piecewise linear analyses, current Idm is generally selected as the estimated
maximum current conducted by the diode under static operating circumstances. On the other
hand, rd in (2-100) is a similar characteristic curve inverse slope, but it is evaluated expressly at
the quiescent operating point of the diode. It follows that rdm ≡ rd for the special case of Idm =
IdQ, and in general, resistance rd is about as small as the scant few ohms previously witnessed as
indigenous to resistance rdm.
If (2-95), (2-96), (2-99), and (2-100) are merged with the power series expansion of (294),
id = I dQ +
Vsig
rd
+ I dh (Vsig ) = I dQ +
vd − VdQ
+ I dh (Vsig ) ,
rd
(2-102)
where
∞
1 ⎛ d k id
I dh (Vsig ) =
⎜
k ! ⎜⎝ d vdk
k =2
⎞ k
(2-103)
⎟Vsig
⎟
⎠
is the sum of all nonlinear current components in (2-94) that involve the second and higher order
derivatives of the diode characteristic curve. Equation (2-102) leads to the PN junction diode
behavioral model advanced in Figure (2.23a), where in practice, the power series represented by
the high order current component, Idh(Vsig), is truncated at user discretion after an appropriate
number of terms that is consistent with the accuracy requirements of the analysis task. If Vsig is
small and/or the diode volt-ampere characteristic curve is reasonably linear in the immediate
neighborhood of its quiescent operating point, Idh(Vsig) is negligible in comparison to the sum of
the first two terms on the right hand side of (2-102). In this situation, (2-102) collapses to
Vsig
vd − VdQ
(2-104)
id ≈ I dQ +
= I dQ +
,
rd
rd
and the behavioral structure in Figure (2.23a) reduces to the equivalent circuit given in Figure
(2.23b). Recalling (2-96), the model in Figure (2.23c) can be promoted as a simple small signal
alternative to the topology in Figure (2.23b).
∑
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id (t)
J. Choma
id (t)
+
Vsig
−
+
VdQ
+
+
vd(t)
−
Vsig
+
vd(t) IdQ
−
rd
−
Idh(Vsig)
+
VdQ
−
−
Isig
(a).
id (t)
Isig
+
Vsig
+
vd(t) IdQ
−
rd
−
+
VdQ
−
+
Vsig
−
rd
Isig
(b).
(c).
Figure (2.23). (a). Behavioral model of a PN junction diode. The diode terminal voltage, vd(t), is
presumed to be the superposition of a Q-point voltage component, VdQ, and a time
varying signal component, Vsig. (b). The model of (a) simplified to reflect the
presumption of small input signals and/or reasonably good linearity of the diode
characteristic curve in the immediate neighborhood of the operating point. (c).
Small signal model of the PN junction diode.
The relevance of the simple small signal model in Figure (2.23c) can best be
appreciated by returning to the network representation in Figure (2.20b) and using the last result
to quantify the diode current, id(t). Specifically,
Vsig ⎞
⎛
(2-105)
Vkk + vT (t) = RT ⎜ I dQ +
⎟ + Vsig + VdQ .
rd ⎠
⎝
But the static voltage, Vkk, appears in the output port loop of the network solely to bias the diode
at a suitable Q-point. This is to say that under quiescent operating conditions for which vT(t) = 0
and hence, Vsig = 0,
(2-106)
Vkk = Rt I dQ + VdQ .
Upon insertion of (2-106) into (2-105), the network equilibrium relationship that arises is
Vsig
(2-107)
vT (t) =
( RT + rd ) = I sig ( RT + rd ) ,
rd
which corresponds to the small signal network model submitted as Figure (2.24).
At least three important sidebars accompany the modeling disclosure in Figure (2.24).
First and perhaps most obviously, the diode in the circuit of Figure (2.20b) is merely supplanted
by the small signal, two terminal, purely resistive diode model advanced in Figure (2.23c).
Second, the network model in Figure (2.24) at hand is incapable of generating any information
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about the quiescent currents and voltages indigenous to the diode, largely because the static
supply used to establish the Q-point is inherently vanquished by the small signal analysis
methodology. In fact, the practical utilization of the small signal network model requires a
priori knowledge of the quiescent operating point of the diode in order that the small signal
diode resistance, rd, can be computed in accordance with (2-101). Third, the current, Isig,
supported by the circuit of Figure (2.24) is not the net diode current, id. Rather, Isig is only the
small signal component of the diode current. The net diode current derives from (2-96), which
obviously requires a numerical delineation of the Q-point diode current, IdQ. Similarly, the small
signal diode voltage, Vsig = rdIsig in Figure (2.24) is not the net diode voltage, vd, but is, in fact,
only the small signal component of said voltage. The overall diode voltage is governed by (295), whose application requires a numerical value for the diode Q-point level, VdQ.
RT
+
vT (t)
+
−
+
Vkk
RT
3 id (t)
+
vd(t)
vT (t)
−
−
−
4
3 Isig
+
Vsig
rd
−
4
Figure (2.24). Equivalent small signal model for the output port of the network addressed in Figure (2.20).
A final observation is that the small signal diode model of Figure (2.23c), as well as the
network model it configures in Figure (2.24), is limited to only low frequency signal processing
environments. If the Fourier spectrum implicit to the Thévenin signal voltage, vT(t), personifies
critically important high frequencies or if timing issues associated with the transient response to
vT(t) are relevant to an engineering problem at hand, the small signal diode model must be
embellished to include the effects of charge storage at the junction. This modeling enhancement
is a straightforward task since charge storage phenomena, as witnessed in conjunction with the
discussion surrounding (2-85), precipitates only a single additional current component to the net
observed diode current. This current is recalled to be dQd(t)/dt, where Qd(t) represents the excess
charge stored in the junction transition region. In turn, the time derivative of the excess charge is
equivalent to currents conducted by the shunt interconnection of two capacitances, as inferred by
the high frequency small signal diode model postulated in Figure (2.25). The capacitance, CdQ,
is the junction diffusion capacitance, which by (2-69) is
τd I dQ
(2-108)
CdQ ≈
,
nVT
where, of course, τd is the average lifetime of free charge carriers that transit the transition layer
of a forward biased diode, n is remembered to be the junction injection coefficient, and VT is the
Boltzmann voltage. Appealing to (2-70), CjQ in the model of Figure (2.25) is
−m
⎛
VdQ − nVT ⎞ j
.
C jQ ≈ C jo ⎜ 1 −
(2-109)
⎟
⎜
⎟
V
j
⎝
⎠
In (2-109), use is made of the fact that the diode turn on voltage, Von in (2-70), lies below the
diode Q-point voltage, VdQ, at which the diode characteristic is approximated by the linear terms
of a Taylor series expansion, by the amount, nVT.
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Isig
+
Vsig
+
vd(t)
−
−
VdQ
+
+
Vsig
−
rd
CdQ
CjQ
−
Figure (2.25). High Frequency, small signal model for the PN junction diode. Capacitance
CdQ is the diffusion capacitance of the junction, while CjQ represents the
depletion capacitance in the forward bias regime.
EXAMPLE #2.4:
In the simple attenuator shown in Figure (2.26a), the input signal is a
small amplitude sinusoid, vs(t), whose phasor is denoted in Figure (2.26b)
by the voltage source, Vs. Resistance R includes the internal resistance of
the signal source. The static voltage, VBB, is used to bias the diode in its
forward regime where the quiescent diode current is set to IdQ and the
corresponding quiescent diode voltage is VdQ. If the small signal resistance of the diode at the indicated Q-point is rd and if the effective total
capacitance across the diode is CT (diffusion plus depletion components),
derive an expression for the transfer function, H(jω) = Vo/Vs. Additionally, determine the radial 3-dB bandwidth, say B, of the circuit. Finally,
explain the operation of the attenuator at low signal frequencies.
R
R
vo(t)
+
id (t)
vs(t)
−
+
Vo
vd(t)
+
+
VBB
rd
Vs
−
CT
−
−
(a).
(b).
Figure (2.26). (a). Simple attenuator circuit addressed in Example #2.4). The static supply voltage, VBB, establishes a diode quiescent operating point at [id(t),
vd(t)] = (IdQ, VdQ). Observe that the output response, vo(t), in the time domain is identical to the voltage, vd(t), developed across the PN junction diode. (b). Small signal, high frequency model of the attenuator in (a).
SOLUTION #2.4:
(1).
The disclosures of the present section of material forge the small signal equivalent circuit of the attenuator shown in Figure (2.26b). In this model, resistance rd is defined
by (2-101), while capacitance CT, is the sum of the capacitances, CdQ and CjQ in (2-
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108) and (2-109), respectively. Voltage VBB does not appear in the small signal model
because it is deployed exclusively to establish the quiescent operating point about
which the output phasor response, Vo, is perturbed in proportion to the phasor, Vs, of
the applied input sinusoid. Moreover, the small signal model of a diode, or of any
other nonlinear element, can never surrender any information regarding the circuit Qpoint.
(2).
An inspection of the topology in Figure (2.26b) reveals
rd
rd
V
1 + jωrd CT
rd + R
H ( jω ) = o =
=
.
(E4-1)
r
Vs
1 + jω ( rd R ) CT
d
+ R
1 + jωrd CT
In this result, the zero frequency value, H(0), of the network transfer function, which
is immediately evident from an inspection of the subject circuit model is
rd
(E4-2)
H (0 ) =
,
rd + R
and by (2-101),
rd
nVT
H (0 ) =
=
.
(E4-3)
rd + R
nVT + RI dQ
Accordingly, as IdQ is varied, through changes in the input supply voltage, VBB, the
zero frequency “gain” (which is always less than one) can be made to vary over a prescribed range. For example, maximum gain, or minimum attenuation, is offered by
small values of IdQ, while minimum gain (corresponding to maximal attenuation) is
provided by large IdQ.
(3).
The radial 3-dB bandwidth, B, is the value of the radial signal frequency, ω, for which
the magnitude of the network transfer function is 3-dB below, or a factor of root two
smaller, than the zero frequency gain of the circuit. Since the zero frequency gain of
the circuit undergoing investigation is little more than the numerator term on the right
hand side of (E4-1), the 3-dB bandwidth evolves by mere inspection of the subject
expression. In particular,
1
1
1
B =
,
(E4-4)
≈
=
( rd R ) CT rd CT rd CdQ + C jQ
(
)
where the reasonable presumption that R >> rd has been invoked. If (2-108) is substituted into (E4-4),
1
(E4-5)
B ≈
,
⎛ nVT ⎞
τd + ⎜
⎟C
⎜ I dQ ⎟ jQ
⎝
⎠
which projects inverse carrier lifetime as a fundamental limitation on the achievable
3-dB bandwidth of the circuit. In fact, the bandwidth approaches 1/τd only for the
maximal attenuation case precipitated by large quiescent diode current, IdQ.
COMMENTS: Although the circuit considered herewith can function as an attenuator, it
is hardly a candidate for an attenuator award. Several shortfalls are
immediately evident. To wit, the attenuation provided by the circuit at
low frequencies is of the order of the ratio, rd/R, which implies an attenuation range of roughly 1/10 (−20 dB) to 1/100 (−40 dB). While this factor
of ten or so attenuation range is appropriate to numerous system applications, it comes at the price of enormous changes in the quiescent drain cur-
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rent, which in turn spawns concerns about circuit power dissipation and
circuit linearity in the immediate neighborhood of low Q-point currents.
Moreover, the degree of attenuation is sensitive to junction operating
temperature because resistance rd is proportional to the Boltzmann voltage
(which is directly dependent on absolute temperature) and inversely
dependent on diode current, whose significant temperature sensitivity in
the absence of appropriate compensation is legendary, as argued earlier in
the chapter. One attribute of the structure is that because the diode small
signal resistance, rd, is very small, its 3-dB bandwidth can theoretically be
well into the tens of gigahertz. Unfortunately, this bandwidth is itself
dependent on temperature, as well as on the attenuation factor (because of
its functional dependence on Q-point diode current). Another arguable
attribute is circuit simplicity. But while simplicity is always laudable from
processing and manufacturing perspectives, not all simplistic design approaches prove satisfying.
EXAMPLE #2.5:
The application and implications of the concepts underlying small signal
analysis techniques are not restricted to PN junction diodes. They are
broadly pertinent to all two terminal elements that exhibit nonlinear voltampere characteristics. As is demonstrated in subsequent chapters, small
signal analysis methods can even be extended to embrace nonlinear multiport networks. To these ends, consider Figure (2.27), which depicts a two
terminal resistance for which the low frequency volt-ampere characteristic
abides by the nonlinear relationship,
0, V < Vh
I =
,
V ⎞
2⎛
β (V − Vh ) ⎜ 1 +
⎟ , V ≥ Vh
Vk ⎠
⎝
where β = 0.05 siemens/volt, Vh = 0.6 volt, and Vk = 15 volts. Evaluate
the small signal resistance, say r, of this nonlinear element when it is biased at a quiescent voltage drop of 850 mV.
I
+
V
−
0, V < Vh
I =
V
2⎛
ß (V − Vh ) ⎜ 1 +
V
k
⎝
⎞
⎟ , V ≥ Vh
⎠
Figure (2.27). The two-terminal nonlinear resistor
studied in Example #2.5.
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SOLUTION #2.5:
(1).
For β = 0.05 siemens/volt, Vh = 0.6 volt, and Vk = 15 volts, the quiescent current, IQ,
conducted by the resistance for a quiescent terminal voltage, VQ, of 0.85 volt, evaluates to
VQ ⎞
2⎛
(E5-1)
IQ = β VQ − Vh ⎜ 1 +
⎟ = 3.302 m A .
Vk ⎠
⎝
(
)
(2). For V ≥ Vh, the linear approximation of the Taylor series expansion of the given voltampere characteristic curve about the stipulated quiescent operating point is
dI
(E5-2)
I ≈ IQ +
V − VQ ,
dV Q
(
)
where IQ = 3.302 mA, VQ = 0.85 volt, and the indicated derivative evaluated at the Qpoint represents the inverse of the desired small signal resistance, r. It is a straightforward matter to confirm that
IQ
VQ ⎞
⎛
1
dI
(E5-3)
=
+ 4 β IQ ⎜ 1 +
⎟ = 26.63 m .
r
dV Q
VQ + Vk
Vk ⎠
⎝
It follows that the small signal resistance at V = VQ = 0.85 volt is r = 37.56 Ω.
20
Nonlinear
Resistance
Characteristic
Current, I (mA)
15
10
5
IQ
0
0
0.2
0.4
0.8 V Q
0.6
1
1.2
-5
Linear Taylor
Series Approximation
-10
Voltage, V (volts)
Figure (2.28). Plot of the volt-ampere characteristic of the nonlinear resistance examined in
Example #2.3. Superimposed on the subject characteristic is the linear approximation of the Taylor series expansion of the curve about the Q-point.
COMMENTS: The nonlinear resistance addressed herewith emulates a diode in the sense
that the current conducted by the element is zero for voltages less than an
effective threshold level, Vh, while for voltages larger than Vh, the current
conducted by the element rises monotonically. Actually, the element at
hand is a diode realized with a metal-oxide-semiconductor field-effect
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transistor (MOSFET), as the reader is to witness in a subsequent chapter.
The evaluation of the requested small signal resistance is quite straightforward, amounting to little more than an evaluation of the slope of the device characteristic curve at the stipulated quiescent operating point. An
appreciation of the accuracy and pertinence of the resistance computation
is another matter that is worthy of at least tacit attention. To this end, the
device characteristic curve is plotted in Figure (2.28), as is the Taylor series approximation projected by (E5-2). An even casual comparison of the
actual curve and the straight line Taylor approximation, which is
foundational to the small signal resistance model, reveals the potential for
substantive modeling errors if (E5-2) is invoked carelessly in an engineering application. For example, if the differences between the two curves
are to be held to within ±10%, the terminal voltage must be restricted to
the range, 0.791 volt ≤ V ≤ 0.963 volt, which corresponds to a current
excursion from 1.91 mA to 9.91 mA.
2.4.3. STEADY STATE SINUSOIDAL RESPONSE
Because the PN junction diode and all other semiconductor elements exude inherently
nonlinear volt-ampere characteristics, their ability to function linearly can only be approximated
for signals whose amplitude variations in the time domain are suitably constrained to an immediate neighborhood of a quiescent operating point established in a region boasting reasonable voltampere linearity. As a result, and in distinct contrast with linear elements and circuits, a single
frequency sinusoid of arbitrary amplitude applied to a nonlinear element generates a distorted response that is not merely a scaled replica of the input sinusoid. By “distorted,” is meant that in
addition to a response component at the fundamental frequency of the applied sinusoid, the output signal contains various harmonics of this input signal frequency. One way of quantifying the
severity of this distorted response, and thus the extent to which the considered element or circuit
is nonlinear, entails a comparison of the amplitudes of each harmonic component of the observed
output with the response amplitude generated at the fundamental frequency.
In order to introduce the reader to the concept and engineering implications of harmonic distortion, return to the PN junction diode of Figure (2.23a) and assume that voltage VdQ
biases the diode in its forward operating regime. Assume further that the indicated signal, Vsig,
applied to the diode is the sinusoid,
Vsig = Vm cos ( ωt ) ,
(2-110)
where Vm represents the amplitude of the sinusoidal signal, and ω is its radial frequency. If frequency ω is not so large as to require an analytical embrace of charge storage phenomena at the
PN junction, (2-1) is the applicable volt-ampere relationship. Accordingly, the diode current,
id(t), corresponding to a net diode voltage of
vd (t) = VdQ + Vm cos ( ωt )
(2-111)
is
⎡ (V + V cos ωt ) nVT
⎤
(V + V cos ωt ) nVT ,
(2-112)
id (t) = I o ⎢ e dQ m
− 1⎥ ≈ I o e dQ m
⎣
⎦
where the unity term within the bracketed quantity is ignored in deference to a sufficiently large
exponentiation of the Q-point voltage, VdQ. Since the quiescent diode current (current flowing
under the zero signal circumstance implied by Vm = 0), IdQ, is
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(V )
nVT
I dQ ≈ I o e dQ
(2-112) is expressible as
J. Choma
(2-113)
,
id (t) ≈ I dQ e X m cos ωt ,
(2-114)
where
Vm
nVT
is the sinusoidal signal amplitude normalized to the effective Boltzmann voltage, nVT.
Xm =
(2-115)
Equation (2-114) defines the diode current response to a voltage input comprised of the
superposition of a biasing level, VdQ, and a sinusoidal signal whose amplitude is Vm. The expression in question can be expanded into its Fourier series to reveal all frequencies contained in the
current response, as well as the amplitudes associated with these individual frequency constituents. In particular[3],
∞
⎡
⎤
(2-116)
id (t) ≈ I dQ ⎢ Bo ( X m ) + 2 Bn ( X m ) cos ( nωt )⎥ ,
⎢⎣
⎥
n =1
⎦
where Bn(Xm) is the nth order modified Bessel function expressed as a function of the normalized
sinusoidal signal amplitude, Xm. While tabulations and a variety of relationships involving modified Bessel functions can be found in the literature[4], two useful and reasonably accurate empiricisms are
∑
( X m 2) n
for X m < 5, & n = 0, 1, 2, 3, "
n!
Bn ( X m ) ≈
⎛
n2 ⎞
⎜1 −
⎟ for X m ≥ 5, & n = 0, 1, 2, 3, "
2X m ⎟⎠
2π X m ⎜⎝
e Xm
.
(2-117)
Equation (2-116) projects an amplitude of the fundamental frequency component of diode current of 2B1(Xm). It also advances a second harmonic amplitude of 2B2(Xm), a third harmonic amplitude of 2B3(Xm), and in general, an nth harmonic amplitude of the diode current in
the amount of 2Bn(Xm). Introduce the amplitude magnitude ratio, αn(Xm), as
2Bn ( X m )
Bn ( X m )
αn ( X m ) =
for n = 2, 3, 4, 5, " .
(2-118)
2B1 ( X m )
B1 ( X m )
Then, a metric commonly adopted to quantify the degree of nonlinearity in a device or a system
is the total harmonic distortion, THD, which is
THD ∞
∑ αn2 ( X m )
,
(2-119)
n=2
and is generally expressed as a percentage. A careful consideration of the foregoing defining
relationship suggests that the THD is the ratio of the root mean square contribution of all
harmonics of the fundamental frequency component to the root mean square value of the
fundamental frequency component itself. Alternatively, it may be viewed as the average power
contributed by the harmonics, normalized to the average power associated with the fundamental
frequency. In addition to expressing the total harmonic distortion as a percentage metric, the
THD is commonly cast in units of decibels and to this end,
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⎡ ∞ 2
⎤
(2-120)
THD(dB) = 20 log (THD) = 10 log ⎢
αn ( X m ) ⎥ ,
⎢⎣ n = 2
⎥⎦
where the indicated logarithms are executed to base 10. Thus, THD(dB) = –60 dB, for example,
infers that THD = 0.1% or equivalently, that the fundamental frequency component of the applied signal boasts an amplitude that is 1,000-times larger than the root mean square contribution
of the amplitudes of all harmonic components. It should be understood that while (2-119) and
(2-120) are applicable to all nonlinear elements excited by a single frequency sinusoid whose
amplitude, Xm, is appropriately normalized, (2-118) applies only to PN junctions excited by a
single frequency sinusoid. Moreover, (2-118) is restricted to only low signal frequencies in that
the diode characteristic equation of (2-112), which tacitly ignores charge storage phenomena,
serves as the basis for the current response formulation of (2-116).
∑
0
1
2
3
4
5
6
7
8
9
10
Normalized Harmonic Amplitude
1
0.1
α 2 (X m )
α 3 (X m )
0.01
α 4 (X m )
α 5 (X m )
0.001
0.0001
Normalized Signal Amplitude, X m
Figure (2.29). The normalized harmonic amplitudes, αn(Xm), as defined by (2-118), plotted as a
function of the normalized amplitude of a sinusoid applied to a biased PN junction
diode. Harmonics through only the fifth order are explicitly considered.
Figure (2.29) depicts the behavior of the harmonic amplitude ratio, αn(Xm), as a function of the normalized amplitude, Xm, for the second through fifth harmonics. The curves depicted in the plot derive from tabulated values of the modified Bessel function, as opposed to
relying on the approximate relationships given in (2-117). Note that for any value of Xm, these
amplitude ratios decrease monotonically with the order, n, of the harmonic, although the amount
of such an observed decrease diminishes with progressively larger Xm. This is to say that for
reasonably small signal amplitudes, higher order harmonics have a progressively decreasing impact on the overall response, which in this case is a diode current. As might be expected, the harmonic amplitude ratio for any harmonic order increases monotonically with the normalized
signal amplitude. Indeed, the harmonic ratio appears to converge toward one for large signal
amplitudes, independent of the actual harmonic order.
The curves in Figure (2.29), coupled with (1-119), generate the total harmonic distortion characteristic shown in Figure (2.30). Although (2-119) is an infinite series, only terms
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through the fifth harmonic are considered in the latter figure. The SPICE circuit simulation software examines the effects of nine harmonic terms in the course of its harmonic distortion analysis, but for most manual analyses, a consideration of the first three to five harmonics proves
sufficient. The news proclaimed by Figure (2.30) is not good in that it shows that the total
harmonic distortion rises rapidly with applied signal amplitude to unacceptable levels. For
example, 10% diode current distortion to an input sinusoid, which is hardly acceptable in the vast
majority of modern communication systems, requires a normalized signal amplitude of only
about Xm = 0.4, which corresponds at room temperature to a sinusoidal signal amplitude of
approximately 10.4 mV. In short, an applied sinusoid whose amplitude is about 10 mV produces
about 10% of THD.
120
Total Harmonic Distortion (%)
100
80
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
Normalized Signal Amplitude, X m
Figure (2.30). Total harmonic distortion, plotted as a function of the normalized amplitude of a
sinusoid applied to a biased PN junction diode. Harmonics through only the fifth
order are explicitly considered.
Harmonic distortion aside, another disconcerting effect of signal overstress is an effective shift in the quiescent operating point imposed on the device undergoing examination. In (2116), each of the infinity of signal components embodied by the second term in the bracketed
quantity on the right hand side has zero average value because each of these terms is a simple
sinusoid. It follows that the average value, say IDC, of the diode current is
I DC = I dQ Bo ( X m ) ,
(2-121)
and not simply the quiescent current, IdQ, that might have been surmised. As is highlighted in
Figure (2.31), which plots the current ratio, IDC/IdQ = Bo(Xm) (using tabulated Bessel function
data), the average current increases dramatically with signal amplitude from the Q-point current
value evidenced at low input signal amplitudes. While the drama implied by the subject figure
may not have been initially predicted, an increase in the average current above the Q-point value
can be rationalized easily. In particular, the diode in the circuit of Figure (2.23a) prohibits a
“wrong way” or negative diode current, id(t). It necessarily converts the applied sinusoidal voltage to a unidirectional, positive diode current. In the vernacular of PN junction diode networks,
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the diode is said to rectify the response current, which is tantamount to asserting that it converts
the applied sinusoid, which has periodic positive and negative voltage values, to a current that is
forever positive. Because this diode current response is exclusively positive over time, it has
nonzero average value. This precipitated average can be expected to superimpose with the
quiescent current value set under zero signal conditions. An implicit undertone of the plot in
Figure (2.31) is that large amplitude sinusoids applied across PN junction diodes may comprise a
destructive phenomenon in that the large average current values resulting from large signal
amplitudes may cause catastrophic thermal stress within the ohmic regions intrinsic to the device.
10000
IDC/IdQ
1000
100
10
1
0
1
2
3
4
5
6
7
8
9
10
Normalized Signal Amplitude, X m
Figure (2.31). The ratio of the average diode current to the Q-point diode current as a function of
the normalized signal amplitude, Xm.
While the total harmonic distortion metric is a reasonable quantification of the
nonlinearity implicit to a response of interest, its engineering implication is somewhat masked by
the requisite mathematics of Fourier components, Bessel functions, and the like. In an attempt to
attach meaningful engineering perspective to the THD, return to (2-112) and note therein that the
maximum achievable diode current, say Idmax, is
(V
+V
)
nV
T
(2-122)
I dmax = I o e dQ m
= I dQ e X m ,
where (2-113) and (2-115) are exploited. It follows from (2-114) that the diode current, id(t),
normalized to its maximum value, Idmax, is
I dQ e X m cos ωt
id (t)
X cos ωt − 1)
(2-123)
,
=
= e m(
X
I dmax
I dQ e m
which is depicted graphically in Figure (2.32). Observe in the subject figure that for small Xm,
and in particular, Xm = 0.4, the diode current response closely resembles a cosine wave despite
the 10% THD engendered by this normalized signal amplitude. At Xm = 2, which corresponds to
45.5% THD, distortion of the applied cosine voltage wave is plainly evident in the diode current
response. For large Xm and specifically, Xm = 10, which reflects better than 120% THD, the observed distortion is so extreme that the diode current begins to resemble a reasonably narrow,
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periodic pulse response. This pulse-like waveform derives from the fact that large signal amplitudes attempt to induce a negative diode current, which is, of course, impossible in the steady
state.
1
X m = 0.4; THD = 10%
Normalized Diode Current
0.8
0.6
X m = 10; THD = 120.8%
0.4
X m = 2.0; THD = 45.5%
0.2
0
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
Normalized Time, ωt /2 π
Figure (2.32). Normalized diode current response to an applied sinusoidal voltage whose normalized amplitude is Xm = Vm/nVT. The current scale is normalized to the maximum
achievable diode current, Idmax, defined in (2-122).
2.5.0. DIODE APPLICATIONS
PN junction diodes and other semiconductors that emulate diode behavior enjoy widespread utility in both integrated and discrete component electronic systems. This section provides a few examples of these applications. Other illustrations of diode utility and versatility,
particularly concerning thermal compensation of biasing networks, appear in subsequent
chapters. No attempt is made herewith to document diode applications exhaustively, nor is any
interest shown in a definitive mathematical analysis of the few considered examples. Rather, the
intent of this section is to demonstrate how meaningful first order mathematical analyses of
practical diode applications are undertaken as a prelude to appropriate computer-aided analyses,
which are foundational to the engineering decision process that underpins circuit design.
2.5.1. LOGARITHMIC AMPLIFIER
A logarithmic amplifier, which is often referenced as a compression amplifier, delivers an output response that is proportional to the natural logarithm of the input signal. It is commonly used in instrumentation, recording, and certain types of communication systems for which
applied signals having a broad range of amplitudes, and thus a wide dynamic range, must be
processed so that they can drive subsequent networks or media characterized by limited dynamic
range.
A simple example of a logarithmic stage appears in Figure (2.33). In this diagram, a diode is connected between the inverting input and output ports of an operational amplifier (opMinh Hsieh Department of Electrical Engineering
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amp). The applied input signal voltage, Vs, whose intrinsic Thévenin resistance is absorbed into
the indicated circuit resistance, R, is also incident with the inverting input port of the op-amp. It
is assumed that the average value of Vs is a positive voltage and since the output voltage, Vo,
swings negative for positive Vs, the diode is forward biased. Accordingly, the diode current, Id,
is non-negative and relates to the diode voltage, Vd, in accordance with (2-3). But since the forward biased diode acts as a low resistance feedback element around the op-amp, voltage v, at the
op-amp input port is driven to near zero if the op-amp provides large open loop gain. If the opamp is additionally characterized by a very large input resistance, the input current, i, flowing
into the inverting input port of the op-amp is nearly zero. It follows that the diode and source
circuit currents, Id and Is, respectively, are virtually identical. Thus,
Id
+
Is
Vs
R
+
v
−
i
−
+
Vd
−
−Op-Amp
+
Vo
Figure (2.33). Basic schematic diagram of a logarithmic
(compression) amplifier. Biasing for the
operational amplifier is not shown.
⎛I ⎞
Vo ≈ − Vd ≈ − nVT ln ⎜ d ⎟ ,
⎝ Io ⎠
(2-124)
while
Vs
.
(2-125)
R
The substitution of (2-125) into (2-124) leads immediately to the desired result; namely,
⎛ V ⎞
(2-126)
Vo ≈ − nVT ln ⎜ s ⎟ .
⎝ RI o ⎠
The signal compression forged by the amplifier at hand is significant. For example, assume in (2-126) that R = 1 KΩ and Io = 50 fA at room temperature. For Vs = 5 mV, (2-126)
yields Vo = −18.42 nVT, which is about −479 mV at room temperature. On the other hand, if Vs
= 500 mV, which corresponds to an input signal dynamic range of 40 dB, Vo in (2-126) is −23.03
nVT, or almost 600 mV at room temperature. The resultant ratio of output voltages corresponding
to the rather striking 5 mV to 500 mV of input signal swing is only about 1.25, or less than 2 dB!
But before pontificating the virtues of the compression amplifier with overt fervor, recall that (2126) effectively relies on an ideal op-amp, which is available only in academe and is progressively more difficult to emulate as the signal frequencies implicit to the input voltage, Vs, rise.
Moreover, (2-126) suggests potentially significant temperature sensitivity issues because of the
dependence of the output voltage on Boltzmann voltage VT and diode leakage current Io.
I s ≈ Id ≈
2.5.2. EXPANDER CIRCUIT
The expander circuit diagrammed in Figure (2.34) performs the inverse of the signal
processing function executed by the compression network of Figure (2.33). As such, it is often
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used in conjunction with the compression circuit, in that it restores a logarithmically compressed
response to its original dynamic range. Analogous to the compression amplifier, an op-amp
boasting very large open loop voltage gain and very large input impedance is used in the expander. This op-amp clamps the indicated input current, i, to zero and in concert with the feedback resistance, R, the input port voltage, v, is remanded to zero. As a result, the voltage, Vs, of
the signal source, which is presumed to be characterized by a negligibly small Thévenin resistance, is dropped entirely across the diode, the current, I, equates to the diode current, Id, and the
output response, Vo, is simply the negative of the resistive drop, RI. In view of these observations,
I
+
Vs
Id
+
Vd
−
+
v
−
i
−
R
−Op-Amp
+
Vo
Figure (2.34). Basic schematic diagram of an expander
amplifier. Biasing for the operational
amplifier is not shown.
Vo = − IR = − I d R ≈ − I o R eVs nVT ,
(2-127)
which confirms an output voltage proportional to the base of natural logarithms exponential of
the applied signal voltage.
2.5.3. POWER SUPPLY
As has already been underscored, electronic systems designed to process applied input
signals in as linear a fashion as possible require that their internal semiconductor elements be biased at suitable quiescent operating points. The establishment of these operating points necessitates internal or external power supplies that are designed to generate static voltages and currents
that support these Q-points. In portable electronics, such supplies may be as simple as one or
more batteries and perhaps an appropriate regulator that desensitizes the device Q-points with respect to battery voltage degradation, variations in the currents conducted by the electrical loads
imposed on the supplies, and fluctuations in on-chip or on-board temperature. For non-portable,
commercial electronic systems, the power supplies must transform the sinusoidal, so-called
alternating or “AC” voltage available at a power outlet to the static energy required for biasing.
Since diodes are capable of transforming alternating energy having zero average, or “DC,” value
to unidirectional energy featuring nonzero DC level (discussed previously as the rectification
ability of diodes), it is not surprising that power supplies for non-portable electronics are among
the most common of applications for PN junction diodes.
Figure (2.35) abstracts the salient features of a power supply that converts alternating
power to static power. The voltage, vs(t), whose internal resistance is Rs, can be taken as the
sinusoid,
vs (t) = V p sin ( ωt ) ,
(2-128)
where in the United States, the root mean square line voltage is commonly 110 volts, which
makes Vp = 2 (110) = 155.6 volts. The radial frequency of this input energy is ω = 2π(60 Hz)
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= 377.0 radians -per- second. In many cases, a transformer is utilized to step down the power
line voltage to a peak amplitude that is more suitable for the application at hand. The AC/DC
converter, or rectifier, which is activated either by the line voltage or by its transformed counterpart, can be as simple as a single diode or as complicated as either a four-diode bridge network
or a two-diode circuit utilizing a center-tapped transformer. The purpose of the lowpass filter,
which often is merely a suitably large capacitance placed in shunt with the load imposed on the
supply, is to attenuate, as sharply as possible, the amplitudes at the fundamental frequency and
the harmonic components of the output response generated by the rectifier. The voltage regulator, which may or may not be present in a particular version of a power supply, ideally renders
the ultimately achieved static, or “DC,” output voltage, VDC, independent of the static load current, IDC, drawn by the load that is driven by the power supply. The regulator, which is not addressed analytically in this chapter, can also be deployed to stabilize voltage VDC against variations in the input peak voltage, Vp, changes in system operating temperature, and even electrical
noise that may be coupled parasitically to critical nodes of the supply system. Finally, the load,
RL, can be taken as purely resistive. Despite its circuit level depiction in Figure (2.35), it is
rarely a physical two-terminal resistance. Instead, it is properly viewed as an effective load
resistance representing the ratio of DC output voltage to DC output current; that is, RL =VDC/IDC.
While the load at the output port of the power supply commonly shares system ground, the input
voltage, vs(t), may or may not be grounded.
Rs
+
vs(t)
AC/DC
Converter
(Rectifier)
Lowpass
Filter
Voltage
Regulator
IDC
VDC
RL
−
Figure (2.35). System level abstraction of a power supply appropriate for non-portable,
commercial electronic systems. Resistance RL is not a physical element. It
is used in the diagram merely to convey the fact that the power supply provides a static output voltage of VDC at a static output current of IDC.
2.5.3.1. Half Wave Rectifier
As stated in the preceding section, the rectifier functions in Figure (2.35) to convert the
alternating input sinusoid, vs(t), which has zero average value, to a unidirectional waveform
featuring nonzero average value. The simplest form of AC/DC converter is the half wave rectifier, which utilizes but a single PN junction diode, as shown in Figure (2.36a). The diode in this
circuit behaves effectively as a switch that is closed, or conductive, for sufficiently positive vs(t)
and is open circuited, or non-conductive whenever vs(t) is smaller than the turn on voltage, Von,
of the utilized diode. As a result, the effective load, which is delineated as resistance RLeff in the
subject diagram, witnesses only a positive voltage, vo(t), for all time. The diode is seen as
removing one-half of the input signal, and in particular, it banishes the one-half of the input
waveform per period for which vs(t) < Von, leaving only a half sinusoid per period that is delivered to the load. Figure (2.37) displays this half wave rectified sinusoid.
For vs(t) < Von, no diode current flows and the pertinent circuit model becomes the
structure in Figure (2.36b), which obviously yields an output voltage, vo(t), of zero. Note in this
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Vd
−
Id = 0
+ Vd −
vo(t)
Rs
vo(t)
Rs
RLeff
+
vs(t)
rdo
+
vo(t)
Rs
RLeff
+
vs(t)
−
Id
−
Id +
Von
model that the diode voltage, Vd, is identical to the source voltage, vs(t). Since vs(t) becomes as
negative as −Vp, this observation confirms that the utilized diode must be capable of withstanding a reverse bias of at least Vp. Common engineering practice in the design and implementation
of a half wave rectifier is to use a diode whose Zener breakdown rating is at least twice the peak
source voltage.
RLeff
+
vs(t)
−
−
(a).
(c).
(b).
Figure (2.36). (a). Schematic diagram of a half wave rectifier. (b). Equivalent circuit of the half wave
rectifier for the case of vs(t) < Von. (c). Equivalent circuit of the rectifier for vs(t) ≥ Von.
60
v s (t)
50
v o (t)
40
Voltage (volts)
30
20
10
0
-10
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
-20
-30
-40
-50
-60
Normalized Time, ωt/ π
Figure (2.37). Input and output voltage waveforms for the half wave rectifier in Figure (2.36). The
peak amplitude, Vp, of the input voltage is taken as 50 volts, the diode turn on voltage, Von, is 700 mV, and the voltage attenuation factor, ke, is taken to be 0.75.
If a silicon diode is used in the rectifier, a reasonable educated guess as to the value of
Von is 700 mV. Otherwise, Von can be approximated in accordance with the analyses and discourse surrounding the diode model postulated in Figure (2.5). In particular, the maximum diode
current, Idm, in light of (2-128) can be estimated as
Vp
(2-129)
I dm ≈
,
Rs + RLeff
whence by (2-3), the corresponding maximum diode voltage, Vdm, is
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⎡
Vp
⎛I ⎞
Vdm ≈ nVT ln ⎜ dm ⎟ = nVT ln ⎢
⎢⎣ I o Rs + RLeff
⎝ Io ⎠
(
)
J. Choma
⎤
⎥.
⎥⎦
(2-130)
It follows from (2-8) that
⎧ ⎡
Vp
⎪
Von ≈ Vdm − nVT = nVT ⎨ln ⎢
⎪⎩ ⎢⎣ I o Rs + RLeff
where ε is the base of natural logarithms.
(
)
⎫
⎤
⎡
Vp
⎪
⎥ − 1⎬ = nVT ln ⎢
⎥⎦
⎢⎣ εI o Rs + RLeff
⎪⎭
(
)
⎤
⎥ , (2-131)
⎥⎦
With vs(t) ≥ Von, the diode is conductive, and a plausible diode model is the architecture
provided in Figure (2.5b). However, since the diode is turned off for approximately 50% of the
time, a more meaningful diode model derives from an expansion of the diode volt-ampere
characteristic about the turn on voltage, as opposed to expanding said curve at the maximum current point, which is the scenario reflected by Figure (2.5b). Accordingly, Vdm in the subject
model is supplanted by voltage Von, which renders current Idm (current corresponding to voltage
Vdm) in the subject model zero. Moreover, the diode resistance, say rdo, is now the inverse of the
slope of the diode characteristic curve at Vd = Von. By (2-5) and (2-131),
nVT
nVT
Rs + RLeff .
=
(2-132)
rdo =
Von nVT
Vp
Io e
(
)
The resultant circuit model of the rectifier for vs(t) ≥ Von, which is offered in Figure (2.36c), predicts
(2-133)
vo (t) = ke [ vs (t) − Von ] ,
where
RLeff
ke =
(2-134)
RLeff + rdo + Rs
is the pertinent voltage attenuation factor. In summary,
0, for vs (t) < Von
(2-135)
vo (t) =
.
ke [ vs (t) − Von ] = ke ⎡⎣V p sin ( ωt ) − Von ⎤⎦ , for vs (t) ≥ Von
This relationship, along with the input waveform are the plots delineated in Figure (2.37).
It is worth interjecting, at risk of offending the multitude of analytical purists who
abound, that the foregoing disclosures in regard to Von and rdo are likely to comprise insignificant
engineering sidebars. In particular, most applications feature Vp >> Von, as well as nVT << Vp,
which collectively imply that the turn on voltage, Von, as well as its corresponding diode turn on
resistance, rdo, can almost invariably be ignored tacitly. In light of these reasonable approximations, the average value, VDC, of the output voltage plotted in Figure (2.37) is
1
VDC =
2π
≈
2π
∫
0
π
π
1
vo (t)d ( ωt ) ≡
vo (t)d ( ωt )
2π
∫
0
1
keV p sin ( ωt ) d ( ωt ) =
2π
∫
0
(2-136)
keV p
π
,
whose numerical value is about 32% of the amplitude of the observed output response. The
background applause recognizes that the rectifier at hand has succeeded in converting an input
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voltage waveform having no average value to a unidirectional response that features a nonzero
average value.
2.5.3.2. Full Wave Rectification
An obvious shortfall of the half wave rectifier is that one-half of the input voltage
waveform is effectively thrown away in the process of achieving the desired AC to DC conversion. The full wave rectifier, an example of which is presented in Figure (2.38), mitigates this
operational dilemma by effectively coalescing two half wave rectifiers. For any reasonable line
voltage input, vline(t), the center-tapped transformer produces a voltage, vs(t), which is a linear
function of vline(t), across each secondary winding, as indicated in the figure. The root mean
square value of the secondary voltage produced for a given line voltage is determined by the socalled turns ratio, N of the transformer[5]. In particular, N > 1, which corresponds to a step
down transformer, establishes vs(t) < vline(t), while the step up version associated with N < 1
delivers vs(t) > vline(t).
Id1 +
Rline
+
vline(t)
+
+
−
D1
vs(t)
−
+
Nvs(t)
−
Vd1
vo(t)
vs(t)
−
−
RLeff
D2
Id2 +
Vd2
−
Figure (2.38). Schematic diagram of a full wave rectifier that utilizes a center
tapped transformer.
A mere inspection of the circuit in Figure (2.38) suggests that when vline(t) is sufficiently positive to enable vs(t) > Von, diode D1 conducts current, but diode D2 is reverse biased.
Because diode D2 is reverse biased, the current conducted by D1 necessarily flows through the
effective load resistance, RLeff. On the other hand, negative vline(t) turns off diode D1 and encourages diode D2 to conduct. Once again, the diode current is forced to ground through the load
resistance. In effect, the section of the circuit connected to the upper part of the center-tapped
secondary processes positive vs(t), while its brethren on the bottom part of the circuit exclusively
handles negative vs(t).
The voltage response, vo(t), of the circuit topology at hand is the full wave rectified
sinusoid displayed in Figure (2.39). Because the full wave sinusoid encloses twice the area per
period than does its half wave counterpart, the average value of voltage delivered to the load is
twice that predicted by (2-136). Specifically,
1
VDC =
2π
2π
∫
0
π
2keV p
2
,
vo (t)d ( ωt ) ≡
vo (t)d ( ωt ) =
2π
π
∫
(2-137)
0
where, in the interest of comparative consistency, the Thévenin resistance, Rline, of the line voltage and the transformer turns ratio, N, are presumed to deliver an effective Thévenin resistance
associated with vs(t) on each secondary winding that is identical to the resistance, Rs, adopted in
the half wave rectifier.
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60
v s (t)
50
v o (t)
40
Voltage (volts)
30
20
10
0
-10
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
-20
-30
-40
-50
-60
Normalized Time, ωt/ π
Figure (2.39). Center tapped input and output voltage waveforms for the full wave rectifier in Figure
(2.38). The peak amplitude, Vp, of the input voltage is taken as 50 volts, the diode turn
on voltage, Von, is 700 mV, and the voltage attenuation factor, ke, is taken to be 0.75.
Several prices are paid for the increased conversion efficiency afforded by full wave
rectification. First, a center-tapped transformer, which is bulky, heavy, and somewhat expensive,
is required. Second, the two diodes in the circuit must be electrically matched to ensure that the
circuit dynamics indigenous to the upper part of the transformer secondary are identical to those
of the bottom part topology. Finally, the matched diodes must be capable of withstanding twice
the peak voltage generated at each secondary port with respect to ground. To wit, with diode D1
conducting, which implies diode D2 is turned off, the diode voltage, Vd2, forged across D2 is
[−2vs(t) + Von], where Von is the nominal forward biasing voltage of D1. Recalling (2-128), the
maximum value of vs(t) is VP, and assuming that 2VP >> Von, Vd2 rises to very nearly −2Vp.
Rline
d3
+
V
D
1
vo(t)
Id
−
−
d4
D
RLeff
Id
4
D2
4
2
+
V
−
vs(t)
V d2 −
+
−
−
D
Nvs(t)
+
3
vline(t)
+
Id
+
1
V d1 −
+
3
Id
Figure (2.40). Schematic diagram of a full wave bridge rectifier that does not require a center
tapped transformer.
An alternative full wave rectifier that does not require the use of a center-tapped transformer is the bridge topology in Figure (2.40). With vs(t) sufficiently positive, only diodes D1
and D2 conduct so that the current generated by the signal source at the transformer secondary
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flows trough diode D1, to ground through the effective load resistance, from ground and through
diode D2, and thence returned to the transformer secondary. On the other hand, negative vs(t)
negative forces only diodes D3 and D4 to conduct. In this circumstance, the current supplied by
the transformer secondary winding flows through diode D4, to ground through RLeff, from ground
and through diode D3, and ultimately back to the transformer secondary.
In addition to boasting the advantage of not requiring a center-tapped transformer, the
maximum voltage that any diode must be capable of withstanding in reverse bias in the bridge
topology can be demonstrated to be only −Vp. In effect, the breakdown of twice voltage amplitude that is common to conventional full wave rectifiers is shared in the bridge circuit by two diodes. Of course, all four diodes must be matched. An issue of potential concern, especially if
the voltage signal, vs(t), earmarked for rectification is characterized by small peak amplitude, is
that the effective turn on voltage for either pair of diodes is 2Von since two diodes are embedded
in the signal path driven by the transformer secondary.
2.5.3.3. Filter
Although the rectifiers introduced in the preceding subsection succeed in transforming
an alternating time domain excitation into a unidirectional response, they do not deliver the constant, or static, output voltages that are prerequisite to successfully biasing an electronic network.
Indeed, the rectifiers produce only a harmonically rich, and therefore distorted, version of the
line input sinusoid. Since the frequency domain content of a purely constant voltage is made up
of only a zero frequency component, it can be argued that the fundamental purpose of the filter in
a power supply is to annihilate these harmonic components, as well as the fundamental frequency component, of the waveform generated by the rectifier. It follows that the requisite filter
must be lowpass in nature and must exude a time constant that is significantly larger than the inverse of the fundamental frequency (usually 60 Hz) of the line voltage.
The simplest, and likely the most commonly used, power supply filter is little more
than a capacitance, say CL, placed in shunt with the effective load resistance. This filter is illustrated schematically in Figure (2.41a) in conjunction with the unfiltered half wave rectifier of
Figure (2.36a). The effectiveness of the appended load capacitance can be argued in terms of the
ability of a sufficiently large CL to short circuit to ground the fundamental and all higher
frequency harmonics of the voltage waveform to which it is exposed. Alternatively, its short
circuiting of voltages changing over time can be viewed as its ability to sustain over time the
voltage to which it is charged by the applied signal. In Figure (2.41a), resistance RLeff is the ratio
of the DC voltage, VDC, which is presumably the voltage to which CL charges, to the DC current,
IDC, supplied to the output port. In the absence of a regulator, RLeff is identical to the resistance,
RL, in the system level diagram of Figure (2.35). With the regulator present, RLeff is the input
resistance of said regulator.
Recall that when vs(t) ≥ Von, the diode in the rectifier conducts to deliver its current to
the effective load. This current delivery generates a nonzero output voltage, vo(t), which charges
the capacitance, CL, which shunts the load. From (2-135), the maximum output voltage in the
steady state, and thus the maximum voltage, say Vomax, to which capacitance CL charges is
Vomax = ke V p − Von ,
(2-138)
(
)
where Vp is recalled as the amplitude of the applied sinusoidal voltage, Von is the turn on voltage
of the diode, and ke is the circuit attenuation factor defined by (2-134). Although a nonzero time
delay between vs(t) and its response, vo(t), is unavoidable when the diode conducts, a small
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Vd
−
Id
vo(t)
Rs
rdo
+
−
Id +
Von
Thévenin source resistance, Rs, and a very small diode resistance, rdo, minimizes this delay,
which is given by the circuit time constant,
vo(t)
Rs
RLeff
+
CL
vs(t)
RLeff
+
+
C
− L
vs(t)
−
−
(a).
(b).
Id = 0
+ Vd −
vo(t)
Rs
RLeff
+
+
C
− L
vs(t)
−
(c).
Figure (2.41). (a). Schematic diagram of a half wave rectifier with capacitive lowpass filter. (b).
Equivalent circuit of the half wave rectifier for the case of vs(t) ≥ Von. In this time
interval, the filter capacitor, CL, charges to a maximum voltage of Vomax = keVp. (c).
Equivalent circuit of the rectifier for vs(t) ≥ Von. In this interval of time, the filter
capacitor discharges through effective load resistance RLeff from its maximum voltage
of Vomax to a designable minimum voltage, Vomin.
τon = ⎡⎣ RLeff ( rdo + Rs )⎤⎦ CL .
(2-139)
Consequently, the capacitor charges periodically in the steady state to its peak value, Vomax, at
nearly the same times at which vs(t) attains its maximum value. It is worthwhile interjecting,
however, that if time constant τon is a large number, the incurred delay between input line signal
and output voltage response lengthens the time required to achieve steady state operation. In
such an event, the achievement of steady state conditions may require that the subject circuit
process several cycles of the input line voltage. This long “wakeup” time does not necessarily
comprise a bad operating scene, for modern, high performance electronic systems are likely to be
vulnerable to voltage overstress problems precipitated by abruptly applied power supply voltages.
As time progresses in the steady state beyond the instant at which vo(t) attains its maximum value, vs(t), and hence the unfiltered, half wave rectified version of vo(t), decreases owing
to the sine wave signature of vs(t). But the load capacitor, which is unable to change its terminal
voltage instantaneously, temporarily retains its maximum voltage value of Vomax. Therefore, vo(t)
is now greater than vs(t) in Figure (2.41a), the diode is resultantly forced to cease conduction, and
Figure (2.41c) is rendered as the applicable equivalent circuit. Clearly, and in light of the fact
that capacitance CL is charged to voltage Vomax at the instant at which the diode cuts off, this
model yields
vo (t) = Vomax e
− t RLeff CL
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;
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that is, capacitance CL discharges through the effective load resistance, RLeff. The result at hand
remains valid as long as the diode does not conduct. But slightly less than one period of the input waveform later and specifically, at a time Tp subsequent to the realization of maximal output
voltage, vs(t) cycles through zero and ultimately matches the voltage value of the continuously
decaying vo(t). If time t = 0 is defined to correspond to the peak value of vs(t), which is tantamount to a shift of π/2 radians in the argument, ωt, of the input sinusoid, time Tp is such that
(
)
−T
R
C
(2-141)
Vomax cos ωT p = Vomax e p Leff L Vomin ,
where Vomin is the minimum value to which the voltage across the shunt load capacitance converges when the diode turns off. At t = Tp, the diode once again enters its conduction regime,
and the output voltage follows its unfiltered form until the maximum level of Vomax is once again
achieved. At the time when vo(t) rises to Vomax, the entire process described above is repeated.
Figure (2.42) captures the salient features of the foregoing discoveries.
Filtered
Output
Line
Voltage
V omax
V omin
Voltage
∆t
Unfiltered
Output
t = Tp
t=0
Time
Figure (2.42). Projected steady state response of the filtered half wave rectifier given in Figure (2.41a).
The filtered output plotted herewith is the output voltage, vo(t), in Figure (2.41a).
When compared to the unfiltered response shown in Figure (2.37), Figure (2.42) shows
that the load capacitor vastly improves the overall character of the output voltage response of the
power supply. But while the use of a load capacitor appears to be prudent engineering recourse,
the response remains imperfect in that the observed output voltage is not the strict constant that is
ideally associated with a static power supply. The problem, of course, is the capacitive discharge
through the effective load resistance. Since this effective load is the ratio of static output voltage
to static output current, the foregoing imperfections are exacerbated when the power supply of
interest is called upon to supply relatively large load currents at small output voltages.
The ripple factor, γ, (generally expressed as a percentage metric) quantifies the extent
to which an actual power supply deviates from the idealized norm of a unit capable of supplying
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a strictly constant static voltage to virtually any arbitrary load. The ripple factor is defined in
terms of the ripple voltage, Vr, which is
Vr Vomax − Vomin ≈ VDC − Vomin ,
(2-142)
where Vomax is equated to VDC because a negligible amount of capacitive discharge (and ideally
zero discharge) establishes Vomax as the constant, steady state output voltage, which should approach the design goal of VDC. The ripple factor compares the foregoing ripple voltage to the
maximum output voltage in accordance with
V
Vr
−T R
C
= 1 − omin = 1 − e p Leff L ,
γ (2-143)
Vomax
Vomax
where (2-141) is invoked. Since a fundamental objective in the design of the power supply is a
minimization of the amount of capacitive discharge, Tp << RLeffCL is a reasonable design
presumption, whence
Tp
Vr
−T R
C
(2-144)
γ .
= 1 − e p Leff L ≈
Vomax
RLeff C L
An analytical disclosure of the time, Tp, required in the preceding relationship can be
marshaled through an iterative solution of (2-41). Rather than enduring this grief, note via an
inspection of Figure (2.42) that Tp is necessarily only slightly smaller, by a specific amount of Δt,
than the period, 2π/ω = 1/f of the unfiltered output response. Time parameter Tp actually approaches period T = 1/f if the capacitance discharges only slightly. It follows that
Tp
Vr
1
−T R
C
(2-145)
γ = 1 − e p Leff L ≈
≈
,
Vomax
RLeff C L
f RLeff CL
where f symbolizes the frequency (in units of hertz) of the unfiltered response. It should be
understood that in the case of half wave rectification, the frequency, f, of the unfiltered response
is identical to the frequency of the applied line voltage. But in a full wave rectifier, which effectively functions as dual half wave rectifiers, frequency f in (2-145) is twice the frequency of the
line voltage. As might have been anticipated, (2-145) confirms that larger shunt load
capacitances engender progressively smaller power supply ripple factor. In addition, the ripple
factor of a full wave rectified power supply is one-half that of a half wave system, assuming the
time constant, RLeffCL, is the same in both considered units.
The foregoing observations seemingly infer that the key to successful power supply design is simply a big enough shunt output capacitance. But before jumping on the capacitance
bandwagon, the reader needs to be advised that large capacitances in power supply units, which
generally approach hundreds, if not thousands, of microfarads, are bulky, relatively expensive,
and generally unreliable in the long term. Moreover, the fact that the load capacitance acts as a
short circuit at the instants of time when the diode in the circuit switches to its conductive state
suggests the possibility of dangerously large diode currents.
An investigation of potential diode current problems begins with the observation that
for −Δt ≤ t ≤ 0 in Figure (2.42), the filtered output response, vo(t), is
(2-146)
vo ( t ) = Vomax cos ( ωt ) ,
while specifically,
2
⎡
ωΔt ) ⎤
(
⎥,
vo ( − Δt) ≡ Vomin = Vomax cos ( −ωΔt ) ≈ Vomax ⎢1 −
(2-147)
2 ⎥
⎢⎣
⎦
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where the indicated approximation exploits the presumption of a sufficiently small time increment, Δt. Thus, the ripple voltage, Vr, in (2-142) becomes
⎡ ( ωΔt ) 2 ⎤
⎥.
Vr Vomax − Vomin ≈ Vomax ⎢
(2-148)
⎢⎣ 2 ⎥⎦
This expression and (2-143) combine to deliver
(2-149)
ωΔt ≈ 2γ ,
which confirms the expected fact that time interval Δt diminishes with progressively decreasing
ripple factor. A sidebar to the last conclusion is that the solution to time Tp in (2-141) can now
be deduced in that Tp, as delineated in Figure (2.42), is clearly T − Δt, where T = 1/f is the period
of the unfiltered response. It can be shown that this observation synergizes with (2-149) to stipulate
2π − 2γ
(2-150)
Tp ≈
.
ω
Note in this approximate result that parameter Tp approaches 2π/ω, the period of the unfiltered
response for very small ripple factor, which is hardly worth writing home about in light of earlier
observations.
Returning to the circuit in Figure (2.41a), the current, Id, flowing through the diode
necessarily satisfies the Kirchhoff constraint,
v (t)
d v (t)
+ CL o .
Id = o
(2-151)
RLeff
dt
At time t = −Δt, when the diode returns from its off state to initiate current conduction, vo(t) =
Vomin = (1 − γ)Vomax, where (2-143) is exploited. On the other hand, (2-146) shows that
d vo (t)
= − ωVomax sin ( ωt ) ,
(2-152)
dt
whence at t = −Δt,
d v (t)
= − ωCLVomax sin ( −ωΔt ) = ωCLVomax sin ( ωΔt ) .
(2-153)
CL o
dt t =− Δt
For small Δt, sin(ωΔt) ≈ ωΔt and thus,
d v (t)
= ωCLVomax sin ( ωΔt ) ≈ ωCLVomax ( ωΔt ) = ωCLVomax 2γ , (2-154)
CL o
dt t =− Δt
where (2-149) is used. It follows that the diode current at time t = −Δt is
V
I d t =− Δt = omin + ωCLVomax 2γ ,
RLeff
(2-155)
Factoring out Vomax/RLeff and recognizing that this voltage to resistance ratio is the desired static
current, IDC, supplied to the effective load, (2-155) becomes
I d t =− Δt = I DC 1 − γ + ωRLeff CL 2γ .
(2-156)
(
)
Appealing to (2-145) and noting that ripple factor γ is invariably far smaller than unity in a high
performance power supply, the last result collapses to
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⎛
8π 2 ⎞⎟
= I dpeak ,
I d t =− Δt ≈ I DC ⎜ 1 +
(2-157)
γ ⎟
⎜
⎝
⎠
where the symbol, Idpeak, simplifies the peak diode current notation. This revealing disclosure
contends that the diode current can peak to levels that lie appreciably above its steady state static
value of IDC if the power supply under consideration is designed for very small ripple. For example, the peak diode current is theoretically almost 64-times larger than the DC output current if a
2% ripple factor is implemented! Fortunately, this current extreme, which occurs periodically
with a period equal to that of the unfiltered, rectified response, is sustained for only the small
time increment, Δt. In particular, at a time, Δt, after the diode begins to conduct and peak diode
current is realized, the output voltage rises to its maximum level and the diode is necessarily
turned off. A short duty cycle notwithstanding, the peak diode current must be weighed carefully in the selection of diodes suitable for use in a filtered supply.
One way of mitigating the effects of harsh diode current transients entails the use of an
inductance placed in series with the diode. The inductance proves effective because of its inherent inability to support instantaneous changes in currents that it conducts. The reader is invited
to explore the utility of a series inductor in Problem #2.26.
EXAMPLE #2.6:
Design a full wave rectified power supply capable of supply a static voltage of nominally 9 volts to a load that draws 25 mA of current. Use a
capacitive filter to achieve a load voltage ripple factor of at most 2.5%.
Assume that the frequency of the applied line voltage is 60 Hz and that its
root mean square amplitude is 110 volts. Examine the time domain
performance of the power supply with SPICE simulation software. To this
end, model parameters of the silicon PN junction diode deemed suitable
for this design initiative are itemized in Table (2.1).
SPICE
TEXT
SYMBOL SYMBOL
IS
Io
RS
N
CJO
VJ
M
TT
n
Cjo
Vj
mj
τd
DESCRIPTION
OF PARAMETER
Saturation Current
Net Ohmic Resistance
Injection Coefficient
Zero Bias Depletion Capacitance
Junction Built-In Potential
Grading Coefficient
Average Carrier Transit Time
VALUE UNITS
45
0.2
1.03
353.6
800
0.5
10
fA
Ω
–
fF
mV
–
nSEC
Table (2.1). SPICE model parameters for the diodes used in the full wave rectifier studied in Example #2.5.
SOLUTION #2.6:
(1).
The effective load resistance imposed on the target power supply is the ratio of the
static output voltage to the corresponding output current. In particular,
V
9
(E6-1)
RLeff = DC =
= 360 Ω .
I DC
0.025
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(2).
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Equation (2-145) defines the ripple factor, γ, for a half wave rectifier. If frequency f
in this relationship is replaced by (2f), the expression at hand can be applied to a full
wave rectifier. Thus, the shunt load capacitance, CL, must satisfy
1
1
CL =
≥
= 925.9 μF .
(E6-2)
(2f )γRLeff
(120)(0.025)(360)
It is entirely appropriate to round up this computed capacitance value to 930 μF or to
whatever value is available commercially at a reasonable price. For the purpose of
this problem, take CL = 930 μF.
(3).
A center-tapped transformer is obviously required. The peak voltages at either secondary tap must be sufficiently large to embrace the desired 9 volt static output, the turn
on voltage of each diode, the resistance, say Rs, associated with each center-tapped
output port, and the ostensibly small losses precipitated by the net series ohmic resistances of the diodes. Assuming a 720 mV turn on voltage and Rs = 5 Ω (which drops
about 0.125 volt for a steady state current delivery of 25 mA, the requisite peak center
tap voltage is slightly greater than 9.8 volts. Because of the uncertainty in the effective resistance of each diode, 10.5 volts is chosen for this design. Recalling Figure
(2.38), the turns ratio, N, to each center-tapped transformer port follows as
110 2
(E6-3)
N =
= 14.82 .
10.5
Although SPICE models of practical center-tapped transformers are commonly available, it is not the intent of this chapter to study the dynamic properties and electrical
nuances of transformers. Hence, the circuit designed herewith and overviewed
schematically in Figure (2.43) simply represents the center-tapped output port
voltages of the transformer by two independent sinusoids possessed of a 10.5 volt
amplitude and 60 Hz frequency.
Vd1
5
Id1 +
−
+
D1
10.5 sin(377t)
−
+
vo(t)
10.5 sin(377t)
360
−
D2
5
Id2 +
Vd2
+
930
−
−
Figure (2.43). Schematic diagram of the power supply designed in Example #2.5.
Signal amplitudes are in volts, the signal frequencies are 60 Hz or
equivalently, 377 radians per second, the resistances are in units of
ohms, and the capacitor is in units of microfarads.
(4).
With IDC = 25 mA and γ ≈ 0.025 in (2-157), the estimated peak diode current computes as
⎛
8π 2 ⎞⎟
(E6-4)
= 57.2I DC = 1.43 amps .
I dpeak ≈ I DC ⎜ 1 +
γ ⎟
⎜
⎝
⎠
While it is arguably sensible to ensure that the utilized diodes can safely withstand
this significant peak current stress, it should be noted that in practice, the inductances
associated with the windings of the transformer embedded in the power supply miti-
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gate this current peak, possibly by as much as a factor of two or more. Moreover, the
energy storage parasitics (junction capacitance and carrier transit time) tend to soften
the transient diode current incurred at those instants of times when the diode enters its
conduction state.
10
Voltage (volts)
8
6
4
2
0
0
10
20
30
40
50
60
70
80
Time (mSEC)
Figure (2.44). Simulated output voltage response, vo(t), of the power supply circuit shown in Figure
(2.43). The solid curve corresponds to the actual filtered response, while the dashed
curve, which mirrors full wave rectification of a sinusoid, is the response with the
load capacitance, CL, removed.
COMMENTS: The simulated voltage response of the power supply considered herewith
is offered in Figure (2.44). The simulated curves in the figure not only depict the desired filtered voltage response, but the unfiltered, or full wave
rectified output, as well. Observe that the filtered output does not track
particularly well with the first few periods of the applied signal waveform
and that indeed, several periods are required before an apparent steady
state is realized. This deviation from the response results projected in Figure (2.42) reflects the delay phenomenon noted earlier and precipitated by
a very large time constant associated with the load capacitance during diode conduction times. Because of this delay, observe further that the load
capacitance does not discharge at the peak of the unfiltered response but
instead, it begins its periodic discharge at roughly a diode turn on voltage
below the aforementioned peak amplitude. An assiduous examination of
the numerical simulation data reveals that the maximum steady state output voltage is 9.012 volts, and the minimum output value is 8.818 volts.
Hence, the simulated ripple factor is 2.15%, which is slightly better than
the design target of 2.5%. The slight improvement in ripple performance
can large be attributed to rounding up of the computed capacitance value.
The simulated diode current responses appear in Figure (2.45). The largest peak diode current is realized at startup, which is reasonable in view of
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the fact that the capacitor is initially uncharged. The peak current is 1.26
amperes, which is about 12% smaller than the peak current value projected in (E6-4).
1.5
Diode D1
Current, Id1
Diode Current (amps)
1.2
0.9
Diode D2
Current, Id2
0.6
0.3
0
0
10
20
30
40
50
60
70
80
90
100
Time (mSEC)
Figure (2.45). Simulated diode current responses of the power supply circuit shown in Figure (2.43).
The SPICE model parameters for the utilized diodes are tabulated in Table (2.1).
2.5.4. DIODE APPLICATIONS FOR LOW LEVEL SIGNALS
PN junction diodes used in the half wave rectifier and the full wave rectifier addressed
in the preceding subsection are utilitarian as long as the amplitude of the periodic voltage signal
earmarked for rectification is larger than the threshold potentials of the utilized diodes. The
bridge topology, in which two series connected and matched diode pairs are embedded, exacerbates the situation in that its input signal amplitude must exceed twice the turn on voltage of each
diode. As has been established, silicon diodes exude turn on potentials of the order of 700 mV,
which means that the rectifiers considered to this point are ineffective when applied signal amplitudes are smaller than about 700 mV. Unfortunately, this situation comprises a serious drawback
in instrumentation systems and in other precision networks that often operate on signals featuring
amplitudes in the range of tens of microvolts to a few millivolts. The relatively large threshold
potential of diodes is also a significant shortfall in electronic networks that exploit adaptive biasing to minimize power dissipation. In the latter application, the biasing of radio frequency (RF)
subcircuits is adjusted in proportion to the amplitude of the input signal detected for signal
processing. Thus, small standby power prevails in these adaptive amplifiers when the input signals are very small, while appropriately larger quiescent power is dissipated to enable the nominally linear signal processing of comparably large input signals. But the effectiveness of such an
adaptive configuration rests squarely on the ability to detect reliably input signals whose amplitudes are far below diode threshold potentials.
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2.5.4.1. Precision Half Wave Rectifier
Figure (2.46) depicts the basic schematic diagram of a precision half wave rectifier
formed of a PN junction diode and an operational amplifier. For simplicity, the requisite biasing
for the utilized op-amp is not shown but nonetheless, it is presumed that the op-amp functions
linearly when suitable negative feedback is applied around it. If diode D conducts a forward current, a low resistance feedback path is forged from the output port of the op-amp to its inverting
input port. Consequently, the voltage, v, observed differentially across the input terminals of the
op-amp, as shown in the diagram, is driven to nearly zero. Specifically, it is driven to voa(t)/Ao,
where voa(t) is the indicated output voltage of the op-amp, while Ao is the open loop voltage gain
of the op-amp. Now, the input voltage, vi(t), at the non-inverting op-amp input terminal is essentially the applied source signal vs(t), if the subject op-amp is characterized by large input resistance. It follows that
vo(t)
Rs
+
vs(t)
−
v
+
vi(t)
−
Op-Amp
+
D
voa(t)
Rl
−
Figure (2.46). Simplified schematic diagram of a precision half wave rectifier. Biasing for the op-amp is not shown, but it is assumed that the op-amp
operates linearly when appropriate feedback is applied around it.
voa (t)
+ vo (t) .
(2-158)
Ao
But if diode D is conducting current, which implies that its terminal voltage is in the immediate
neighborhood of the turn on potential, Von,
vo (t) ≈ voa (t) − Von ,
(2-159)
and in light of (2-158),
v (t)
vs (t) − oa
≈ voa (t) − Von .
(2-160)
Ao
This expression suggests that in order for voltage voa(t) to exceed Von, thereby assuring turn on of
diode D, it is necessary that the applied signal voltage, vs(t), be larger than only voa(t)/Ao. Since
voa(t) must rise to at least Von in order that diode D conduct, the last observation puts forth an
effective turn on voltage for the overall network of Von/Ao. This effective threshold voltage is
very small in that high quality op-amps routinely boast open loop voltage gains of at least 80 dB.
To wit, Von = 700 mV and Ao = 80 dB = 10,000 volts/volt yield an impressively low effective
turn on voltage of only 70 μV!
vs (t) ≈ vi (t) =
While the diode remains conductive, the output voltage response to an input signal larger than Von/Ao satisfies
v (t)
V + vo (t)
vo (t) = − oa + vi (t) ≈ vs (t) − on
,
(2-161)
Ao
Ao
or
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⎛ Ao ⎞
Von
(2-162)
vo (t) ≈ ⎜
.
⎟ vs (t) −
Ao + 1
⎝ Ao + 1 ⎠
As long as vs(t) > Von/Ao, the output response essentially follows the input signal with an offset
of Von/(Ao +1). When vs(t) falls below Von/Ao, diode D ceases conduction, which starves the load
resistance, Rl in Figure (2.46), of current. Neglecting leakage currents in both the diode and the
op-amp, the output response therefore falls to zero. This fact and (2-161) combine to couch the
circuit at hand as a precision half wave rectifier; that is, a half wave rectifier that functions as expected whenever the input signal voltage exceeds the generally very small effective threshold
voltage of Von/Ao.
Unfortunately, the rectifier at hand is vulnerable to turn off transients similar to those
assessed in Section 2.4.1.1 and illustrated in Figure (2.17c). These transients, which are somewhat mitigated by diodes boasting small junction depletion capacitances, limit the input signal
frequencies that can be processed faithfully. Further mitigation of undue diode turn off transients is afforded by signal sources that have small internal impedances.
2.5.4.2. Precision Limiter
A slight modification of the rectifier in Figure (2.46) produces the precision limiter depicted in Figure (2.47). As in the rectifier considered in the preceding subsection, the op-amp is
presumed to have a large open loop gain, Ao, and is further presumed to operate in its linear regime when diode D is conductive. Accordingly, voltage v in the schematic diagram is voa(t)/Ao
when negative feedback forged by nonzero diode current prevails. When the applied signal voltage, vs(t), is smaller than the static reference potential, VR, applied at the non-inverting input
terminal of the op-amp, the op-amp output voltage, voa(t) rises to facilitate current conduction in
diode D. In this event, the output voltage is
vo(t)
Rs
v−
+
+
vs(t)
−
+
−
Op-Amp
+
D
voa(t)
Rl
VR
−
Figure (2.47). Simplified schematic diagram of a precision limiter. Biasing for the
op-amp is not shown, but it is assumed that the op-amp operates
linearly when appropriate feedback is applied around it.
v (t)
vo (t) = − oa + VR ,
(2-163)
Ao
and since for a diode turn on voltage of Von,
voa (t) ≈ Von + vo (t) ,
(2-164)
(2-163) generates
⎛ Ao ⎞
Von
(2-165)
vo (t) ≈ ⎜
.
⎟VR −
A
+
1
A
+
1
o
⎝ o
⎠
For a large open loop voltage gain, Ao, (2-165) shows that the diode threshold potential negligibly impacts the output response, vo(t), which is essentially clamped to the reference potential, VR.
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Thus, vo(t) is limited to reference voltage VR, regardless of the amount by which the input signal,
vs(t), exceeds VR.
When vs(t) is greater than or equal to VR, the op-amp output port voltage, voa(t), is
driven negative, and the diode consequently shuts off. If the op-amp is characterized by large input resistance at either of its input ports, a series circuit is thereby established among vs(t), signal
source resistance Rs, and the load resistance, Rl. It follows that
⎛ Rl ⎞
(2-166)
vo (t) = ⎜
⎟ vs (t) ,
R
R
+
s⎠
⎝ l
and the output response is seen to track linearly with the input signal. In summary,
⎛ Ao ⎞
Von
≈ VR for vs (t) < VR
⎜
⎟VR −
Ao + 1
⎝ Ao + 1 ⎠
(2-167)
vo (t) ≈
.
⎛ Rl ⎞
⎜
⎟ vs (t) for vs (t) ≥ VR
R
R
+
s⎠
⎝ l
A potentially serious problem with the limiter in Figure (2.47) is manifested when diode D turns off, as it does for vs(t) ≥ VR. In this case, no feedback is applied around the op-amp,
with the result that said op-amp invariably saturates; that is, voa(t) locks to the negative supply
voltage used to bias the op-amp. This situation imposes a severe limitation to the processing
speed attainable by the circuit since a significant level of stored charge within the op-amp must
be removed to enable the return of the op-amp to its linear region when vs(t) < VR. In a word, the
op-amp is simply incapable of responding rapidly to input signals whose amplitudes change suddenly from a level above VR to a level below VR. Moreover, the magnitude of the differential
voltage across the input terminals of a saturated op-amp can become very large, thereby risking
breakdown of the amplifier unit. The problem at hand can be mitigated, but only through use of
appropriately connected transistors, which is subject matter reserved for subsequent chapters.
2.5.4.3. Precision Full Wave Rectifier
The precision full wave rectifier in Figure (2.48) requires two operational amplifiers
and two PN junction diodes. The two diodes must be matched and while the two op-amps need
not be identical, both must have large open loop voltage gains and large input impedances. As is
demonstrated by the forthcoming simplified analysis, the output response, vo(t), is
R
vo (t) ≈
vs (t) .
(2-168)
Rt
where resistance Rt includes the Thévenin resistance of the source voltage. Thus, if the signal,
vs(t), applied to the indicated network is a sinusoid, the output response is a full wave rectified
sinusoid with the added attribute of voltage gain in the amount of (R/Rt). By adjusting resistance
Rt, perhaps electronically, the gain can be controlled, which means that when a filter capacitor is
connected across the load resistance, the static output voltage can be adjusted electronically.
The full wave rectifier in Figure (2.48) is obviously more topologically complex than is
its half wave counterpart in Figure (2.46). It is hardly earth shattering to declare that enhanced
topological complexity breeds correspondingly increased analytical challenges. At the worthwhile risk of preaching to the reader, recall that the purpose of circuit analysis is not necessarily
the generation of precise network solutions. Rather, its fundamental purpose is to inspire the
engineering insights that beget design creativity. Accordingly, meaningful approximate analyses
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of complex networks comprise prudent undertakings in that they generally highlight the attributes and shortfalls of achievable I/O characteristics, albeit to crude first order. An effective
intellectual response to the purist who suffers heartburn with this schema is that a network
proven dysfunctional for approximate, and generally idealized, model and architectural circumstances can hardly be expected to satisfy design goals under “real world” conditions. In other
words, outstanding performance achieved under idealized conditions is a prerequisite to acceptable performance in an actual engineering environment.
R
R
R
D1
Rt
−
v1
+
−
Op-Amp
+1
voa(t)
D2
+
−
v2
+
−
Op-Amp
+2
vo(t)
Rl
vs(t)
−
R
Figure (2.48). Basic schematic diagram of a precision full wave rectifier. Biasing for the op-amps is
not shown, but it is assumed that these op-amps operate linearly when negative feedback is applied around them. While the diodes are presumed to be identical, the opamps need only present very large open gains and very large input impedances.
EXAMPLE #2.7:
As an illustration of the efficacy of an approximate analysis of a reasonably complex circuit topology, study the circuit in Figure (2.48), subject to
the idealized circumstances of (1) infinitely large open loop gain in both
op-amps and (2) infinitely large input impedances at both input ports of
each op-amp. In particular, deduce approximate results for the output
voltage, vo(t), for both positive and negative values of the input signal,
vs(t). Confirm the propriety of the analyses through appropriate SPICE
simulations of the network in question.
SOLUTION #2.7:
(1).
Since the input voltage, vs(t), is applied through a resistance, Rt, to the inverting input
terminal of the first op-amp, voltage voa(t) at the output port of op-amp 1is driven
negative. This output voltage swing turns on diode D1, while turning off diode D2.
Consequently, the pertinent equivalent circuit is the structure appearing in Figure
(2.49a), in which all known node voltages and branch currents are explicitly delineated. These electrical variables are deduced as follows
(a). With diode D1 conductive, negative feedback is established around op-amp 1. In
light of the infinitely large open loop gain assumption, voltage v1 across the input
terminals of this op-amp is zero. Negative feedback via resistance R is always applied around op-amp 2, which therefore affords v2 = 0.
(b). The infinite input impedance assumption applied to both op-amps implies that the
currents flowing into the inverting and non-inverting input terminals of each of
these units are zero.
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R
vs(t)/Rt
vs(t)/Rt
0
Rt
−
0
+
0
0
−vo(t)
R
J. Choma
vo(t)/R
Lecture Supplement #3
D1
−
Op-Amp
+1
−
0
+
voa(t)
R
0
0
0
vo(t)/R
−
vo(t)
Op-Amp
+2
Rl
+
0
vs(t)
−
R
vs(t)/Rt
Rt
0
−
0
+
0
0
−
Op-Amp
+1
[vo(t)−vx ]/R
voa(t)
D2
+
vs(t)
−
vx /R
R
R
R
vx
−
0
+
0
0
−
Op-Amp
+2
[vo(t)−vx ]/R
R
[vo(t)−vx ]/R
vs(t)/Rt + vx /R
(a).
vo(t)
Rl
vx
(b).
Figure (2.49). (a). Equivalent circuit of the rectifier in Figure (2.48) for the case of vs(t) < 0, which
turns on diode D1 and turns off diode D2. (b). Equivalent circuit of the rectifier in
Figure (2.48) for the case of vs(t) > 0, which turns off diode D1 and turns on diode D2.
(c). Since the non-inverting input port of the first op-amp is grounded and its differential input voltage is zero, the voltage with respect to ground at the inverting node
of op-amp 1 lies at zero. Accordingly, the current supplied to this node by the
signal source is vs(t)/Rt.
(d). Since no current is conducted by the resistance, R, which is incident with the noninverting input port of op-amp 2, the current, vs(t)/Rt, conducted by resistance Rt
flows through the resistance, R, which is incident with the inverting input terminal
of the op-amp 1 and the p-side of diode D1.
(e). The inverting input terminal of op-amp 1 is a virtual ground, no current flows
through the resistance, R, which is connected between said op-amp terminal and
the non-inverting input terminal of op-amp 2, and zero volts prevails across the
input terminals of op-amp 2. It follows that the inverting input terminal of opamp 2 is a virtual ground, thereby establishing a current, vo(t)/R, which flows in
the indicated direction through the feedback resistance, R, appended to the second
op-amp. Moreover, this same current is forced to flow through the resistance, R,
which intertwines the inverting input terminal of op-amp 2 with the p-side of diode D1.
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(f). The last current discussed above and the virtual ground at the inverting input node
of op-amp 2 forces a voltage of −vo(t) from the p-side of diode D1 to ground. By
KVL, it follows that −vo(t) = −R[vs(t)/Rt], whence for vs(t) > 0,
⎛R⎞
vo (t) = ⎜ ⎟ vs (t) .
(E7-1)
⎝ Rt ⎠
(2).
With vs(t) < 0, voltage voa(t) in Figure (2.48) rises, thereby effecting cutoff of diode
D1 and conduction of diode D2. The applicable equivalent circuit, with critical
branch currents and node voltages explicated, is the structure offered in Figure
(2.49b).
(a). With diode D1 turned off, negative feedback is nonetheless maintained around
op-amp 1 because of the upper resistances R and the lower resistance R. Voltage
v1 across the input terminals of this op-amp is zero, as is voltage v2. Of course,
the input ports of neither op-amp conduct any current.
(b). Since the inverting input port of op-amp 1 remains virtually grounded, the current
supplied to this node by the signal source is vs(t)/Rt.
(c). Temporarily assign a voltage, vx, at the inverting node of op-amp 2. Because zero
differential voltage prevails across the input ports of this second op-amp, the same
voltage is manifested at the n-side of diode D2.
(d). The last conclusion, coupled with the virtual ground at the inverting input port of
op-amp 1, gives rise to a current, vx/R, flowing through resistance R and toward
the aforementioned port. By KCL, a current of [vs(t)/Rt + vx/R] necessarily flows
through the resistance, R, which is incident with the inverting input terminal of
op-amp 1.
(e). In view of the temporarily assigned potential, vx, the current conducted by the
feedback resistance imposed around op-amp 2 is [vo(t) − vx]/R, as shown. Since
the input ports of op-amp 2 conduct no current, this same current flows from right
to left through the resistance, R, which appears topologically to the left of the
node at which voltage vx is established with respect to ground. An inspection of
the branch containing the series interconnection of the two resistances of value R
indicates that [vs(t)/Rt + vx/R] = −[vo(t) − vx]/R, which readily produces
⎛R⎞
vo (t) = − ⎜ ⎟ vs (t) .
(E7-2)
⎝ Rt ⎠
(3).
Obviously, (E7-2) and (E7-1) combine to validate (2-168).
(4).
In order to test the propriety of the foregoing disclosures, the precision rectifier of
Figure (2.48) is simulated on SPICE software with ideal operational amplifiers having
open loop gains of 10,000 volts/volt. The diodes have SPICE model parameters of IS
= 2 fA, RS = 0.20 uΩ, N = 1.02, CJO = 0.5 fF, VJ = 800 mV, M = 0.5, and TT = 1.0
fSEC, where the symbolic nomenclature is provided in Table (2.1). For the purpose
of this exercise, Rt is taken to be 50 Ω, R = 100 Ω (implying an I/O voltage gain of 2),
and Rl = 500 Ω. In addition, 100 KΩ resistances are appended between ground and
each op-amp input port to allow consideration of large, but finite op-amp input resistances.
(a). The first simulation is a static sweep of input signal vs(t) to determine the describing function that relates output voltage vo(t) to vs(t). The simulated results are displayed in Figure (2.50) over an input voltage range of −2 volts ≤ vs(t) ≤ +2 volts.
The projected dependence of the output voltage on the absolute value of the
source signal is clearly confirmed, as is the I/O voltage gain of R/Rt = 2 volts/volt.
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6
Output
Voltage, vo(t)
Voltage (volts)
4
2
0
Input
Voltage, vs(t)
-2
-2
-1
0
1
2
Voltage (volts)
Figure (2.50). Output voltage response, vo(t), of the precision rectifier in Figure (2.48) for a static
sweep of the applied input voltage, vs(t).
Output
Voltage, vs(t)
12
Voltage (volts)
8
4
0
-4
Input
Voltage, vs(t)
-8
0
3
6
9
12
15
Time (nSEC)
Figure (2.51). Output voltage response, vo(t), of the precision rectifier in Figure (2.48) for a 250
MHz, 5 mV, input sinusoid.
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(b). The second simulation is the transient time domain response of the rectifier output
voltage to an applied 250 MHz sinusoid having an amplitude of only 5 mV. The
pertinent results appear in Figure (2.51). Fundamentally, a full wave rectified
sine appears to be generated, although diode turn off transients manifest observable effects after the first full cycle of the input waveform. In concert with the diode turn off compensation strategy documented earlier, these effects can be partially mitigated by appending small capacitances (about 100 fF) across the two
resistances, R, which are incident with the inverting input terminal of op-amp 1.
COMMENTS: The approximate, and admittedly idealized, analysis of the subject circuit
tracks well with relevant SPICE simulations. As a result, the analysis
serves to confirm the validity of pertinent theoretic disclosures. More
importantly, the analysis establishes a sturdy foundation upon which
practical design modifications and refinements can be formulated. For
example, the capacitance compensation noted above tracks with
fundamental theory and indeed improves the observed response (refer to
Problem #2.33). Additional computer-based investigations can be conducted in advance of the actual realization of the required amplifiers in
MOSFET or bipolar device technologies. For example, the effects on
transient time domain responses of nonzero output resistances, nonzero
output capacitances and inductances, and nonzero input port capacitances
in both amplifiers can be assessed straightforwardly. The fruits of these
assessments can facilitate the choice of geometries of the active devices
deployed in the final form design, and they can prove useful for the selection of suitable device biasing levels.
2.6.0. REFERENCES
[1]. R. T. Howe and C. G. Sodini, Microelectronics: An Integrated Approach. Upper Saddle River,
New Jersey: Prentice Hall, 1997, pp. 88-106.
[2]. A. B. Phillips, Transistor Engineering and Introduction to Integrated Semiconductor Circuits.
New York: McGraw-Hill Book Company, Inc., 1962, pp. 133-139.
[3]. K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and Design. Reading,
Massachusetts: Addison-Wesley Publishing Company, 1978, pp. 107-113 and pp. 636-641.
[4]. M. Abramowitz and I. A. Stegun, Handbook of Mathematical Functions. Washington, D. C.:
National Bureau of Standards, Applied Mathematical Series No. 55, 1964, Section 9.6.
[5]. A. M. Davis, Linear Circuit Analysis. Boston, Massachusetts: PWS Publishing Company,
1998, chap. 16.
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EXERCISES
Problem #2.1
Assume a constant current conducted by a forward biased PN junction diode. Show that at
room temperature, the diode voltage commensurate with constant diode current must decrease by almost 60 mV for each one order of magnitude increase in the diode saturation
current, Io.
Problem #2.2
The two diodes in the circuit of Figure (P2.2) are identical. Current Ik is a constant current
sink. If the volt-ampere characteristics of each diode are approximated by
I d ≈ I oeVd nVT ,
derive expressions for the individual diode currents, Id1 and Id2, as a function of current Ik
and the difference voltage, (V1 − V2) Δ V. Argue the validity of these expressions for the
cases of V strongly positive and then voltage V strongly negative.
Id1 D1
D2
+
V1
Id2
+
Ik
−
−
V2
Figure (P2.2)
Problem #2.3
Repeat Problem #2.2 for the case in which the junction area of diode D2 is K-times larger
than that of diode D1.
Problem #2.4
In the circuit of Figure (P2.4), diode D2 has twice the junction injection area of diode D1.
When each diode conducts measurable current, each displays a nominally constant forward
operating voltage of Von; that is, the series resistance associated with each diode is negligibly small.
R1
R3
+Vcc
R2
D1
D2
Figure (P2.4)
(a). What condition must be satisfied by the power supply voltage, Vcc, if the two PN junction diodes are to conduct measurable forward current?
(b). If the condition in (a) is satisfied, give expressions, in terms of circuit parameters, for
the currents, Id1 and Id2, conducted by diodes D1 and D2 respectively?
(c). If both diodes are either silicon or germanium units, is it possible for only one of the
two diodes to conduct forward current?
(d). If one diode is a silicon semiconductor and the other is a germanium unit, is it possible
for only one of the two diodes to be conductive? If indeed possible, which diode (the
silicon or the germanium device) is actually conductive?
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Problem #2.5
The circuit in Figure (P2.5) is used to “square” a 10 KHz sinusoid (Vs) whose peak amplitude is 50 volts. The diodes in the circuit have forward resistances of 10 Ω, infinitely large
reverse resistances, and turn on voltages that are sufficiently small in comparison to the applied input signal to warrant their tacit neglect. The battery voltages, Vr1 and Vr2 are such
that |Vr2| > |Vr1|, but Vr2 and Vr1 are allowed to be of opposite algebraic signs. The output
voltage (Vo) waveform is to be flat for 90% of the time. Design the circuit by selecting Vr1,
Vr2, and a reasonable value for resistance R.
R
Vo
+
Vs
−
+
+
Vr1
Vr2
−
−
Figure (P2.5)
Problem #2.6
In the circuit of Figure (P2.6), diode D2 has 3-times the junction injection area of diode D1.
When each diode conducts measurable current, each displays a nominally constant forward
operating voltage of Von.
D1 Id1
R3
R1
D2
Id2
R2
−
Vdd
+
Figure (P2.6)
(a). What condition must be satisfied by the power supply voltage, Vdd, if each of the two
PN junction diodes are to conduct nonzero forward current? Express your result in
terms of Von and relevant circuit parameters.
(b). If the actual power supply used in the circuit provides a terminal voltage that is fivetimes the minimum voltage deduced in Part (a), give expressions, in terms of Von and
relevant circuit parameters, for the diode currents, Id1 and Id2.
Problem #2.7
Each of the diodes in the circuit of Figure (P2.7) has a threshold voltage of Von and a forward small signal terminal resistance (inverse slope of diode I-V curve) that can be taken to
be zero. Assume that input voltage Vs is a sinusoid whose amplitude, Vp, exceeds Von.
What is the maximally positive value of the current, IL, conducted by the parallel diode
configuration, and what is the maximally negative value of current IL?
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Lecture Supplement #3
PN Junction Diode
Rs
+
J. Choma
IL
Vs
D1
−
D2
Figure (P2.7)
Problem #2.8
Repeat Example #2.1 for the case in which diode D is operated at a junction temperature of
75 °C. Assume that D has a temperature factor of P = 3.5. Compare the diode voltage result obtained herewith with the diode voltage computed in the example and deduce the average temperature coefficient, ΔVd/ΔT, of the diode.
Problem #2.9
In the circuit of Figure (P2.9), the indicated voltages, V1, and V2, are constrained to be equal
by additional circuitry that is not shown in the diagram. Diodes D1 and D2 are identical,
save for the fact that their junction areas differ. All resistors can be presumed to have zero
temperature coefficients.
+Vdd
R
R
V1
V2
D2
D1
Id1
Id2
R1
R2
Figure (P2.9)
(a). What is the relationship between diode current Id1 and diode current Id2?
(b). Derive an expression for diode current Id1 in terms of the difference between the two
diode voltages.
(c). Which of the two diodes must have a larger junction injection area? Explain why.
(d). If the magnitude of the difference between the two diode voltages is to be nominally
500 mV, by what factor must one diode junction injection area exceed the injection
area of the other diode?
Problem #2.10
Derive equations (2-45) and (2-46).
Problem #2.11
Integrate equation (2-26) from a stipulated position, say Xi, to any arbitrary position, x. Let
position Xi be selected as the position where the observed free hole and free electron
concentrations lie at their intrinsic concentration values. Use the fruits of the foregoing
integration exercise to confirm that under equilibrium conditions, p(x)n(x) = ni2, where p(x),
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n(x), and ni respectively symbolize the free hole concentration at x, the free electron
concentration at x, and the intrinsic carrier concentration of the considered semiconductor.
Problem #2.12
A silicon PN junction diode is doped such that the doping concentration, ND, on the n-side
of the junction is much larger than the dopant level, NA, on the p-side of the junction; that is,
ND >> NA, as is typically the case in routine diode fabrication. Show that for this fabrication scenario, the equilibrium field intensity at the junction can be approximated as
2V j
E (0) ≈ −
,
Wo
where Vj is the equilibrium built-in potential of the junction and Wo is the equilibrium width
of the depletion layer.
Problem #2.13
When PN junction diodes are fabricated, the impurity profile resulting from the diffusion of
dopants into the semiconductor crystal can often be best approximated, at least in the
immediate neighborhood of the transition region about the junction, as a linear function.
This state of affairs gives rise to the symmetric charge profile, ρ(x), projected by Figure
(P2.13), where parameter m is a profile grade factor having units of atoms/cm4. The figure
at hand obviously implies
ρ(x)
−Wo /2
0
+Wo /2
x
ρ(x) = qmx
Figure (P2.13)
W
W
qmx, − o ≤ x ≤ o
ρ(x) =
2
2 .
0, elsewhere
where q is the magnitude of electron charge, and Wo represents the equilibrium width of the
depletion layer. In addition to the stipulated charge profile, the electric field can be taken as
zero outside of the transition region.
(a). Show that the equilibrium electric field intensity, E(0), at the PN junction of the diode
considered herewith is
qmWo2
E (0) = −
,
8εs
where εs is the dielectric constant of the semiconductor.
(b). Show that the equilibrium width, Wo, of the depletion region is expressible as
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1
⎛ 12εsV j ⎞ 3
Wo = ⎜
,
⎟
⎝ qm ⎠
where Vj is the equilibrium built-in potential of the junction.
(c). Show that the zero bias value, Cjo, of the capacitance associated with the depleted
junction region is
1
⎛ ε 2 qm ⎞ 3
C jo = ⎜ s
.
⎟
⎜ 12V j ⎟
⎝
⎠
(d). If the dopant concentration at x = Wo/2 is No, show that the equilibrium built-in potential, Vj, of the considered PN junction is given by
Vj =
2qN o3
3m 2 εs
.
Problem #2.14
A silicon diode has a p-side dopant concentration of 1016 atoms/cm3, and an n-side dopant
concentration of (8)(1017) atoms/cm3. For equilibrium and room temperature conditions,
calculate the built-in potential of the junction, the width of the junction transition layer, the
maximum magnitude of electric field internal to the junction, and the zero bias value of the
junction capacitance density in units fF/cm2. Assume the validity of the depletion
approximation and take the intrinsic carrier concentration at room temperature to be
(1.5)(1010) atoms-cm−3.
Problem #2.15
A silicon PN junction diode operates at room temperature (27 °C). It has a p-side dopant
concentration of (6)(1016) atoms/cm3, an n-side dopant concentration of (8)(1017) atoms/cm3,
a junction injection coefficient (n) of 1.02, a junction grading coefficient (mj) of 0.5, a junction cross section area of 100 μm2, and an average free charge carrier lifetime (τd) of 75
pSEC. The saturation current of the subject diode is Io = 15 fA. Develop a plot of the total
capacitance, CT, as a function of the diode current, say Id, across the forward biased diode.
On the same graph, plot separately the diffusion and depletion components of this total
capacitance. In arriving at the depletion capacitance characteristic, do not assume that the
turn on voltage, Von, is a constant. Instead, use values of Von that are calculated as a function of specifically considered diode currents.
(a). Compare, and comment on, the magnitudes of the diffusion and depletion capacitance
components.
(b). Develop an empirical relationship for the depletion capacitance across a forward biased junction as a function of the diode current supported by the junction.
Problem #2.16
The design philosophy underlying the deployment of a speedup capacitance, as suggested in
Figure (2.19), to reduce the switching time of a resistance-diode network is commonly applied to linear networks, such as the structures depicted in Figure (P2.16). An electrical
measurement system is a notable system modeled by these structures, where the voltage
vi(t), is to be measured, as accurately as possible, by a voltmeter whose parasitic input
impedance is comprised of the shunt interconnection of a resistance, Ri, and a capacitance,
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Ci. The resistance, Rp, in Figure (2.16a) represents the characteristic impedance of the
measurement probe. It is generally true that Rp << Ri. The speedup capacitance, Cp, in Figure (2.16b) is adjusted (often manually) to a value that achieves an observable measured
voltage, vm(t), that is independent of the frequency spectrum embraced by the voltage, vi(t),
sensed for ultimate measurement.
vi(t)
vm(t)
vi(t)
(a).
vm(t)
(b).
Figure (P2.16)
(a). Assuming that Rp << Ri and that vi(t) is a sinusoid of radial frequency ωi, derive an
expression for the maximum tolerable value of parasitic instrumentation capacitance
Ci, in Figure (2.16a) such that the measured amplitude of voltage vm(t) differs from the
sensed amplitude of vi(t) by less than 5%.
(b). Deduce a design-oriented relationship for capacitance Cp in Figure (2.16b) such that
the measured amplitude of voltage vm(t) is independent of the frequencies implicit to
the sensed signal, vi(t).
(c). Discuss any engineering shortcomings implicit to the capacitor relationship deduced
in the preceding part of this problem.
Problem #2.17
The silicon diode in the circuit of Figure (2.19) has a PN junction injection area of 150 μm2,
an approximately constant p-side dopant concentration of 1017 atoms/cm3, an approximate
n-side dopant concentration of (9)(1018) atoms/cm3, and a free carrier lifetime (in the junction transition region) of 125 pSEC. For relevant computational purposes, assume room
temperature operating conditions and take the intrinsic carrier concentration at room
temperature to be (1.5)(1010) atoms/cm3. The circuit at hand uses VF = VR = 3 volts, while
resistance R is 300 Ω.
(a). With no speedup capacitor utilized (C = 0), calculate the diode turn off time and comment as to the relative contributions of storage and depletion capacitance effects on
this turn off time.
(b). Find an optimum value of speedup capacitance commensurate with the minimization
of the turn off transient. What is the corresponding estimate of the diode turn off
time?
Problem #2.18
In the circuit of Figure (P2.18), VBB = 5 volts, Rs = 300 Ω, and the input signal, vs(t), is a 30
mV step function. The silicon PN junction diode is biased to conduct 10 mA of current at
room temperature. At room temperature, this diode has a saturation current of 25 fA, unity
junction injection coefficient, a built-in junction potential of 850 mV, a zero bias junction
depletion capacitance of 25 fF, a junction grading coefficient of 0.5, and an average carrier
Minh Hsieh Department of Electrical Engineering
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PN Junction Diode
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lifetime in its junction transition layer of 150 pSEC.
Rs
+
vs(t)
id(t)
+
vd(t)
vl(t)
−
−
Rl
+
VBB
−
Figure (P2.18)
(a). What value of the resistance, Rl, is required to support the 10 mA current biasing of the
PN junction diode?
(b). Because the input signal is a step function with a small voltage amplitude, the diode
can be replaced by a small signal model comprised of the shunt interconnection of a
resistance and a capacitance. Calculate the small signal resistance of the diode and the
effective capacitance that it shunts. In arriving at the depletion component of the net
diode capacitance, assume that the turn on voltage of the diode is one Boltzmann
voltage level below the quiescent diode voltage.
(c). Derive an expression for the small signal Laplace transform, say Vl(s), of the indicated
load voltage, vl(t).
(d). Give an expression for the time domain response, vl(t), to the input step voltage, vs(t).
(e). What is the circuit time constant pervasive of the time domain response determined in
the preceding part of this problem?
Problem #2.19
Reconsider the diode and circuit topology studied in Problem #2.18, but let the input signal,
vs(t), be the simple sinusoid, vs(t) = Vmcos(ωt), where the amplitude, Vm, of the subject sinusoid is small enough to justify the use of a small signal model for the PN junction diode.
(a). Derive an expression for the transfer function, H(jω) = Vl(jω)/Vs(jω).
(b). Above what radial frequency is the magnitude response determined in Part (a) nominally independent of the radial frequency, ω, of the input sinusoid?
(c). The steady state load voltage phasor, Vl(jω), has a nonzero phase angle, say ϕ(ω). Derive an expression for this phase response.
Problem #2.20
In the circuit of Figure (P2.9), the two PN junction diodes are forward biased by the
application of the supply line voltage, Vdd. In addition to this input static voltage, a small
signal, vs(t), is inserted directly in series with Vdd. Derive general expressions for the low
frequency, small signal components of each of the indicated diode currents. Assume that
the two diodes are identical, are biased identically, and are characterized by a small signal
resistance of rd at their quiescent operating points.
Problem #2.21
The volt-ampere characteristic of a certain nonlinear resistance is
⎛V ⎞
I = I k tanh ⎜ ⎟ ,
⎝ Vk ⎠
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where Ik and Vk are known constants, and, of course, V is the terminal voltage and I is the
corresponding current conducted by the subject element.
(a). Evaluate the small signal resistance, say r, at zero quiescent terminal voltage.
(b). Over what range of terminal voltage and corresponding element current does the small
signal resistance model deliver volt-ampere characteristics that differ from the actual
characteristics of the nonlinear element by no more than ±10%?
Problem #2.22
The nonlinear resistance in Figure (2.27) has β = 0.05 siemens/volt, Vh = 600 mV, and Vk =
15 volts. The voltage, V, applied across the nonlinearity is a superposition of a quiescent
voltage that is 50% larger than the voltage parameter, Vh, and a sinusoid whose amplitude is
Vm and whose radial frequency is ω; specifically,
V = 1.5Vh + Vm cos ( ωt ) .
(a). Evaluate the quiescent current conducted by the nonlinear resistance.
(b). In terms of voltage amplitude Vm, derive expressions for the amplitudes of the
fundamental frequency component, the second harmonic, and the third harmonic.
(c). Evaluate the percentage total harmonic distortion for Vm = Vh/2, Vm = Vh/3, Vm = Vh/4,
Vm = Vh/5, and Vm = Vh/10.
(d). What is the maximum signal amplitude commensurate with a total harmonic distortion
that is at most 10%?
Problem #2.23
Assume that the volt-ampere characteristic of the nonlinear resistance addressed in Problem
#2.21 can be represented adequately by the truncated power series,
3
5
⎛V ⎞
⎛V ⎞ ⎛V ⎞
I
2 ⎛V ⎞
= tanh ⎜ ⎟ ≈ ⎜ ⎟ − ⎜ ⎟ +
⎜ ⎟ ,
Ik
V
V
V
15
⎝ k⎠
⎝ k⎠ ⎝ k⎠
⎝ Vk ⎠
where the current parameter, Ik, is 5 mA. The applied voltage, V, is the sinusoid,
V = Vm cos ( ωt ) = kVk cos ( ωt ) ,
with constant k representing a positive, less than unity constant.
(a). In terms of parameter k, derive expressions for the current amplitudes of the
fundamental frequency component, the third harmonic, and the fifth harmonic.
(b). Plot the percentage total harmonic distortion as a function of parameter k.
Problem #2.24
In the compression amplifier of Figure (2.33), represent the operational amplifier by the
model offered in Figure (P2.24) to account for the relevant effects of finite open loop gain
(Ao) and nonzero output resistance (ro). Derive an expression for the resultant output voltage, Vo, of the logarithmic amplifier, and compare this result to the idealized disclosure postured by (2-126).
ro
+
v
−
i
−Op-Amp
+
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i
Vo
+
v
−
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−
Vo
A ov
+
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PN Junction Diode
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Figure (P2.24)
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Problem #2.25
In the expander circuit of Figure (2.34), represent the operational amplifier by the model offered in Figure (P2.24) to account for the relevant effects of finite open loop gain and nonzero output resistance. Derive an expression for the resultant output voltage, Vo, of the expander, and compare this result to the idealized disclosure advanced by (2-127).
Problem #2.26
An inductance, L, is inserted in series with the diode in the half wave rectifier of Figure
(2.41). The resultantly filtered power supply adopts the schematic portrayal offered in Figure (P2.26).
Id +
Vd
− vi(t)
L
vo(t)
Rs
RLeff
+
CL
vs(t)
−
Figure (P2.26)
(a). Show that the transfer function, H(s) = Vo(s)/Vi(s), of the imposed filter is of the form
V (s)
1
H(s) = o
=
,
2
Vi (s)
2ζ s ⎛ s ⎞
+⎜
1+
⎟
ωn
⎝ ωn ⎠
where ωn represents the undamped natural frequency of oscillation of the filter, and ζ
is its damping factor. Give expressions for ωn and ζ in terms of the elemental parameters of the filter.
(b). What circuit conditions give rise to a damping factor of ζ = 1/ 2 ? What is the
engineering significance of this particular value of filter damping factor?
(c). The filtered power supply is to be capable of delivering 12 volts at 50 mA with less
than 2% ripple. Determine the requisite values of capacitance CL and inductance L,
given that a damping factor of ζ = 1/ 2 is to be achieved in the filter.
Problem #2.27
The half wave rectifier with capacitive filter does not strictly produce a constant output voltage, but rather, it generates exponentially decaying, periodic pulses, as depicted in Figure
(2.42). Demonstrate that within reasonable approximations, the average, or “DC” value,
say VDC, of the generated output response abides by the expression,
I
VDC ≈ Vomax − DC ,
4 f CL
where IDC represents the average current delivered to the effective load resistance in the
supply, while Vomax is the maximum value of output voltage.
Problem #2.28
Repeat Example #2.6, but realize the quoted operating specifications through use of a half
wave rectifier. The diode model parameters for SPICE circuit simulation are itemized in
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Table (2.1). Simulate the circuit and discuss simulation results in light of response results
predicted by pertinent analyses undertaken in the text.
Problem #2.29
Repeat Example #2.6, but realize the quoted operating specifications through use of a
bridge full wave rectifier. The diode model parameters for SPICE circuit simulation are
itemized in Table (2.1). Simulate the circuit and discuss simulation results in light of response results predicted by pertinent analyses undertaken in the text.
Problem #2.30
In the precision rectifier of Figure (2.46), assume for the purpose of this problem that the
operational amplifier behaves as an ideal voltage controlled voltage source of voltage gain
Ao. The diode has a carrier lifetime of τd and a zero bias depletion capacitance of Cjo. Let
the input signal, vs(t), be the pulse waveform pictured in Figure (P2.30), were it is understood that the positive voltage level, VF, prevails for a very long time prior to its change to
−VR at time t = 0. Derive an approximate relationship for and sketch the diode current response for t ≥ 0+.
vs(t)
VF
time (t)
0
−VR
Figure (P2.30)
Problem #2.31
Use SPICE or comparable circuit simulation software to simulate the time domain response,
vo(t), of the precision rectifier in Figure (2.46). The SPICE model parameters of the diode
are those delineated in Table (P2.31).
SPICE
TEXT
SYMBOL SYMBOL
IS
Io
RS
N
CJO
VJ
M
TT
n
Cjo
Vj
mj
τd
DESCRIPTION
OF PARAMETER
Saturation Current
Net Ohmic Resistance
Injection Coefficient
Zero Bias Depletion Capacitance
Junction Built-In Potential
Grading Coefficient
Average Carrier Transit Time
VALUE UNITS
4.5
0.2
1.03
3.5
800
0.5
10
fA
Ω
–
fF
mV
–
pSEC
Table (P2.31)
Take the input source signal, vs(t), to be a sine wave at a frequency of 2 MHz and an amplitude of 800 μV. The Thévenin resistance, Rs, of this signal source is 50 Ω. The operational
amplifier behaves as an ideal voltage controlled voltage source of voltage gain 10,000.
Depending on the version of SPICE used in the execution of this problem, it may be
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necessary to append resistances of about 100 KΩ between circuit ground and each of the input terminals of the op-amp. Use SPICE to examine the sensitivity of response vo(t) to a
zero bias depletion capacitance that is one-third as large as the value indicated in the table.
Repeat the simulation for a capacitance that is three times larger than the tabulated value.
While adjusting the simulation to account for different junction depletion capacitance values, keep in mind that the principle vehicle for adjusting the junction depletion capacitance
is junction area to which the diode saturation current is directly proportional.
Problem #2.32
An alternative topology to the precision half wave rectifier of Figure (2.46) is shown in Figure (P2.32). The two PN junction diodes, D1 and D2, are identical and have a turn on voltage of Von. The operational amplifier has infinitely large input impedance at either of its
two input ports, and it produces an open loop voltage gain of Ao.
R
vo(t)
Rs
+
vi(t)
vs(t)
−
−
v
+
−
Op-Amp
+
D1
voa(t)
Rl
D2
Figure (P2.32)
(a). When the signal voltage, vs(t), is sufficiently negative, which of the two PN junction
diodes is turned off and which is turned on?
(b). For suitably negative vs(t), derive an expression for the output voltage, vo(t). Simplify
this expression for the case of a very large open loop gain in the op-amp.
(c). For suitably positive vs(t), derive an expression for the output voltage, vo(t). Simplify
this expression for the case of a very large open loop gain in the op-amp.
(d). What is the effect of shunting the load resistance, Rl, by a large capacitance, say Cl?
Problem #2.33
The precision full wave rectifier of Figure (2.48) is modified, as shown in Figure (P2.33),
by the addition of two capacitances, C, as shown. The purpose of these capacitances is to
improve the transient response by mitigating, at least in part, the turn off transients in the
PN junction diodes. For the purpose of this exercise, assume that the operational amplifiers
behave as ideal voltage controlled voltage sources whose open loop voltage gains are each
10,000 volts/volt. The SPICE parameters of the two diodes are those exploited in Example
#2.7, while the input voltage, vs(t), is a 250 MHz, 5 mV sinusoid. Use SPICE to explore the
effectiveness of the introduced compensation capacitances for capacitance values of C = 20
fF, 50 fF, 100 fF, and 250 fF. Submit a design recommendation for the selection of
capacitances C, and provide engineering rationale to support your conclusion.
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C
R
R
R
D1
Rt
−
v1
+
−
Op-Amp
+1
voa(t)
D2
+
−
v2
+
−
Op-Amp
+2
vo(t)
Rl
vs(t)
−
R
C
Figure (P2.33)
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