Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-1
LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORS
LECTURE ORGANIZATION
Outline
• pn junctions
• MOS transistors
• Layout of MOS transistors
• Parasitic bipolar transistors in CMOS technology
• High voltage CMOS transistors
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 29-43
CMOS Analog Circuit Design
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
© P.E. Allen - 2010
Page 050-2
PN JUNCTIONS
How are PN Junctions used in CMOS?
• PN junctions are used to electrically isolate one semiconductor region from another
• PN diodes
• ESD protection
• Creation of the thermal voltage for bandgap purposes
• Depletion capacitors – voltage variable capacitors (varactors)
Components of a pn junction:
1.) p-doped semiconductor – a semiconductor having atoms containing a lack of
electrons (acceptors). The concentration of acceptors is NA in atoms per cubic
centimeter.
2.) n-doped semiconductor – a semiconductor having atoms containing an excess of
electrons (donors). The concentration of these atoms is ND in atoms per cubic
centimeter.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-3
Abrupt PN Junction
Metal-semiconductor junction
pn junction Metal-semiconductor junction
p+ semiconductor
n semiconductor
Depletion Region
W
p+ semiconductor
W1 0
W1 = Depletion width on p side
060121-02
n semiconductor
x
W2
W2 = Depletion width on n side
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
CMOS Analog Circuit Design
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
© P.E. Allen - 2010
Page 050-4
Influence of Doping Level on the Depletion Regions
Intuitively, one can see that the depletion regions are inversely proportional to the doping
level. To achieve equilibrium, equal and opposite fixed charge on both sides of the
junction are required. Therefore, the larger the doping the smaller the depletion region
on that side of the junction.
The equations that result are:
2(o-vD)
1
W1 =
N
N
A
A
qNA1+ND
and
2(o-vD)
1
W2 =
N
N
D
D
qND1+NA Assume that vD = 0, o = 0.637V and ND = 1017 atoms/cm3. Find the p-side depletion
region width if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
For NA = 1015 atoms/cm3 the p-side depletion width is 0.90 μm.
For NA = 1019 atoms/cm3 the p-side depletion width is 0.9 nm.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-5
Graphical Characterization of the Abrupt PN Junction
Assume the pn junction is open-circuited.
Impurity Concentration (cm-3)
ND
Cross-section of an ideal pn junction:
xp
p+ semiconductor
iD
NA
Impurity Concentration (cm-3)
qND
-W1
x
0
W2
n semiconductor
+
x
0
xd
xn
vD −
-qNA
060121-03
Symbol for the pn junction:
iD
Built-in potential, o:
NAND
+v o = Vt ln n 2 ,
D
i
iD
where
kT
+v D
Vt = q
Fig. 06-03
ni is the intrinsic concentration of silicon.
Electric Field (V/cm)
x
E0
Potential (V)
ψο
x
xd
CMOS Analog Circuit Design
060121-04
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Reverse-Biased PN Junctions
Depletion region:
xd = xp + xn = W 1 + W2
xp = W 1 vR
and
xn = W 2 vR
Page 050-6
xd
vD
iD
Influence
of vR on
depletion
region width
− vR = 0V +
xd
vR
060121-05
Breakdown voltage (BV):
If vR > BV, avalanche multiplication will
occur resulting in a high conduction state as
illustrated.
− vR > 0V +
iD
BV
vD
Reverse
Bias
Forward
Bias
060121-06
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-7
Breakdown Voltage as a Function of Doping
It can be shown that†:
si(NA+ND) 2
BV 2qNAND Emax
where Emax = 3x105 V/cm for silicon.
An example:
Assume that ND = 1017 atoms/cm3.
Find BV if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
NA = 1015 atoms/cm3:
si 2
1.04x10-12·9x1010
If NA << ND, then BV 2qNA Emax = 2·1.6x10-19·1015 = 291V
NA = 1019 atoms/cm3:
si 2
1.04x10-12·9x1010
If NA >> ND, then BV 2qND Emax = 2·1.6x10-19·1017 = 2.91V
†
P. Allen and D. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, 2002
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-8
Depletion Capacitance
Physical viewpoint of the depletion capacitance:
d
xd
siA
siA
Cj = d = W 1+W 2
siA
=
2si(o-vD) ND
q(ND+NA) NA +
=A
=
siqNAND
2(NA+ND)
Cj0
vD
1-o
CMOS Analog Circuit Design
W1
W2
−
−
−
−
−
−
060204-01
+
+
+
+
+
+
+ vD −
Cj
NA ND
Ideal
Cj0
1
o-vD
GummelPoon Effect
Reverse Bias
0
v
ψo D
060204-02
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-9
Forward-Biased PN Junctions
When the pn junction is forward-biased, the potential barrier is reduced and significant
current begins to flow across the junction. This current is given by:
v Dnnpo qAD ni2
D
Dppno
-V GO
3
where Is = qA Lp + Ln L N = KT exp V iD = Isexp V t -1
t
Graphically, the iD versus vD characteristics are given as:
25
20
iD 15
Is 10
5
0
-5
ln(iD/Is)
-4
-3
-2
-1
0
1
vD/Vt
2
3
Decade current
change/60mV
or
Octave current
change/18mV
4
10 x1016
8 x1016
16
iD 6 x10
Is
4 x1016
2 x1016
vD
0V
060204-03
0
-40
-30
-20
-10
0
vD/Vt
10
20
30
40
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-10
Graded PN Junctions
In practice, the pn junction is graded rather than abrupt.
Impurity
Concentration Impurity profile
approximates a
p+
constant slope
n+
p+
Intrinsic
Concentration
x
x
0
Surface
Junction
060204-04
The previous expressions become:
Depletion region widthsDepletion capacitance
2
(
-v
)N
si o D Dm 1
siqNAND m
W 1= qNA(NA+ND) C
=
A
j
1 m
2(N
+N
)
A
D
o-vD m
W N
2si(o-vD)NA m
Cj0
W 2= qND(NA+ND) = vD m
1-
o
where 0.33 m 0.5.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-11
Metal-Semiconductor Junctions
Ohmic Junctions: A pn junction formed by a highly doped semiconductor and metal.
Energy band diagram
IV Characteristics
I
1
Vacuum Level
;;;;
;;;;
Thermionic
or tunneling
qφm
qφs
qφB
n-type metal
Contact
Resistance
EC
EF
EV
n-type semiconductor
V
Fig. 2.3-4
Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal.
Energy band diagram
IV Characteristics
;;;;
;;;;
;;;;
qφB
n-type metal
I
Forward Bias
EC
EF
Reverse Bias
Forward Bias
Reverse Bias
V
EV
Fig. 2.3-5
n-type semiconductor
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-12
MOS TRANSISTOR
PHYSICAL ASPECTS OF MOS TRANSISTORS
Physical Structure of MOS Transistors in an n-well Technology
Substrate Salicide
Substrate Salicide
Well Salicide
W
n+
Shallow
Trench
Isolation
W
p+
p+
L
nn++
L
Shallow
Trench
Isolation
n-well
nnn+++
p-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
070322-02
Metal
Width (W) of the MOSFET = Width of the source/drain diffusion
Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions
Note that the MOSFET is isolated from the well/substrate by reverse biasing the
resulting pn junction
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-13
Enhancement MOSFETs
The channel of an enhancement MOSFET is formed when the proper potential is applied
to the gate of the MOSFET. This potential inverts the material immediately below the
gate to the same type of impurity as the source and drain forming the channel.
VGS=0V
S
0V<VGS<VT V <V (sat)
DS DS
VDS<VDS(sat)
G
D
S
VDS
Cutoff
G
D
VGS>VT
S
VDS
G
VDS<VDS(sat)
D
VDS
Strong Inversion
Weak Inversion
060205-06
V T = Gate-bulk work function (MS) + voltage to change the surface potential (-2F)
+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)
+ voltage to compensate the undesired interface charge (-Qss/Cox)
Qb0 QSS Qb-Qb0
V T = MS -2F - Cox - Cox - Cox
= VT0 + |-2F+vSB|- |-2F|
where
Qb0 QSS
2qsiNA
VT0 = MS - 2F - Cox - Cox , = Cox
and Qb 2qNAsi(|-2F+vSB|)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-14
Depletion Mode MOSFET
The channel is diffused into the substrate so that a channel exists between the source and
drain with no external gate potential.
Source Gate
Drain
p+
an
Ch
Polysilicon
ne
lW
id
th
,W
Bulk
Fig.
4.3-4
n+
n+
n-channel
Channel
Length, L
p substrate (bulk)
The threshold voltage for a depletion mode NMOS transistor will be negative (a negative
gate potential is necessary to attract enough holes underneath the gate to cause this
region to invert to p-type material).
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-15
Weak Inversion Operation
0V<VGS<VT VDS<VDS(sat)
Weak inversion operation occurs when the applied
gate voltage is below VT and occurs when the surface
of the substrate beneath the gate is weakly inverted.
Regions of operation according to the surface
potential, S.
S < F :
Substrate not inverted
F < S < 2F :
Channel is weakly inverted
(diffusion current)
2F < S :
Strong inversion (drift current)
log iD
Diffusion Current
Drift current versus
diffusion current in a
MOSFET:
10-6
10-12
0
G
S
D
VDS
Diffusion
Current
Weak Inversion
060205-07
Drift Current
VGS
VT
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-16
LAYOUT OF MOS TRANSISTORS
Layout of a Single MOS transistor:
L
STI
L
Well/Bulk
Well/Bulk
Drain
Drain
W
W
p-well
n-well
Gate Source
Gate Source
060223-01
Comments:
• Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.
• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-17
Geometric Effects
Orientation:
Devices oriented in the same direction match more precisely than those oriented in other
directions.
;;;;
;;
;;;;
;;
Good Matching
;;
;;;;;
;;
;;;
;;
Poorer Matching
041027-02
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-18
;;
;;
;;
;;
;;
;;;
;;
;;
;;
;;
;;;
;;
;;
;;
;;
;;;;;
;;
;;;;;
Diffusion and Etch Effects
• Poly etch rate variation – use dummy elements to prevent etch rate differences.
Dummy
Gate
Dummy
Gate
041027-03
• Do not put contacts on top of the gate for matched transistors.
• Be careful of diffusion interactions for diffusions near the channel of the MOSFET
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-19
Thermal and Stress Effects
• Oxide gradients – use common centroid geometry layout
• Stress gradients – use proper location and common centroid geometry layout
• Thermal gradients – keep transistors well away from power devices and use common
centroid geometry layout with interdigitated transistors
Examples of Common Centroid Interdigitated transistor layout:
SA/SB
DA
B
DA
A
GA
GB
GB
GA
Interdigitated, common centroid layout
041027-04
A
B
GA
GB
GB
GA
B
A
Dummy Gate
B
SA/SB
Dummy Gate
A
DB
Dummy Gate
SA/SB
Dummy Gate
DA
DB
DB SB/SA DA
Cross-Coupled Transistors
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-20
MOS Transistor Layout
Photolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI
comes from optical interactions between the UV light and the masks.
Examples of the layout of matched MOS transistors:
1.) Examples of mirror symmetry and photolithographic invariance.
;;
;
;;
;
;;
;
;;;
Mirror Symmetry
CMOS Analog Circuit Design
;;;;
;;
;;;;
;;
Photolithographic Invariance
Fig. 2.6-05
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-21
MOS Transistor Layout - Continued
2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.
;;
;
;;;
;;
;
;;;
Metal 2
Via 1
;;;;
;
;;
;;
;
;;;;;;;;
;;;;
;
;;
;;
;
;;;;;;;;
Metal 1
Fig. 2.6-06
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-22
MOS Transistor Layout - Continued
3.) Compact layout of the previous example.
Metal 2
;;;;;;;
;;
;;;
;;
;;
;;;
;;
;;;;;;;
Via 1
Metal 2
CMOS Analog Circuit Design
Metal 1
Fig. 2.6-07
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-23
PARASITIC BIPOLAR TRANSISTORS IN CMOS TECHNOLOGY
A Lateral Bipolar Transistor
E
B
VC
LC
LC
n-well CMOS technology:
p+ p+
n+
p+
• It is desirable to have the lateral
collector current much larger than the
STI
STI
vertical collector current.
n-well
• Lateral BJT generally has good
Substrate
matching.
060221-01
• The lateral BJT can be used as a
photodetector with reasonably good
Vertical
STI
Lateral Collector
Collector
efficiency.
• Triple well technology allows the
Emitter
current of the vertical collector to
avoid the substrate.
Base
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-24
A Field-Aided Lateral BJT
Use minimum channel length to
enhance beta:
ßF 50 to 100 depending on
the process
VC
STI
B
LC
E
LC
n+
p+
p+
pp++
Keeps carriers from
flowing at the surface
and reduces 1/f noise
n-well
STI
Substrate
060221-02
Vertical
Collector
STI
Lateral Collector Emitter
Base
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-25
HIGH VOLTAGE CMOS TRANSISTORS
Extended Voltage MOSFETS
The electric field from the source to drain in the channel is shown below.
Electric
Field
Emax
Area = Vp
0
Distance, x
;;;
;;;;;;
;;;
;;;;;;;;;;;
;;;
;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;;
;;;;;;;;;;;
Pinch-off region
Source
depletion
region
Area = Vd
Source n+
Channel
xp
xd
Drain n+
Drain
depletion
region
Substrate depletion region
p - substrate
040920-01
The voltage drop from drain to source is,
V DS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)
Emax and xp are limited by hot carrier generation and channel length modulation
requirements whereas these limitations do not exist for xd.
Therefore, to get extended voltage transistors, make xd larger.
CMOS Analog Circuit Design
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
© P.E. Allen - 2010
Page 050-26
High Voltage Architectures
The objective is to create a lightly doped, extended drain region where the high voltage
of the drain can drop down to a level that will not cause the gate oxide to breakdown.
LOCOS Architecture:
DSM Architecture:
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-27
Lateral DMOS (LDMOS) Using LOCOS CMOS Technology
The LDMOS structure is designed to provide sufficient lateral dimension and to prevent
oxide breakdown by the higher drain voltages.
One possible implementation using LOCOS technology:
Drain
Gate
n+
Source/Bulk
n+
xd
p-body
p epi
p+
Gate
Drain
n+
n+
p-body
xd
n well
p substrate
p epi
071025-01
• Structure is symmetrical about the source/bulk contact
• Channel is formed in the p region under the gates
• The lightly doped n region between the drain side of the channel and the n+ drain
contact (xd) increases the depletion region width on the drain side of the channel/drain
pn junction resulting in larger values of vDS.
• Drain voltage can be 20-30V
CMOS Analog Circuit Design
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
© P.E. Allen - 2010
Page 050-28
Lateral DMOS (LDMOS) Using DSM CMOS Technology
Cross-section of an
NLDMOS using DSM
technology:
Differences between an NLDMOS and NMOS:
• Asymmetry
• Non-uniform channel
• Current flow (not all at the surface)
• No self-alignment (larger drain-gate overlap
capacitance)
• Note the extended drift region on the drain side of the
channel
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 050 – PN Junction and CMOS Transistors (4/30/10)
Page 050-29
SUMMARY
• pn junction usage in CMOS include:
- Electrical isolation, pn diodes, ESD protection, depletion capacitors
• Depletion region widths are inversely proportional to the doping
• Depletion region widths are proportional to the reverse bias voltage
• Ohmic metal-semiconductor junctions require a highly doped semiconductor
• MOSFETs can be:
- Enhancement – the applied gate voltage forms the channel
- Depletion – the channel is physically constructed in fabrication
• The threshold voltage of MOSFETs consists of the following components:
- Gate bulk work function (MS)
- Voltage to change the surface potential (-2F)
- Voltage to offset the channel-bulk depletion charge (-Qb/Cox)
- Voltage to compensate the undesired interface charge (-Qss/Cox)
• Weak inversion is MOSFET operation with the gate-source voltage less than the
threshold voltage
• Layout of the MOSFET is important to its performance and matching capabilities
• Extended drain regions lead to higher voltage capability MOSFETs
CMOS Analog Circuit Design
© P.E. Allen - 2010