Statistical Quality Control of Wafer Level DC Die Sort Test
Y.Z. Wang, R.S. Persaud, R.C. Salvador, D. J. Troy
ANADIGICS, INC.
141 Mt. Bethel Road, Warren, NJ 07059
Tel: (908) 668-5000, e-mail: ywang@anadigics.com
Keywords: Die Sort, statistical quality control, yield, yield
excursion
Abstract
In this report, we developed a statistical quality
control (SQC) system associated in our test programs to
control wafer level DC Die Sort test by providing controls
over TRI failures, bin yield loss and mean and standard
deviation variances of key parameters. This SQC system
has dramatically reduced the test caused yield loss ~1.2%
since the tool was implemented. The yield excursions
have been captured in real-time from the control of bin
yields and variability of the critical parameters.
Productivity is also greatly improved by integrating
automated recipe downloading and TRI re-test as well as
Die Sort disposition decision making into the process.
INTRODUCTION
The increasing competition and the challenges of cost
reduction have forced the GaAs manufacturers to pursue the
improvements in die yield and cycle time [1].
The
ANADIGICS wafer fab is working towards a goal of a “Good
Die Fab” mentality (as opposed to a “Good Wafer Fab”
mentality) [2]. To achieve this goal, we would not only need
to maintain higher cumulative wafer yields, but it must also
increase die yields. This requires us to reduce the yield loss at
the wafer level DC Die Sort test to ensure die level
compliance. The Die Sort test is used to screen out die level
defects, process or material variations resulted in device or
circuit failures as measured on the die [3]. The criteria that
we had used to disposition products at Die Sort for some time
was to apply a minimum yield limit for each wafer by
product. However, a large quantity of die loss may be
incurred due to test-related failures. Since the measured Die
Sort yield was above the minimum yield standard, the wafer
would continue processing and the learning regarding the
failure would be lost. In addition, the wafers showing unique
process or material signatures may pass the minimum yield
without requiring engineering attention. If the process or
material caused electrical parameter shifts, we would not
know until generating the historical trend charts.
The objective of statistical quality control (SQC) at Die
Sort test is to provide a control system by implementing
controls over test related failures, Die Sort bin yield loss and
critical parameter stability. This includes the integration of
control limits which are imbedded into the Die Sort test
program for each product while providing a system to
perform an automated Die Sort disposition. With an SQC
control system, we are able to reduce the Die Sort yield loss
on testing related issue (TRI) caused failures, which in turn
relieves engineering disposition resources while reducing the
cycle time. In addition, yield excursion and process shifts are
captured in real-time on wafer to wafer base.
DIESORT TEST PROCEDURE
ANADIGICS wafer level DC Die Sort test is performed
in an integrated PXI test platform interfaced to an EG4090
prober. The tester delivers the measurement capability
required by the production with high breakdown voltage
capability, low-current measurement accuracy and flexibility
[4]. The PXI-based tester provides a calibrated system that
met the high-speed throughput as well as exceeding the
acceptable gauge R&R requirements for key parameter
measurements. This is a prerequisite condition for statistical
quality control of Die Sort probing. Periodic golden wafer
verification procedures have also been established to ensure
the test gauge capability.
For Die Sort testing prior to the SQC implementation, an
operator would load the test program template for the product
that was to be probed, and then loaded the first wafer, aligned
the wafer and started to probe. When the whole lot was
completed Die Sort test, the operator could reload the lot to
test the failures if the Die Sort yield is below the minimum
yield standard, or operator could move the lot to next process
step when passing the minimum yield standard. For wafer
passing the minimum yield standard, operator had no
visibility whether the failed wafers were caused by TRI
failures or by the unique material or process defects. Running
a retest was completely dependent on the operator’s
judgments or the engineering disposition requirements. In
some cases, it even took a longer time for operator to reload
the lot than to retest failures on wafer. Running a retest at Die
Sort was a time-consuming process.
In the SQC of Die Sort probing, we developed a system
for in-situ control of the Die Sort test. The SQC system is
associated in the product program template. It will be loaded
when pulling out a corresponding test program by inputting a
lot number. When a wafer is completely probed, the SQC
disposition information of the wafer will show up on the
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79
screen. Operator follows the guidance to take the actions.
Figure 1 shows the SQC test flow chart. When a wafer needs
to be retested, the operator will be guided to do so following
the OCAP procedure without unloading the wafer. That
greatly saves on test time.
be close to the sanity limits. However, it is necessary to
adjust the limits for some parameters so that the TRI failures
are really captured. These types of failures are easily
recovered by re-testing failures while adjusting either
alignment, Z-height or by cleaning the probe tips.
14
Lot Start
Yield Improvement from TRI, %
12
Load Wafer
Probe Wafer
Save "P" file &
Track
Disposition
Message
Delta Yield,%
10
8
6
4
2
TRI Failure?
Yes w/TRI -Retest Message
0
Load Next
Wafer
1
No w/ Other
Messages
15
22
29
36
43
50
57
64
71
78
85
92
99 106 113 120 127 134 141 148 155 162 169 176
Wafer Number
Continue
Retest
Unload Wafer
Yes w/ TRI -on Hold message
Figure 2. The delta yield improved from TRI re-test of a
single product with the SQC.
Follow OCAP?
Yes
OK
No w/ other messages
More wafers
to test ?
End Test
8
Retest/Continue
Mode Select
No
Retest Failures
TRI Failure?
Save "R" File &
Track Message
Figure 1. The Die Sort test flow chart using the SQC.
RESULTS AND DISCUSSIONS
The Die Sort SQC system consists of three parts: TRI
failure control, Die Sort bin control and parameter 3sigma
control. For each key parameter the control limits are set up
in these three parts based on the historical data. The SQC
priority is in the order of TRI failure, Die Sort bin and then
parameter 3sigma. The SQC results will show up in the
screen and it is also saved in the Die Sort data file when the
wafer is completely probed.
Figure 2 shows the delta yield improvement from TRI retest of a single product with the SQC control. The improved
yield is determined by the difference between the wafer yield
with TRI re-test and the initial yield, which varies from near
0% up to >10%, and the average yield improvement is
~1.20% per wafer. From the improved yield in Figure 2 we
can see some wafers have higher yield loss on the TRI
failures, these failures are normally distributed in different
parameters. Figure 3 shows the yield loss comparison of the
electrical parameters before and after the implementation of
SQC for the same product shown in Figure 2. This figure
clearly shows the significant yield improvements for most
parameters with the introduction of SQC. From Figures 2 and
3 we can see ~ 0% improvement for some wafers or some
parameters. It indicates the catastrophic failures may be the
real failures from circuit open or shorting caused by defects.
The TRI limits cannot completely distinguish the TRI failures
and the defect caused failures. In order to reduce unnecessary
re-test, a limit for TRI failed die count limit is put in place for
each parameter.
2.
1. TRI Failure Control
From the Die Sort historical data analysis, the number one
failure mode at Die Sort was the TRI caused yield loss prior
to SQC implementation. Probing misalignment, probe
contact and the contamination of probing tips were the
possible root causes of the TRI failures. The TRI failures
contributed the most to catastrophic failures recorded at Die
Sort test. For most parameters the control limits of TRI can
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Die Sort Bin Control
The Die Sort test can screen out electrical failures that
are outside the parameter specification limits and defect
caused circuit or device failures. The defect limited yield
(DLY) loss has a random variation from parameter to
parameter and wafer to wafer. Whereas the parametric
limited yield (PLY) loss may indicate the material or process
is out of control or the design has deviated significantly from
the target value on a given product. When implementing
CS MANTECH Conference, April 24-27, 2006, Vancouver, British Columbia, Canada
parameter yield loss control at Die Sort test, it is easy to
capture the yield excursions. From the data analysis, we can
detect root cause quickly. For a new product we are able to
accelerate the yield learning, too.
0.3
Pre_SQC
0.25
Post_SQC
Yield Loss, %
0.2
0.15
0.1
(b)
0.05
0
RB1_bias
RB2_bias
RB3_bias
Ipd_Vm0
Imode_Vm0
VB2_Vm0
Imode_Vm3 IccSunLK
Parameter
Figure 3. The yield loss comparison of the electrical
parameters pre and post the implementation of SQC.
Figure 4 shows the pie charts of the limited yield loss
comparison with and without SQC implemented for a single
high running product. In the charts, the yield loss is split into
TRI, DLY and PLY yield loss respectively. Prior to the SQC
implementation the TRI yield loss was the highest in total
yield loss. With the implementing of SQC the total yield loss
is reduced, and the losses due to TRI are dramatically
decreased from ~40% to ~16%. Both DLY and PLY losses
are almost equally split for the remaining yield loss at Die
Sort.
Figure 4. The limited yield loss (a) without SQC implement,
(b) with SQC implement.
Figure 5 shows VB2_Vm0 yield excursions of a CDMA
power amplifier product at Die Sort. In a certain time frame
more than 5 production lots had VB2_Vm0 out of the bin
control limit and it also caused higher yield loss. The yield
loss was up to 8% per wafer. From the data analysis the
VB2_Vm0 failures were found to be related to the NV1
openings where the first layer interconnections to resistor or
base contacts are located. The SEM pictures on the contact
revealed that a damaged stripe next to the contact resulting in
VB2_Vm0 failures at Die Sort. It indicates that yield
excursion can be captured and a problem can be isolated in
time using bin control in place of the minimum yield loss.
9.0
VB2_Vm0 %
8.0
VB2_Vm0 Yield Loss, %
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1
14 27 40 53 66 79 92 105 118 131 144 157 170 183 196 209 222 235 248 261 274 287 300 313 326
Wafert Number
Figure 5. VB2_Vm0 yield excursions of a CDMA power
amplifier product at Die Sort.
3.
(a)
Parameter 3sigma control
In the third part of Die Sort SQC program, the across
wafer averages and standard deviations of the critical
parameters are monitored to determine the significant
changes in the mean and in the variance. The control limits
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are calculated using +/- 3 sigma of the parameter historical
data to indicate the boundary limits for the mean and standard
deviation. When the mean shifts or the variation changes, it
implies that the process or material have shifted and requires
investigation to return the parameter back under control.
Figure 6 shows the bias resistance deviation control chart
from a major product during a specific time frame. From the
figure we can see the deviation of bias resistance is out of
control starting from wafer No. 120 in the chart. This
variation of the bias resistance deviation did not cause the
bias resistance to go outside of specification limits, and there
were no yield losses. However, the bias resistance showed a
“bull’s eye” pattern at the wafer center. It indicated that our
bias resistor process was out of control. From a fusing current
test that is used to force device damage by sweeping current,
we found that the resistors within the “bull’s eye” failed at
the resistor to metal contact. This was different from the
normal resistor, which had the resistor itself failed as a result
of the fusing test. The root cause was identified as inadequate
photo process latitude which resulted in the slight plasma
damage to the contacts. The problem was subsequently fixed
when the root cause was identified, and the process was back
in control from wafer No. 300. This example demonstrates
the importance of 3 sigma statistical control of the critical
parameters at Die Sort.
R_Bias Across Wafer Standard Deviation
14
12
CONCLUSIONS
We developed a SQC system associated in our Die Sort
test programs to control TRI failures, bin yield loss as well as
stability of the critical parameters. This SQC system
dramatically reduces the TRI caused yield loss at Die Sort
test, and overall ~1.2% yield is improved with the auto TRI
re-test since the tool was implemented. The yield excursions
caused by the process or material variations have been
captured in real-time from the control of bin yield and mean
and deviation of critical parameters. Productivity is greatly
improved by integrating automated re-test and Die Sort
disposition decision making into the process.
The
methodology is so successful that it has been propagated to
our PCM testing process.
ACKNOWLEDGEMENTS
The authors would like to thank Mr. Henry Ang of
ANADIGICS for his contributions to this work. We would
also like to express our appreciations to Mr. Gregory Guth of
ANADIGICS for the useful discussions.
REFERENCES
[1]. J. Bordelon, et al., IEEE Design & Test of Computers,
Vol. 19, No. 3, May 2002.
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[2]. R. B. Miller, W. C. Riordan, Proceedings of 2001
International Test Conference, pp. 1118-1127, Oct. 2001.
UCL
6
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UCL
[3]. P. Bohlinger, Y. Z. Wang, T. McGuine and C. Nielson,
2001 GaAs MANTECH Technical Digest, pp. 37-40, May
2001.
2
LCL
514
495
476
457
438
419
400
381
362
343
324
305
286
267
248
229
210
191
172
153
96
134
115
77
58
39
1
20
0
Wafer Number
Figure 6. The bias resistance standard deviation SQC control
chart from a major product during a specific time frame.
The wafer level Die Sort testing was a bottleneck to
throughput because many lots need engineering attention
before continuing to process. Since the SQC of Die Sort test
was implemented, the TRI failures are going to be re-tested
immediately following the wafer Die Sort test. The
automated disposition information for each wafer is clearly
shown in the Die Sort map. Operators can move lots
following the disposition message without the engineer’s
involvement. From the comparison pre and post SQC
implementation, the re-testing rates are comparable.
82
However, the wafers held for engineering disposition were
dramatically reduced ~65% by implementing SQC. With the
application of SQC, wafer level DC Die Sort test can also use
sampling strategy when the 100% automated defect
inspection is applied in wafer fab. All these efforts greatly
improve the productivity of Die Sort test and reduce the
overall cycle time.
[4]. Pickering Interfaces, User Manual of Matrix Module,
Issue 3, pp.6.1-6.2, March 2002.
ACRONYMS
SQC: Statistical Quality Control
TRI: Testing Related Issue
DLY: Defect Limited Yield
PLY: Parametric Limited Yield
CDMA: Time Division Multiple Access
OCAP: Out of Control Action Procedure
PCM: Process Control Monitor
CS MANTECH Conference, April 24-27, 2006, Vancouver, British Columbia, Canada