INVITED
PAPER
Regional, National, and
International Nanoelectronics
Research Programs: Topical
Concentration and Gaps
This survey of electric research programs aims to encourage international
collaboration; examples of collaborative programs are provided and
funding sources are identified.
By Michel Brillouët, Member IEEE , George I. Bourianoff, Member IEEE ,
Ralph Keary Cavin, III, Life Fellow IEEE , Toshiro Hiramoto, Member IEEE ,
James A. Hutchby, Life Fellow IEEE , Adrian M. Ionescu, Senior Member IEEE , and
Ken Uchida, Member IEEE
ABSTRACT | This paper will outline some results obtained by an
I. INTRODUCTION
international working group on nanoelectronics, which collects
In the last decades, the electronics industry has been a
major enabler of the computer, communication, and consumer industries that have propelled the growth of the
world economy. The impressive success of microelectronics relies on the beneficial effects of scaling the
critical dimensions of the complementary metal–oxide–
semiconductor (CMOS) technology, bringing at the same
time a higher integration density, a reduced cost per
function, and better performances. However, in the next
one or two decades, CMOS scaling eventually will approach hard limits either physical or economical. This has
triggered an intense search worldwide for new information processing paradigms and related technologies
that will allow continuing progress for another 30 years
or more.
Research on nanotechnologies is expected to contribute greatly in this quest for new computation frameworks
and an enhanced communication among the different
nanotechnology fields is of paramount importance. A
unique conferenceVcalled the International Nanotechnology Conference on Communication and Cooperation
(INC)Vstarted in 2005 to foster communication and cooperation on electronics-related nanotechnology fields
among the various research stakeholders. Initiated by
Europe, Japan, and the United States to further strengthen
a continuous dialogue, the INC effort provides broad
data from major publicly funded programs in Europe, Japan,
and the United States on long-term nanoelectronics research. It
maps these programs and projects onto a set of research
directions that are expected to drive nanoelectronics for the
long term. The purpose is to identify those research topics
attracting a lot of attention and those important topics that
seem less attractive. This paper will give examples of interregional collaborative programs and identify sources of funding
specifically provided to support international collaborations.
KEYWORDS
|
Collaborative work; information technology;
international relations; nanoarchitecture; nanoelectronics;
nanotechnology
Manuscript received February 2, 2010; revised April 7, 2010; accepted May 25, 2010.
Date of publication September 23, 2010; date of current version November 19, 2010.
M. Brillouët is with CEA-LETI, 38054 Grenoble Cedex 9, France
(e-mail: michel.brillouet@cea.fr).
G. I. Bourianoff is with the Technology & Manufacturing Group-External Programs,
Intel Corporation, Austin, TX 78746 USA (e-mail: george.i.bourianoff@intel.com).
R. K. Cavin, III and J. A. Hutchby are with SRC, Research Triangle Park,
NC 27709-2053 USA (e-mail: Ralph.Cavin@src.org; hutchby@src.org).
T. Hiramoto is with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan (e-mail: hiramoto@iis.u-tokyo.ac.jp).
A. M. Ionescu is with School of Engineering (STI)VNanolab, EPFL, 1015 Lausanne,
Switzerland (e-mail: andrian.ionescu@epfl.ch).
K. Uchida is with the Department of Physical Electronics, Graduate School of
Engineering, Tokyo Institute of Technology, Tokyo 1528552, Japan
(e-mail: uchida.k.ag@m.titech.ac.jp).
Digital Object Identifier: 10.1109/JPROC.2010.2061210
0018-9219/$26.00 2010 IEEE
Vol. 98, No. 12, December 2010 | Proceedings of the IEEE
1993
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
overviews of regional programs from each of the regions1
combined with in-depth technical reviews of this promising
field.
In the same period, the International Technology
Roadmap for Semiconductors (ITRS) recognized the
potential value of an alternative computational paradigm.
The ITRS’ Emerging Research Devices chapter (ITRS/ERD)
[1]Vcomplemented by an Emerging Research Materials
chapterVsurveys, assesses, and catalogs viable new information processing devices and architectures for their longrange potential, their technological maturity, and the
challenges to be overcome for further development.
There is a need to link the technical challenges outlined
by the ITRS roadmapping effort and the nanotechnology
programs performed in major regions and to identify paths
for better synergies. Responding to this necessity, the
semiconductor community formed an ad hoc international
working group to promote international research collaborations on basic, precompetitive topics targeting new
information processing technologies. This collaborative
group, the International Planning Working Group on
Nanoelectronics (IPWGN), consisting of members from
Europe, Japan, and the United States, collects information
on major national and regional nanoelectronics research
programs and maps the research topics/objectives of these
programs against a set of research needs. This mapping
exercise, once completed for all major research programs,
highlights research gaps and potential for reduced overlaps. The Working Group also looks for available funding
tools to encourage international research collaborations.
The aim of this paper is to outline some results from
this Working Group with a goal of encouraging international research collaborations especially on topics requiring additional attention.
II. IPWGN
A. Background
For almost one decade, the ITRS/ERD chapter appears
to have influenced technical research directions in Europe,
Japan, the United States, and other regions where substantial long-term research efforts are under way in nanoelectronics. At the same time, the scientific community is
fairly aware of the daunting challenges of finding and
building new computing paradigms, which would be ready
for industrial development in less than two decades. The
number of ideas and options to be explored is exploding
and a better and up-to-date view of the ongoing programs
and gaps in this research field is an important input for
policy makers and research laboratories alike in making
decisions for future work. Being at this stage precompetitive, the research on developing a new information
processing approach is best suited for pulling interna1
In this paper, the word Bregion[ means more specifically Europe,
Japan, or the United States.
1994
tional efforts together: the INC conferences provide the
forum for interregional communications, coordination,
and cooperation.
Sponsored both by the ITRS/ERD Technical Working
Group and the INC, the IPWGN began in 2006 as an
international group of scientists from Europe, Japan, and
the United States tasked with the mission of gathering,
vetting, and organizing the information on nanoelectronics
programs in their respective region with a goal of identifying global gaps in the long-term nanoelectronics
research and of encouraging interregional research collaborations especially in under resourced research topics.
B. Technical Domain Covered by the IPWGN
The technical domain covered by the IPWGN follows
the focus of the ITRS/ERD chapter: it addresses what is
often called Bextended CMOS,[ including Bbeyond
CMOS[2 or to be more precise Ball new approaches proposed to scale some functional performance of information
processing substantially (i.e., orders of magnitude) beyond
that attainable by ultimately scaled CMOS.[ In this wording, Bultimately scaled CMOS[ may be perceived as a
moving target and should be understood as the estimation
of the best performance attainable by the present technology of CMOS integrated circuits scaled to its presently
perceived ultimate limits. The expected performance of
the Bultimately scaled CMOS[ that any alternative solution must beat is extensively discussed in the ITRS/ERD
chapter and will not be discussed any further here.
C. Activities of the IPWGN
As mentioned, the IPWGN has the charter to collect
information on research programs, identify gaps, and stimulate international collaboration.
Understanding the scope and size of publicly funded
regional nanoelectronics research programs has been the
main task of this group from the beginning. This is a neverending activity as long as new programs are launched in
different regions. Finding the right granularity in the
mapping process and partitioning these programs under
meaningful keywords has required several iterations
and greatly benefited from the work done within the
ITRS/ERD.
To identify potential research gaps one need first to
identify the important research directions (also called
Bresearch vectors[ or Bguiding principles[): a significant
time has been spent in defining common priorities among
the different regions. Mapping the ongoing programs onto
these research vectors requires some in-depth analysis of the
details of the programs: when achieved one can pinpoint
2
Though often used, the expression Bbeyond CMOS[ is rather
confusing and/or inaccurate. Furthermore, it has different interpretations
in the different regions of the world. It will thus be preferably avoided
here to define the technical fields addressed by the IPWGN in looking for
future approaches of the nanoelectronics.
Proceedings of the IEEE | Vol. 98, No. 12, December 2010
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
Table 1 Thirteen BResearch Vectors[ Defined by the U.S. Nanoelectronics Research Initiative for Developing a New Logic Switch Able to
Replace the Current CMOS-Based Gate
Table 2 Six BFundamental Guiding Principles[ Defined by the ITRS/ERD for BBeyond CMOS Information Processing[ and Partly Derived and
Condensed From Table 1
where major research resources are assigned and where gaps
are developing worldwide.
Stimulation of international collaboration is probably
the most difficult part of the IPWGN activity. On the one
hand, the IPWGN is not entitled to promote research
groups best suited to address gaps or to organize specific
cooperation between regions. In the same way, it is not in
the IPWGN charter to enforce new activities in underresourced fields or to reduce potential redundancy. On the
other hand, facilitating international collaboration may be
a way to address thinly covered topics. After much discussion, it was decided that the contribution of the
IPWGN would be in identifying mechanisms specifically
dedicated to fund interregional research between the three
regions.
Finally, the outcome of this work had to be made
public. For the last few years, this has been reported
annually at the INC conference and further dissemination
activities are expected in the future.
II I. IDENTI FYING MAJ OR
RESEARCH DRIVERS
The definition of major drivers whose research results
could provide order of magnitude improvement in information processing beyond that attainable with ultimately
scaled CMOS is not obtained by only considering the list of
the many disparate new approaches proposed in the literature. It requires an in-depth analysis of the key limitations
of the present scaling approach and to reword them as
scientific challenges that could drive the academic
research.
In that respect, the United States performed a pioneering work in identifying a critical need to develop a
Bnew logic switch[ able to replace the current CMOSbased gate and in formalizing 13 Bresearch vectors[ (see
Table 1) which form the heart of the Nanoelectronics
Research Initiative (NRI) [2].
These research vectors were condensed into six Bfundamental guiding principles[ for Bbeyond CMOS information processing[ in the later versions of the ITRS/ERD
(see Table 2).
To complement this focus on a digital switch, other
directions were considered by the IPWGN as worthwhile
for mapping the research effort.
/ Memory. It was later decided to merge the research
projects on a Bnew switch[ and on memories in a
single category called Bcomputation and storage.[
/ System–architecture–device interaction (including
the Bsystem ability[3 [3], [4] of emerging research
devices, new architectures with conventional
3
The Bsystem ability[ of an emerging device means its ability to be
integrated into functional systems. This concept was proposed by H. de Man
and detailed in a report from the MEDEA+ Scientific Committee.
Vol. 98, No. 12, December 2010 | Proceedings of the IEEE
1995
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
devices, self-learning circuits, fault tolerant architectures, etc.). It should be stressed that in the case
of emerging architectures the methodology to
derive suitable drivers is still in infancy and could
be a field of enhanced activity in the future.
/ More-than-Moore devices (i.e., sensing, actuating
the outside world, and powering the system). The
concept of BMore than Moore,[ initially proposed
by Europe and first introduced in the 2005 ITRS
roadmap, has been further refined since. It covers
the Bincorporation into devices of functionalities
that do not necessarily scale according to BMoore’s
law,[ but provide additional value to the end customer in different ways. The BMore-than-Moore[
approach allows for the nondigital functionalities
[e.g., radio-frequency (RF) communication, power
control, passive components, sensors, actuators] to
migrate from the system board level into the
package (SiP) or onto the chip (SoC).[ In short,
BMore-than-Moore[ covers all the added functionalities aimed at interacting with the outside world
(sensing and actuating) and at powering the
system.
From that initial analysis, the IPWGN derived two
main domains for collecting information on research
programs: Bcomputation and storage[ and BMore-thanMoore devices[ (see Table 3).
/ In the first domain, the Bguiding principles[ of
the ITRS/ERD are selected as main research
drivers. To be in line with the full spectrum of
devices covered by the ITRS/ERD, an additional
research direction on B0D/1D/2D charge-based
extended CMOS devices[ was added in order to
cover the shorter-term research on emerging research devices. In the same way, projects on
emerging architectures are surveyed under the
heading Barchitectures.[
/ The BMore-than-Moore[ domain was tentatively
divided along Bmaterials and devices,[ Bmanufacturing techniques,[ and Barchitecture[ research
directions. It soon became apparent that technology, device, and application are often strongly
intertwined in a single project making the proposed
classification less relevant. For the time being, this
domain was thus left undivided in the IPWGN
survey.
I V. MAPS AND GAPS IN PUBLICLY
FUNDED RE SEARCH
Having defined the technical domain to be covered and the
research vectors onto which they should be mapped, the
IPWGN started collecting data. For an adequate granularity of the survey it was decided to select R&D programs of a
significant size (typically more than US$ 1 M/yr./program)
and to collect information allowing a deeper analysis
(e.g., funding agency, lead and participating organizations,
website, projects funded within the identified programs,
etc.). It was also decided to collect only publicly available
data on programs supported by public authorities: major
institutions (centers, laboratories, universities, etc.),
research supported by private companies, networks of
excellence centers, and research infrastructures are significant contributors to the nanoelectronics research. However, data are often not publicly available and including
them would have introduced too many biases in the survey.
Even by limiting the scope of the data collection a few
issues and shortcomings were identified.
• Some programs are broader than the targeted field
(e.g., ICT or nanotechnology programs) and need a
more in-depth analysis. In most cases, a nanoelectronics program covers most if not all the
research guiding principles and a project-perproject analysis is needed to map the effort onto
the defined research drivers.
• The coverage is still far from exhaustive. Most of
the major regional programs are rapidly identified.
On the other hand, local initiatives can be easily
overlooked; that is especially true in Europe where
a significant part of the public funding is provided
at the national or local level.
• The More-than-Moore domain is a less chartered
field especially when looking at disruptive approaches and emerging devices; it is likely that
significant projects may have been overlooked.
However, this limited exercise made by the IPWGN
brought some interesting interim conclusions for each
region.
Table 3 Major Research Directions Selected by the IPWGN to Collect Information on Research Programs Whose Results Could Lead to Order of
Magnitude Improvement in Information Processing Beyond That Attainable With Ultimately Scaled CMOS
1996
Proceedings of the IEEE | Vol. 98, No. 12, December 2010
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
Fig. 1. In nanoelectronics projects funded at the European level there
is a strong focus on nanodevices and related fabrication techniques
and on emerging architectures while the other nanoelectronics
research drivers seem to be underrepresented.
A. Europe
Data on programs funded by the European Commission
(EC) are easy to access: the information is publicly
available through the EC website [5] and most often it links
to a specific website for each project. With respect to the
topics covered by the IPWGN, three major programs are
funding research on advanced nanoelectronics.
/ Future and Emerging Technologies (FET) [6]
addresses the disruptive approaches to nanoelectronics. Projects are of significant size (few Meuros
mostly for three years) and can be supported either
through a top-down policy-driven scheme on
visionary and challenging long-term predefined
goals (FET-proactive) or through a bottom-up open
scheme of continuous submission (FET-open).
/ The more classical nanoelectronics program [7]
targets primarily research on extended CMOS.
/ The NMP program on nanosciences, nanotechnologies, materials, and new production technologies
[8] covers a much broader field with some projects
relevant to nanoelectronics.
In addition, projects can be cofunded between different
European Member States. Of relevance to the IPWGN
work is the European Science Foundation [9], which facilitates cross-border research activities, e.g., on nanoscale
phenomena affecting electron transport (FoNE), on selforganized nanostructures (SONS), or on graphene (EuroGRAPHENE).
In mapping these programs onto the selected research
drivers in nanoelectronics, one can get an idea of the
respective efforts in the different fields (see Fig. 1): the
R&D intensity is estimated through the number of major
projects addressing the selected topics. One observes a
strong focus on nanodevices and related fabrication techniques and on emerging architectures while the research
oriented towards noise mitigation (out-of-equilibrium
computation), interconnections (energy transfer), and
thermal management seems to be underrepresented.
With respect to the More-than-Moore domain, the low
R&D intensity observed is probably due to an observational
bias related to the present methodology of the survey and
to the program sampling used.
Many more projects/programs are funded at the
national level. Owing to the complexity and diversity of
the funding schemes in and between the different
European countries and owing to the fact that some information is not available in English, the corresponding
mapping proved to be more difficult and it is still in
progress. However, the IPWGN tends to think that the
conclusions drawn from European programs can be extrapolated to the national programs.
B. Japan
All the identified programs are funded by the Japanese
Government. Most of the basic research is funded through
the Ministry of Education, Culture, Sports, Science and
Technology (MEXT) or the New Energy and Industrial
Technology Development Organization [NEDO [10] under
the umbrella of the Ministry of Economy, Trade and
Industry (METI)]. NEDO is also contributing to industryoriented programs like Millennium Research for Advanced
Information Technology (MIRAI) [11].
Mapping these programs onto the selected research
drivers in nanoelectronics (see Fig. 2), the same trend is
Fig. 2. In nanoelectronics projects funded by the Japanese
Government there is a strong activity on nanodevices and related
fabrication techniques, on emerging architectures and on
More-than-Moore advanced research at the expense of the other
nanoelectronics research drivers.
Vol. 98, No. 12, December 2010 | Proceedings of the IEEE
1997
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
observed as for Europe with a strong focus on nanodevices
and related fabrication techniques and on emerging architectures, while the research on out-of-equilibrium computation, energy transfer (i.e., interconnect), and thermal
management is not significantly covered. The More-thanMoore domain is addressed notably through a NEDO
program on 3-D integration named Bdream chip.[
C. The United States
In the United States, there are major programs supported either locally by the state, local authorities and
industry, or at the national level.
The first category includes two major programs driven
by the Semiconductor Research Corporation (SRC): the
Focus Center Research Program (FCRP) [12] cofunded by
SRC and the Defense Advanced Research Projects Agency
(DARPA) and focusing on ultimate CMOS and beyond,
and the Nanoelectronics Research Initiative (NRI) [13]
cofunded by SRC, the National Science Foundation
(NSF), the National Institute of Science and Technology
(NIST), and several state governments (California, New
York, Texas, and Indiana). The NRI program addresses the
quest for a new logic switch.
At the national level, the NSF through the National
Nanotechnology Initiative (NNI) [14], the national laboratories of the Department of Energy, NIST, and the
Department of Defense have major programs for the future
nanoelectronics.
The topical map of these programs (see Fig. 3)
outlines a strong focus on nanodevices, energy transfer
(interconnect), and advanced architectures, while out-of-
equilibrium computation, thermal management, and
disruptive manufacturing attract less attention.
The More-than-Moore domain is mostly addressed
through universities and state programs, while national
programs focus on materials and nanoscale measurement
techniques that will have a significant application in Morethan-Moore.
D. Interim Conclusion on Research Gaps
Building interregional comparison of the main topics
addressed by the nanoelectronics community may be premature and misleading owing the different funding mechanisms and program managements in the different regions
and the incompleteness of the survey.
It is however probably fair to draw the following
interim conclusions:
/ extending CMOS to its limits and finding disruptive logic switches and memories represent a strong
research activity worldwide;
/ there is a growing interest to address new computation paradigms at the architectural level, looking
at the applicability of disruptive devices in actual
systems (Bsystem ability[) and at new architectures
(e.g., non-Boolean or biomimetic approaches);
/ mapping the research effort for the More-thanMoore domain is far from being comprehensive
enough and it is still a work in progress;
/ out-of-equilibrium computation and research on
phonon engineering/advanced thermal management seem to be less attractive themes for the
research community, at least in terms of publicly
funded programs.
As a final word of caution, we have to stress that this
mapping exercise represents a snapshot of the programs in
three regions by the end of 2008. New programs may
emerge altering significantly this instantaneous picture.
V. FUNDING SOURCE S FOR
INTERREGIONAL COLLABORATIONS
Fig. 3. In the United States, the nanoelectronics programs are funded
either at the national level, locally by states, and/or by the industry.
Main focus is on devices, information transfer, architecture, and
More-than-Moore, while nonequilibrium devices, thermal
management, and disruptive manufacturing attract less attention.
1998
Establishing new information processing paradigms is a
huge research challenge: no single country or region is
expected to provide alone a conclusive answer to this demanding question within the next decade or so. As the
resources of a single region may not be enough, international cooperation could be a way forward.
At first, the IPWGN group expected to identify and to
outline specific research themes where an international
collaboration would accelerate the nanoelectronics research, close research gaps, and/or potentially reduce
overlaps. Ideally, it would have also suggested research
entities that could play a significant role in this process.
This ambitious goal proved to be inadequate: on the one
hand, this activity would have required an extensive effort
well beyond the resources of the small IPWGN group, and
more important, the group as a whole was not entitled by
Proceedings of the IEEE | Vol. 98, No. 12, December 2010
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
the research stakeholders to push cooperation between
specific teams and/or on specific topics.
On the other hand, identifying best practices and surveying the different regional funding mechanisms facilitating interregional collaboration is a useful exercise
benefiting to the whole nanoelectronics community and
within reach of the IPWGN.
A. Collaboration Tools
International collaboration between research teams is
not new: since science exists, researchers have sought and
exchanged ideas and results with foreign colleagues. The
Engineering and Physical Sciences Research Council in
United Kingdom estimates that 13% of its current research
grants involve an international collaborator and that
around a quarter of the publications resulting from its
funding has an international coauthor. However, in most
cases, this results from personal links between researchers
and it does not imply a coordinated funding scheme between the different countries or funding agencies involved
in the research and/or publication.
There are many different tools available for international collaboration at the regional, national, and local
levels. Many of them are facilitating the mobility of Ph.D.’s,
postdoctorals, and researchers between different countries.
Less common are dedicated mechanisms allowing teams to
be funded simultaneously in different regions for a collaborative research effort: this latter area was explored by
the IPWGN.
1) Europe: There are dedicated calls from national
funding agencies or from the EC encouraging/targeting
international collaboration. Most often they are directed towards a specific foreign country and additional
funds may be available for allowing this transregional
collaboration.
At the national level, the vast majority of funding tools
favors joint projects with other European Member States
and/or with Associated Countries. In some cases, bilateral
agreements between funding agencies of European countries, Japan, and/or the United States enable a cofunding
mechanism of international teams (see Table 4).
As a general rule, funds will support research activities
only in the country/region providing the support. A call is
issued by the respective regional agencies encouraging international collaboration or cooperation with specific
countries. The evaluation and selection is made by the
national agency according to its own rules, timeline, and
selection criteria: when the teams of the different countries get their grants accepted, the international collaboration can start effectively. Decoupling the selection
procedure prevents a lengthy and difficult alignment between the different funding agencies. Furthermore, it may
ease the discussion on Intellectual Property Rights.
At the European level, non-European partners can
participate in a project funded by the EC; moreover, the
non-European partner can exceptionally be funded by EC
for its research activity if it brings a unique expertise in the
project [15].
Table 4 Bilateral Agreements Between European Funding Agencies or Academic Institutions on One Side and Japan and/or the United States
on the Other Side Enable a Cofunding Mechanism of International Teams, Each Local Team Being Funded by Its Respective Local Authorities.
Some of These Agencies and Institutions Which Contracted Such Bilateral Agreements Are Listed in This Table
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1999
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
2) Japan: International collaboration is facilitated
mostly through two entities: the Japan Society for Promotion of Science (JSPS) and the Japan Science and Technology Agency (JST).
Following various intergovernmental agreements, the
JST implements, in collaboration with its foreign counterpart organizations, cooperative research of relatively
small scale on specific research areas under the guidance
of the Japanese Ministry of Education, Culture, Sports,
Science and Technology (MEXT) [16].
JSPS is an independent administrative institution, established by way of a national law for the purpose of contributing to the advancement of science in all fields of the
natural and social sciences and the humanities. JSPS plays a
pivotal role in the administration of a wide spectrum of
Japan’s scientific and academic programs. JSPS’s operation
is supported in large part by annual subsidies from the
Japanese Government. Its main functions include promoting international scientific cooperation. Besides specific
bilateral programs between Japan and foreign countries
[17], the JSPS Core-to-Core Program [18] is conducted with
the purpose of building and expanding a cooperative
international framework among universities and research
institutions in Japan and, among others, the United States
and many European countries: foreign institutions are
required to secure project funding for their own activities.
Other governmental organizations, such as the New
Energy and Industrial Development Organization (NEDO)
Grant for Industrial Technology Research [10], offer grants
for international collaboration. The National Institutes
for Materials Sciences (NIMS) is also involved in joint
research in the field of material science [19]: any NIMSbased research unit can agree to collaborate on research
for a specific subject with an international research organization under a Memorandum of Understanding
(MOU).
3) The United States: The NSF, through its Office of
International Science and Engineering (OISE) provides a
Partnership program for International Research and
Education (PIRE) [20]. This program supports bold,
forward-looking research whose successful outcome results from all partners, the United States and foreign,
providing unique contributions to the research endeavour.
More than 30 projects were awarded and the funding
ranges from few tens of thousands to near three millions of
US dollars. Either new proposals including international
components or projects already supported by the NSF
requesting supplemental funding for international cooperation can be considered.
This tool is often linked to specific agreements with
foreign funding agencies (e.g., l’Agence Nationale de la
Recherche in France [21]). It should be noted that each
funding agency selects the funded projects according to its
own schedule and rules avoiding a difficult synchronization and alignment in the selection criteria.
2000
The Air Force Office of Scientific Research through its
International Office also offers research grants to provide
seed money for promising research conducted outside the
United States [22].
B. Specific Examples of Interregional Collaboration
This paper will not focus on spontaneous collaboration
between research teams worldwide. Our aim is to outline
some examples of transregional collaboration in advanced
nanoelectronic/nanotechnology research resulting from a
coordinated policy of funding agencies in the three
regions.
1) Health and Environmental Impact of Nanoparticles: A
common worldwide concern is the risk incurred in using
engineered nanoparticles and their impact on health and
the environment: this was early identified as a possible
field of transregional collaboration. Addressing this need
for international discussions the International Council on
Nanotechnology (ICON) was founded in 2004 as an extension of the U.S. NSF Center for Biological and Environmental Nanotechnology (CBEN) at Rice University,
Houston, TX [23]. It is composed of individuals from academia, industry, government, and nongovernmental organizations from France, Japan, The Netherlands,
Switzerland, Taiwan, the United Kingdom, and the United
States and it explores, among other activities, health and
environmental risk issues in nanotechnology. This was one
of the many forums which helped, along with international
conferences held in the three regions, to set the scene for
coordinated funding on this topic across regions.
On December 22, 2006, the EC launched a first call of
the NMP Program (NMP-2007-1.3-2): cooperation with
the United States research teams was strongly recommended, possibly through a balanced EU–USA participation in each project. U.S. Agencies (EPA, NSF, and DOE)
launched on May 21, 2007 a joint research solicitation
indicating that the United States researchers are encouraged to collaborate with European researchers. Two European projects (NANOMMUNE [24] and NANORETOX
[25]) were started in 2008 with the active participation
of European and American partners. A third project
(NEURONANO [26]) started in 2009 involving Europe,
Japan, and the United States.
A second call (NMP-2008-1.3-2) was launched by the
EC on the same topic on November 30, 2007: it recommended again an international cooperation, possibly
through participation of interested partners all over the
world. Two out of the five selected project involve U.S.
partners (ENPRA [27] and INLIVETOX). A third call was
launched in 2009 by EC (NMP-2010-EU-USA) and U.S.
agencies (EPA, NSF, USDA and NIOSH) on the same topic
and further projects should be awarded soon.
Capitalizing on this international collaboration, an
International Alliance for NanoEHS Harmonization
(IANH) was launched on September 9, 2008, seeking to
Proceedings of the IEEE | Vol. 98, No. 12, December 2010
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
establish reproducible approaches for the study of
nanoparticle hazards [28].
2) European Projects Involving Non-European Partners: As
already mentioned, the EC allows non-European partners
to participate in projects where they bring a specific added
value. There are many examples in different fields. Looking
more specifically on the field of information processing, the
HIP project [29] brings together European groups with
researchers located in Japan and Australia: it addresses the
problem of scaling quantum processors by building elementary hybrid atom–photon devices and integrating them on
scalable platforms.
Another project, named Atomic Quantum Technologies (AQUTE), has just begun and addresses atomic
quantum computing and technologies: led by the
University of Ulm, it involves partners from the United
States, Australia, Singapore, along with many European
groups.
Compared to the preceding Framework Program
(FP6), the present European program (FP7) shows clearly
more examples of international cooperation especially in
long-term research conducted within the frame of the
Future and Emerging Technology scheme [30].
3) JST: JST also shows many examples of international cooperation through its Basic Research Program/
International Cooperative Research Projects (JST/ICORP
[31]) where the funding is secured by each research team in
its country. In the field of information processing, the
Quantum Spin Information Project [32] supervised by
Prof. S. Tarucha (University of Tokyo, Tokyo, Japan)
involves complementary expertise from Japanese research
groups, from the Delft University of Technology, Delft,
The Netherlands (Prof. L. P. Kouwenhoven), and from
the University of Basel, Basel, Switzerland (Prof. D. Loss).
In exploring spin-based quantum information technologies in confined systems, they expect to provide dramatic evolution of information security and processing
systems.
In the recently completed Computational Brain project
[33] aiming at humanoid robots that acquire skilful human
behaviors, the Japanese Advanced Telecommunications
Research Institute (cognition, neuroscience, psychology,
and computational theories of behavioral acquisition)
cooperated with the Carnegie Mellon University, Pittsburgh, PA (robot hardware and verification of the
computational theories) bringing complementary expertise in a common research goal.
4) NSF/OISE: Only few examples of the NSF/OISE/
PIRE mechanism relate to the nanoelectronics domain.
BThe spin triangle[ [34] associates researchers from the
Ohio University, Columbus (nanospintronics and nanomagnetism), from University of Hamburg, Hamburg,
Germany (spin-polarized scanning probe microscopy),
and from groups in Buenos Aires, Argentina (ab initio
calculations). The scientific goals of the collaboration
include the control and manipulation of the electron spin
for novel device functionalities and the understanding of
spin behavior at the nanoscale level. Besides the scientific
cooperation capitalizing on the complementary skills of
the three groups, a significant training component is
included in the program.
These examples show some factors of success in
cofunded international collaboration:
1) the selected topic should be perceived as a
priority for all the involved countries or funding
agencies;
2) a targeted call encourages the international
participation;
3) some major players in the field drive the individual projects;
4) the cooperation should engage few groups with
complementary skills.
They also show that, once successfully started,
transregional cooperation induces its own virtuous circle
leading to new international initiatives in the same field.
VI . CONCLUSION AND PERSPECTIVES
The mapping exercise performed by the IPWGN is useful
to obtain a glimpse of the ongoing long-term research in
nanoelectronics. The quality of the picture should however
not be overestimated: the survey is far from complete even
for publicly funded projects and programs. Furthermore,
significant contributors to the progress of nanoelectronics
are not taken into account, including major public and
private institutions, networks, and infrastructures supporting this research. Further work is needed to get a
better view of the real effort in the different research
directions.
The definition of scientific challenges that should drive
the R&D activity for further progress in nanoelectronics
needs also further refinement. While the NRI research
vectors give some perspective on the long-term research
needs in computing devices the same structuring effort
should be pursued for memories, for the disruptive architectures in information processing, and in the More-thanMoore domain.
Mapping the ongoing programs and projects onto those
research directions gives already some ideas where there is
a strong combined effort worldwide (namely, in new
devices, architectures, and manufacturing methods), while
some domains clearly attract less attention (namely,
information transfer, thermal management, and out-ofequilibrium computing). The very limited number of
identified funded projects on Bout-of-equilibrium computing[ calls for a stimulation of innovative ideas and for
dedicated funding to support research in this area. There
is finally some doubt that the coverage of the present
survey faithfully represents the effort on disruptive
Vol. 98, No. 12, December 2010 | Proceedings of the IEEE
2001
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
More-than-Moore devices and architectures: more work
is needed in that direction.
The description of potential funding sources for
international collaboration may help in improving the
synergy in the well-covered domains and in stimulating
worldwide efforts in field attracting less attention. It is
expected that advertising some success stories and making
the scientific community aware of further funding
opportunities will benefit all the stakeholders in nanoelectronics research.
Improving the present outcome of the IPWGN will not
come only from the small international group which
produced these results. In making the raw data available
very soon on a public website [35], the participants to the
IPWGN expect to improve the quality and quantity of
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The authors would like to thank H. Akinaga, Y. Awano,
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Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
ABOUT THE AUTHORS
Michel Brillouët (Member, IEEE) graduated from
Ecole Polytechnique, Paris, France, in 1974 and
Télécom, Paris, France, in 1976.
Currently, he is a Senior Advisor at CEA-LETI,
Grenoble Cedex, France. He is strongly involved in
the shaping of the European Research Area in
nanoelectronics [European Nanoelectronics Initiative Advisory Council (ENIAC), Cluster for Application and Technology Research in Europe in
NanoElectronics (CATRENE), European Semiconductor Industry Association (ESIA), etc.] and in different international
bodies [including the International Technology Roadmap for Semiconductors (ITRS) and International Planning Working Group for Nanoelectronics (IPWGN)]. He joined CEA-LETI in 1999 where he managed an R&D
Division on silicon microsystems and from 2001 also on silicon
microelectronics. Prior to joining CEA-LETI, he worked for 23 years in
Centre National des Télécommunications (CNET; France Telecom R&D
Center), where he held different positions in microelectronics research,
starting with interconnect developments and materials research, and
moving to lithography and CMOS process integration and as deputy
manager of CNET’s Pilot Line. In 1992, he was assigned to the Common
R&D Center between STMicroelectronics and France Télécom, Crolles,
France, as Process Development Division Manager and then Technology
Director. He was in charge of all the technology R&D programs for the
Crolles site, including CMOS, eDRAM and BiCMOS process, and process
integration. He has authored many technical publications and invited
talks in major conferences, including the International Electron Devices
Meeting (IEDM), the International Interconnect Technology Conference
(IITC), etc.
George I. Bourianoff (Member, IEEE) received the
B.S., M.S., and Ph.D. degrees in physics from the
University of Texas at Austin, Austin, in 1965, 1967,
and 1969, respectively.
Currently, he is a Senior Program Manager
for Emerging Research Technologies, Intel, Corporation, Austin, TX. He is responsible for managing the Intel-sponsored research programs at
64 universities around the world relating to
semiconductor technology. He also serves as an
Intel representative on the scientific advisory boards of the Nanoelectronic Research Initiative and the Focused Center Research Programs.
Prior to joining Intel, he worked at the DOE-sponsored Superconducting
Supercollidier Project in Texas. He was the group leader responsible for
simulation of the entire accelerator complex. Since joining Intel in 1994,
he has focused on beyond CMOS areas such as nanomagnetics,
optoelectronics, and alternative computational devices.
Dr. Bourianoff is a coeditor of the Emerging Research Device (ERD)
group of the International Technology Roadmap for Silicon (ITRS) and
serves as Chairman of the International Planning Working Group for
Nanoelectronics. He serves on Advisory Boards of numerous institutions
including Massachusetts Institute of Technology (MIT), Stanford University, Harvard University, University of California in Los Angeles, University of Texas, Rice University, Georgia Institute of Technology. He has
published extensively on beyond CMOS devices, applications, and
technology. He is a member of the American Physical Society.
Ralph Keary Cavin, III (Life Fellow, IEEE) received
the B.S.E.E. and M.S.E.E. degrees from Mississippi
State University, Starkville, in 1961 and 1962, respectively, and the Ph.D. degree in electrical
engineering from Auburn University, Auburn, AL,
in 1968.
He was a Senior Engineer at the MartinMarietta Company, Orlando, FL, from 1962 to
1965. In 1968, he joined the faculty of the
Department of Electrical Engineering, Texas A&M
University obtaining the rank of Full Professor. In 1983, he joined the
Semiconductor Research Corporation, Research Triangle, Park, NC, as
Director of Design Sciences. He became Head of the Department of
Electrical and Computer Engineering from 1989 to 1994 and Dean of
Engineering at North Carolina State University from 1994 to 1995. He
served as the Semiconductor Research Corporation Vice President for
Research Operations from 1996 to 2007 and is currently the SRC Chief
Scientist. His technical interests span very large scale integration (VLSI)
design, advanced information processing technologies, semiconductor
device and technology limits, and control and signal processing. He has
authored or coauthored over 100 refereed technical papers and
contributions to books. He has served as an advisor to a number of
government, industrial, and academic institutions.
Toshiro Hiramoto (Member, IEEE) received the
B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo,
Japan, in 1984, 1986, and 1989, respectively.
In 1989, he joined the Device Development
Center, Hitachi Ltd., Ome, Japan, where he was
engaged in the device and circuit design of
ultrafast BiCMOS SRAMs. In 1994, he joined the
Institute of Industrial Science, University of Tokyo,
Japan, as an Associate Professor and has been a
Professor since 2002. His research interests include low-power CMOS
devices design, variability, silicon nanowire transistors, and silicon single
electron transistors.
Dr. Hiramoto is a member of the Institute of Electronics, Information
and Communication Engineers (IEICE) and Japan Society of Applied
Physics. He was an Elected AdCom Member of the IEEE Electron Devices
Society from 2001 to 2006. He served as the General Chair of Silicon
Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999,
and 2001. He has served on Program Committee of Symposium on Very
Large Scale Integration (VLSI) Technology since 2001. He also served on
Program Subcommittee on CMOS Devices of the International Electron
Devices Meeting (IEDM) in 2003 and 2004. He was the Subcommittee
Chair of CMOS Devices in 2005, the Asian Arrangement Co-Chair in 2006
and 2007, the Publications Chair in 2008, and the Emerging Technologies
Chair of IEDM in 2009.
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2003
Brillouët et al.: Regional, National, and International Nanoelectronics Research Programs
James A. Hutchby (Life Fellow, IEEE) received the
B.S. degree in electrical engineering from Auburn
University, Auburn, AL, in 1964 and the M.S. and
Ph.D. degrees in electrical engineering, in 1966 and
1969, respectively.
Currently, he is a Senior Scientist and formerly
was Director of Device Sciences with the Semiconductor Research Corporation, Research Triangle, Park, NC. He founded and chairs the Emerging
Research Device (ERD) Working Group for the
International Technology Roadmap for Semiconductors (ITRS). Prior to
joining SRC, he was the Director of the Research Triangle Institute’s
Center for Semiconductor Research. He has published over 140
contributed and invited papers in scientific journals and conferences.
His research encompassed ion implantation in III-V and II-VI semiconductors; modeling, growth and fabrication of high efficiency III-V
multijunction cascade solar cells; modeling and fabrication of complementary high-speed III-V heterojunction bipolar transistors circuits; and
optoelectronic devices including optoelectronic integrated circuits.
Dr. Hutchby chaired the IEEE Reynold B. Johnson Data Storage Device
Technology Award Committee and the IEEE Electron Devices Society’s
Very Large Scale Integration (VLSI) Technology and Circuits Committee.
He was General Chair of the IEEE International Electron Devices Meeting
(IEDM), the IEEE Gallium Arsenide Integrated Circuit Symposium (now
Compound Semiconductor Integrated Circuit Symposium), and the
Workshop on Compound Semiconductor Materials and Devices. He also
chaired the Duke University Electrical and Computer Engineering’s
Industry Advisory Panel. He is a recipient of the IEEE Third Millennium
Medal.
Adrian M. Ionescu (Senior Member, IEEE) received the B.S./M.S. degrees in microelectronics
from the Polytechnic Institute of Bucharest,
Bucharest, Romania, in 1989 and the Ph.D. degree
in physics of semiconductors from the National
Polytechnic Institute of Grenoble, Grenoble,
France, in 1997.
Currently, he is an Associate Professor at the
Ecole Polytechnique Fédérale de Lausanne (EPFL),
Lausanne, Switzerland. He held staff and/or
visiting positions at LETI-Commissariat à l’Énergie Atomique, Grenoble,
CNRS, Grenoble, and Stanford University, Stanford, CA, in 1998 and 1999.
2004
He is currently the Director of the Nanoelectronic Devices Laboratory and
Director of the Doctoral School of Microsystems and Microelectronics of
EPFL. He has published more than 200 papers in international journals
and conference proceedings.
Prof. Ionescu was the recipient of three Best Paper Awards at
international conferences and of the Annual Award of the Romanian
Academy of Sciences in 1994. He served on the International Symposium
on Quality Electronic Design and International Electron Devices Meeting
technical committees in 2003/2004 and 2008/2009 and as Technical
Program Committee Chair of the European Solid-State Device Research
Conference in 2006. He is a member of the Scientific Committee of the
Cluster for Application and Technology Research in Europe on Nanoelectronics (CATRENE) and the academic representative of Switzerland to
the European Nanoelectronics Initiative Advisory Council (ENIAC).
Ken Uchida (Member, IEEE) received the B.S.
degree in physics and the M.S. and Ph.D. degrees
in applied physics from the University of Tokyo,
Tokyo, Japan, in 1993, 1995, and 2002, respectively.
In 1995, he joined the Research and Development Center, Toshiba Corporation, Kawasaki,
Japan. Currently, he is an Associate Professor at
Tokyo Institute of Technology, Tokyo, Japan. He
has studied carrier transport in nanoscale devices
such as single-electron devices, Schottky source/drain MOSFETs, ultrathin-body SOI MOSFETs, strained silicon MOSFETs, carbon sanotube
transistors, and (110) Si MOSFETs.
Dr. Uchida is a member of the Japan Society of Applied Physics and
IEEE Electron Devices Society (EDS). He won the 2003 IEEE EDS Paul
Rappaport Award. He served as a Subcommittee Member as well as the
Subcommittee Chair of the IEEE International Electron Devices Meeting
(IEDM) from 2005 to 2007. He was a Program Committee Member of
many international conferences such as the IEEE Silicon Nanoelectronics
Workshop (SNW) in 2003, 2005, 2006, 2007, 2008, and 2009, the International Conference on Solid-State Devices and Materials (SSDM) in
2009, and European Solid-State Device Research Conference (ESSDERC)
in 2008 and 2009. He was a Distinguished Lecturer of the IEEE SolidState Circuit Society (SSCS) in 2007 and 2008.
Proceedings of the IEEE | Vol. 98, No. 12, December 2010