WM2000 - Mouser Electronics

w WM2000

Handset Receiver Speaker Driver with Ambient Noise

Cancellation

DESCRIPTION FEATURES

The WM2000 is a low power, high quality handset receiver speaker driver with ambient noise cancellation. Together with well designed handset acoustics, it provides enhanced voice communication quality in a noisy environment.



Wolfson Ambient Noise Cancellation (ANC)

- Wide noise cancellation bandwidth (300Hz-2.5kHz)

- 20dB typical ambient noise reduction (with welldesigned acoustics)

- Dynamic control algorithm copes with extremes of ambient noise

The device integrates into the handset output signal path with minimal architectural changes. WM2000 drives the receiver directly.

The Wolfson ANC (Ambient Noise Cancellation) Engine uses an adaptive filtering algorithm which requires only one or a pair of dedicated analogue microphones. The filtering algorithm can be adapted to the handset's acoustic characteristics for optimum noise cancellation performance. A dynamic control algorithm adjusts ANC parameters for variations in ambient noise levels.



Handset Receiver Speaker driver

- -79dB THD at 31mW into 32



- -68dB THD at 80mW into 16





Two

- Differential Microphone input for ambient noise

- Differential or single-ended Line input for received voice

High power supply rejection allows WM2000 to operate in a noisy electrical environment without degradation of signal quality. The device is controlled via registers which can be accessed using a 2-wire serial control interface. A preconfigured Internal Sequencer controls the internal hardware such that a single register write can be used to perform key analogue sequences during power up / power down or mode transition.



Low power consumption

- 20mW added to voice call when noise cancellation enabled

- 68



W standby power



CSP25 package, -40



C to +85



C temperature range



APPLICATIONS

BLOCK DIAGRAM

SPKVDD

RECEIVED

VOICE

INPUT

1uF

LINN

LINP

1uF

AMBIENT

NOISE

MICS

1uF

MICN

MICP

MICBIAS

-

+

LINEPGA

LINE

ADC

AMBIENT NOISE

CANCELLATION

ENGINE

ANC

DAC

SPKVDD

+

-

-

+

MICPGA

250k 250k

MIC

ADC

V

REF

AVDD

SYSCLK

SPKVDD

LDO

REF

DCVDD

/2

+

WM2000

INTERNAL

SEQUENCER

CONTROL

INTERFACE

SPKN

SPKP

SPKGND

GPIO

16-32R speaker

1uF

WOLFSON MICROELECTRONICS plc Production Data, July 2012, Rev 4.1

Copyright



2012 Wolfson Microelectronics plc

WM2000

TABLE OF CONTENTS

DESCRIPTION ....................................................................................................... 1

FEATURES ............................................................................................................ 1

APPLICATIONS ..................................................................................................... 1

BLOCK DIAGRAM ................................................................................................ 1

TABLE OF CONTENTS ......................................................................................... 2

PIN CONFIGURATION .......................................................................................... 3

ORDERING INFORMATION .................................................................................. 3

PIN DESCRIPTION ................................................................................................ 4

ABSOLUTE MAXIMUM RATINGS ........................................................................ 5

RECOMMENDED OPERATING CONDITIONS ..................................................... 5

ELECTRICAL CHARACTERISTICS ..................................................................... 6

TEST TYPE ..................................................................................................................... 9

TERMINOLOGY .............................................................................................................. 9

TYPICAL POWER CONSUMPTION .................................................................... 10

SIGNAL TIMING REQUIREMENTS .................................................................... 11

MASTER CLOCK .......................................................................................................... 11

CONTROL INTERFACE ................................................................................................ 12

DEVICE DESCRIPTION ...................................................................................... 13

TYPICAL APPLICATION CONFIGURATION ................................................................ 13

ANC (AMBIENT NOISE CANCELLATION) ................................................................... 13

TYPICAL NOISE CANCELLATION PERFORMANCE .................................................. 14

AMBIENT NOISE CANCELLATION (ANC) ENGINE .................................................... 15

INPUT SIGNAL PATH ................................................................................................... 20

ANALOGUE TO DIGITAL CONVERTERS (ADC) ......................................................... 28

DIGITAL TO ANALOGUE CONVERTER (DAC) ........................................................... 29

OUTPUT SIGNAL PATH ............................................................................................... 29

OUTPUT PGA MIXER ................................................................................................... 29

BYPASS PATH .............................................................................................................. 30

SPEAKER OUTPUT ...................................................................................................... 31

LDO REGULATOR ........................................................................................................ 32

SYSTEM CLOCKING .................................................................................................... 32

GENERAL PURPOSE INPUT/OUTPUT ........................................................................ 32

CONTROL INTERFACE ................................................................................................ 34

SOFTWARE RESET AND DEVICE ID .......................................................................... 37

POWER-ON RESET (POR) .......................................................................................... 38

THERMAL SHUTDOWN ............................................................................................... 40

REGISTER MAP .................................................................................................. 41

REGISTER BITS BY ADDRESS ................................................................................... 43

APPLICATIONS INFORMATION ........................................................................ 53

SPEAKER AND MICROPHONE SELECTION .............................................................. 53

ACOUSTICS AND PLASTICS DESIGN ........................................................................ 53

RECOMMENDED EXTERNAL COMPONENTS ........................................................... 54

PACKAGE DIMENSIONS .................................................................................... 56

IMPORTANT NOTICE ......................................................................................... 57

ADDRESS ............................................................................................................ 57

REVISION HISTORY ........................................................................................... 58 w PD, July 2012, Rev 4.1

2

Production Data

PIN CONFIGURATION

WM2000

Figure 1 Pin Configuration (25 ball Chip Scale Package) - Top View

Exact dimensions of the 25 ball CSP configuration are shown under “Package Dimensions” on page 56.

ORDERING INFORMATION

DEVICE

TEMPERATURE

RANGE

WM2000ECS/RV -40 o

C to +85 o

C

PACKAGE

CSP25

(Pb-free, tape and reel)

MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING

TEMPERATURE

MSL3 260 o

C

Note:

Reel quantity = 3,500 w PD, July 2012, Rev 4.1

3

WM2000

PIN DESCRIPTION

The following pins/balls are available on WM2000.

BALL NAME

A5 SCLK

TYPE

Digital Input

DESCRIPTION

2 wire control interface clock

B5

D3

SDA

DNC

C4 DNC

C5 DNC

D4 DNC

D5 DBVDD

Digital Input/Output 2 wire control interface data

Production test pins Do not connect. Wolfson internal use only.

Supply Digital buffer (I/O) supply

A2

B2

E1

A3

A4

C3

C2

A1

C1

B1

B3

B4

E5

E4

DGND

DCVDD

GPIO

ADDR

Ground

Supply

E3 AGND Ground

E2

D2

D1

VMID

LINN

LINP

MICN

MICP

SPKVDD

SPKN

SPKGND

Analogue Output

Analogue Input

Analogue Input

Analogue Input

Analogue Input

Supply

Analogue Output

Ground

SPKP

MICBIAS

Analogue Output

Analogue Output

LDO_OUT Analogue Output

SCAN_MODE Digital Input

MCLK Digital Input

Digital ground (return path for DCVDD and DBVDD)

Digital core supply

Mid rail reference decoupling pin

Received Voice (Line) inverting differential input (can be grounded for single ended configuration).

Received Voice (Line) non-inverting input (must be AC coupled for single ended configuration).

Noise Cancelling (Mic) inverting differential input

Noise Cancelling (Mic) non-inverting differential input

Supply for speaker driver and internal LDO.

Negative speaker output (connected in BTL mode)

Speaker ground (return path for SPKVDD)

Positive speaker output

Bias supply for external microphone

Voltage regulator decoupling connection.

This pin must be grounded.

Master clock

Digital Input/Output General purpose I/O pin

Digital Input 2 wire control interface device address select. Should be pulled up to

DBVDD or grounded. w PD, July 2012, Rev 4.1

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Production Data

WM2000

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30



C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30



C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30



C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

Supply voltages (SPKVDD, DBVDD)

Supply voltages (DCVDD)

Voltage range digital inputs

Voltage range analogue inputs

Operating temperature range, T

A

Storage temperature after soldering

RECOMMENDED OPERATING CONDITIONS

-0.3V +4.5V

-0.3V +2.5V

DGND - 0.3V DBVDD + 0.3V

AGND - 0.3V DCVDD + 0.25V

-40ºC +85ºC

-65ºC +150ºC

Digital supply range (Core)

Digital supply range (Buffer)

Speaker supply range

Ground DGND, AGND, SPKGND

Notes

1. Analogue and digital grounds must always be within 0.3V of each other.

0

2. All supplies are completely independent from each other (i.e. not internally connected).

V w PD, July 2012, Rev 4.1

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WM2000

ELECTRICAL CHARACTERISTICS

Test Conditions

DCVDD=DBVDD =1.8V, SPKVDD=2.8V, T

A

= +25 o

C

VMID

=1



F, C

MICBIAS

C, 1kHz differential input and output signals, PGA gains=0dB,

=1



F, unless otherwise stated. Specifications for Single-ended and Non-inverting modes apply to LINN and

LINP only.

TEST

TYPE

Analogue Inputs (LINN, LINP, MICN, MICP)

3 Full-scale input signal level Single-ended input 0.936 V

RMS

V

RMS

3 Input resistance (see note 8) Inverting mode 12.82 k



3 Inverting



MIC_VOL_SHIFT=1 or

LINE_IN_VOL_SHIFT = 1

3 Input capacitance Single-ended or differential input

Input Amplifiers (MICPGA and LINEPGA)

3

3

3

3

2

2

2

Gain minimum

Gain maximum

Bandwidth

Mute attenuation

Common mode rejection ratio

SPKVDD power supply rejection ratio

100mV pk-pk ripple,

217Hz

100mV pk-pk ripple,

10kHz

-6

+30

0

90

40 dB dB dB dB

85 dB

78 dB

Audio Performance: ANC signal path (Noise Mic Input to Speaker Output; see note 3)

3 Signal to Noise Ratio 20Hz to 10kHz

(see note 5)

87 dB

2 20Hz to 20kHz 82 dB

2 Total Harmonic Distortion 10mW, 16



load

2

2

2

Total Harmonic Distortion +


0dBFS input, 10k

217Hz



load

100mV pk-pk ripple,

100mV pk-pk ripple,

10kHz

-75

-76

-90 dB dB dB dB dB dB dB

-90 dB dB dB dB

79 dB

66 dB w PD, July 2012, Rev 4.1

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Production Data

WM2000

Test Conditions


A

= +25 o

C

VMID

=1



F, C

MICBIAS


=1




LINP only.

TEST

TYPE

Audio Performance: Bypass path (Line Input to Speaker Output; see note 4)

2 Signal to Noise Ratio 20Hz to 20kHz 97.5 dB

2

2

Total Harmonic Distortion

Total Harmonic Distortion +

10mW, 16



load

0dBFS input, 10k



load

-80

-99

-90 dB dB dB dB dB dB dB

-90 dB dB dB dB

90.5 dB 2

1

2


Signal to Noise Ratio

Total Harmonic Distortion

100mV pk-pk ripple,

217Hz

2 100mV pk-pk ripple,

10kHz

Audio Performance: Line Input to Mixer path to Speaker Output

10mW, 16



load

81 dB

-77

-80 dB dB dB dB dB

2 Total Harmonic Distortion + 10mW, 16



load -75 dB dB dB dB

2

2

SPKVDD power supply rejection ratio (see note 6)

100mV pk-pk ripple,

217Hz

100mV pk-pk ripple,

10kHz

-80 dB

83 dB

73 dB

Speaker Driver

3 DC Offset at load

3 BTL speaker load rating (see note 9)

-10

16 32 See note 10



Microphone Bias

1

1 MIC_BIAS_VSEL=1 V

2

2

2

Bias Voltage (see note 1)

Bias Current Source

Output Noise Voltage


MIC_BIAS_VSEL=0 1.9 2.0 2.1 V for V

MICBIAS

within +/-3%

20Hz to 20kHz

100mV pk-pk ripple,

217Hz

5

1.5

 mA

V

RMS

91 dB

2 100mV pk-pk ripple,

10kHz

70 dB w PD, July 2012, Rev 4.1

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WM2000

Test Conditions


A

= +25 o

C

VMID

=1



F, C

MICBIAS


=1




LINP only.

TEST

TYPE

Digital Input / Output

3

3

3

3

3

3

Input HIGH Level

Input LOW Level

Output HIGH Level

Output LOW Level

Input Capacitance

Input leakage

System Clock (MCLK) Timing

I

I

OL

OH

0.8



DBVDD V

0.2



DBVDD V

= 1mA

= -1mA

0.8



DBVDD V

0.2



DBVDD V

10 pF

1 nA

3

3

Frequency MCLK divider disabled

(see note 7)

MCLK divider enabled

(see note 7)

19 27

T

MCLKH

: T

MCLKL

60:40 40:60 3 Duty cycle

LDO Voltage Regulator

1 Output voltage (see note 1)

2 LDO accuracy with respect to (DCVDD+0.05V)

3

3

3

2

2

2

Load capacitor (external)

External capacitor ESR

External capacitor series inductance

SPKVDD PSRR (100mV pkpk ripple, 217Hz) (excluding reference) at 20mA

SPKVDD PSRR (100mV pkpk ripple, 10kHz) (excluding reference) at 20mA

DCVDD PSRR (20kHz)

0

SPKVDD = 2.8. (see note

6) nF

49 dB

40 dB

28 dB DCVDD = 1.8v (see note

6)

2.5 – 3.6V

0 – 20mA

1

2.5

%

%

2

2

Line regulation

Load regulation

Thermal Shutdown

3 T

TP_WARN

(Threshold at which

TP_WARN is set to ‘1’. See note 5) temperature rising

3 T

TP_SHUT

(Threshold at which

TP_SHUT is set to ‘1’. See note 5) temperature rising

T

TP_WARN

145 160 o o

C

C w PD, July 2012, Rev 4.1

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Production Data

WM2000

Notes:

1. Varies with (DCVDD + 0.05). These figures assume DCVDD = 1.8v.

2. Full scale input signal level, in single-ended mode, equals ((DCVDD+0.05)/2.83)+ 0.282. In differential modes, it is 2 x Single Ended.

3. ANC Path measured using fixed digital filter coefficients giving flat frequency response; No active ANC Active control algorithm; MCLK in the range 20-24.576MHz, MCLK divider is enabled.

4. Bypass Path measured with ADC, ANC Engine and DAC disabled.

5. This is guaranteed by design only.

6. Measured on COL28 evaluation package with LDO_OUT externally connected to AVDD pin.

7. For details of the MCLK Divider function, see “Signal Timing Requirements”.

8. Input impedance is not dependant on PGA gain setting.

9. The variability of speaker impedance over frequency can affect noise cancellation performance, see “Applications

Information”.

10. The actual speaker impedance must be connected across the SPKP and SPKN pins. If end of line calibration is used, an external speaker driver circuit cannot be connected between WM2000 and the speaker because this prevents WM2000 from measuring the speaker’s impedance.

TEST TYPE

Electrical characteristics have been specified in the following ways, as shown in Table 1.

TEST TYPE = 1

TEST TYPE = 2

TEST TYPE = 3

Production test limit

Limits determined by bench test and characterisation

Target specification, or guaranteed by design only

Table 1 Test Type for all Electrical Characteristics

TERMINOLOGY

1. Signal-to-Noise Ratio (dB) – SNR is the difference in level between a full scale output signal and the device output noise with no signal applied measured over a bandwidth of 20Hz to 20kHz. This ratio is also called idle channel noise.

(No Auto-zero or Automute function is employed).

2. Total Harmonic Distortion (dB) – THD is the difference in level between a 1kHz full scale sinewave output signal and the first seven harmonics of the output signal. The amplitude of the fundamental frequency of the output signal is compared to the RMS value of the next seven harmonics and expressed as a ratio.

3. Total Harmonic Distortion + Noise (dB) – THD+N is the difference in level between a 1kHz full scale sine wave output signal and all noise and distortion products in the audio band. The amplitude of the fundamental reference frequency of the output signal is compared to the RMS value of all other noise and distortion products and expressed as a ratio.

4. Channel Separation (dB) – is a measure of the coupling between left and right channels. A full scale signal is applied to the left channel only and the right channel amplitude is measured. Then a full scale signal is applied to the right channel only and the left channel amplitude is measured. The worst case channel separation is quoted as a ratio.

5. Channel Level Matching (dB) – measures the difference in gain between the left and the right channels.

6. Power Supply Rejection Ratio (dB) – PSRR is a measure of ripple attenuation between the power supply pin and an output path. With the signal path idle, a small signal sine wave is summed onto the power supply rail, The amplitude of the sine wave is measured at the output port and expressed as a ratio.

7. All performance measurements are carried out with a 20kHz low pass filter, and where noted an A-weighted filter.

Failure to use such a filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the

Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

w PD, July 2012, Rev 4.1

9

WM2000

TYPICAL POWER CONSUMPTION

The WM2000 power consumption is dependent on many parameters. Typical power consumption figures are quoted in this section for five specific operating modes. These modes are defined in the

“ANC Engine Operating Modes” section. It is important to note that entry into these modes and transitions between modes normally requires a specific sequence of actions; any deviation from the recommended sequences may result in incorrect operation and different power consumption characteristics.

Quiescent Conditions - No input signal present

Test Conditions


A

= +25 o

C, C

VMID

=1



F, C

MICBIAS

=1



F, unless otherwise stated.

No input signal present

TEST

TYPE

2 Device Ready 2.64mA 5.4



A 129



A 5.12mW

2 ANC Active

(see note 1)

Power-On Reset completed,

MCLK applied. See note 2.

MCLK = 9.5MHz,

MCLK Divider Disabled

5.42mA 4.23



A 9.26mA 35.7mW

2 7.63mA 5.71



A 9.26mA 39.7mW

2

MCLK = 13.5MHz,


MCLK = 19MHz,

MCLK Divider Enabled

5.47mA 6.98



A 9.26mA 35.8mW

2 7.69mA 9.57



A 9.26mA 39.8mW

2 Standby

MCLK = 27MHz,


Power supplies and VMID reference maintained, MCLK stopped, ANC and Internal RAM disabled

2.8



A 5.3



A 19



A 68



W

2 Bypass 22.4



A 9.1



A 4.96mA 14mW

2 Powered down

Power supplies and VMID reference maintained, MCLK applied (see note 2), ANC and

Internal RAM disabled

Power supplies and, MCLK maintained. Power-Down mode transition completed.

2.70mA 5.56



A 137



A 5.25mW

2 2.8



A 5.3



A 9.8



A 42



W Power supplies maintained,

MCLK stopped. Power-Down mode transition completed.

ANC Active conditions - Received Voice signal present (see Note 3)

Test Conditions


A

= +25 o

C, C

VMID

=1



F, C

MICBIAS

=1




Received Voice input signal 1kHz, 1V

RMS

into LINN/LINP, LINE PGA Gain +4.2dB, MCLK = 13.5MHz, MCLK Divider Disabled.

TEST

TYPE

2

2

ANC Active (see note

1)

32



speaker load

16



speaker load

7.7mA 6.77



A 32.9mA 106mW

7.7mA 5.56



A 57.8mA 176mW

Notes:

1. The ANC Active Mode measurements are made with ANC Active and based on an example ANC Engine configuration.

Actual power consumption in a real application may differ depending on ambient noise levels and handset characteristics.

2. MCLK frequency is within the limits defined in “Signal Timing Requirements”.

3. Note that power consumption figures include speaker driver power dissipation; this is normally part of the power consumed by the baseband processor or other speaker driver device.

4. For details of the MCLK Divider function, see “Signal Timing Requirements”. w PD, July 2012, Rev 4.1

10

Production Data

SIGNAL TIMING REQUIREMENTS

MASTER CLOCK

WM2000

Figure 2 Master Clock Timing

Test Conditions

DCVDD=DBVDD= 1.8V, SPKVDD=2.8V, T

A

= +25 o


C

VMID

=1



F, C

MICBIAS

=1




TEST

TYPE

MCLK Timing Information

3

3

MCLK Frequency

(to support full ANC operation and Read/Write Control

Interface functionality)

3

3

3

MCLK Frequency during device initialization - to support

Control Interface Write operations only

Duty cycle (T

MCLKH

: T

MCLKL

)




(default condition)

19

9.5

27

13.5

MHz

MHz

9.5 13.5

60:40

Table 2 Master Clock (MCLK) Timing

MCLK is the Master Clock signal applied to the WM2000. It is required by the ANC Engine and by the

Control Interface and by other internal circuits in some operating modes. The WM2000 includes a selectable ‘divide by two’ function on the MCLK input; the resultant signal is SYSCLK. The MCLK

Divider can be controlled using the register bits described in the “Ambient Noise Cancellation (ANC)

Engine” section.

When the WM2000 reaches the “Device Ready” condition following a successful Power-On Reset, the internal MCLK Divider is enabled by default. If the MCLK frequency is in the range 9.5MHz -

13.5MHz, then the Control Interface capability will be limited; Read operations will not be supported across the full range of SCLK frequencies. In this case, the MCLK Divider should be disabled as the first register write, in order to allow full Read/Write Control Interface functions and full ANC operation.

If the MCLK frequency is in the range 19MHz - 27MHz, then the MCLK Divider does not need to be adjusted from the default setting. w PD, July 2012, Rev 4.1

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WM2000

CONTROL INTERFACE

Figure 3 Control Interface Timing

The Control Interface function has a dependency on MCLK. The WM2000 includes a selectable

‘divide by two’ function on the MCLK input; the resultant signal is SYSCLK.

Test Conditions

DCVDD=DBVDD= 1.8V, SPKVDD=2.8V, T

A

= +25 o

C, unless otherwise stated.

TEST

TYPE

SCLK Timing Information

3 SCLK Frequency (50:50 duty cycle)

3

3

3

SCLK Low Pulse-Width

SCLK High Pulse-Width f

SYSCLK

* Min(t

1

and t

2

): 2-wire read (see notes 1 and 2)

Hold Time (Start Condition) t

1

1300 t

2

600 ns ns

5

3

3

3

3

Setup Time (Start Condition)

Data Setup Time

SDIN, SCLK Rise Time

SDIN, SCLK Fall Time t

3

600 t

4

600 t

5

100 t

6 t

7 ns ns ns

3

3

3

3

Setup Time (Stop Condition)

Data Hold Time

Pulse width of spikes that will be suppressed t t

8

9

600 t ps

0 ns

Table 3 Control Interface (SCLK) Timing

Notes:

1. Min(t1, t2) means the smaller of t1 and t2.

2. During power on, when the “Device ready” state is reached, the MCLK divider is enabled by default. Until the MCLK divider has been disabled, f

SYSCLK

= f

MCLK

/ 2, and both t

1

and t

2

must be greater than (5 / f

SYSCLK

) for serial interface reads. If the MCLK frequency is in the range 9.5MHz - 13.5MHz, then the MCLK Divider should be disabled as the first register write, in order to maximise the permitted SCLK frequency at non 50:50 duty cycle during reads through the Control Interface. w PD, July 2012, Rev 4.1

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Production Data

WM2000

DEVICE DESCRIPTION

TYPICAL APPLICATION CONFIGURATION

The WM2000 is designed for integration into the handset receiver output path as shown in Figure 4.

The WM2000 takes as input the signal from a Voice Codec earpiece driver, and generates an output suitable for directly driving a receiver/speaker, having applied noise cancellation to the incoming audio signal.

Figure 4 Typical Application

ANC (AMBIENT NOISE CANCELLATION)

The Ambient Noise Cancellation engine within the WM2000 improves the intelligibility of a voice call by using destructive interference to reduce the acoustic energy of the ambient sound. To do this effectively, the Host Microprocessor must configure WM2000 with a set of acoustic coefficient data that describe the properties of the acoustic components of the handset. The primary acoustic elements in the handset are the microphones and the speaker, but other components such as the plastics and the PCBs also have significant importance to the acoustic coefficient data.

As a result, the acoustic coefficient data is specific to each handset design and require to be recalculated following any change in the design of acoustic elements in the handset. Any mismatch between acoustic coefficient data and handset acoustic design can give inferior ANC performance.

This acoustic data will be designed on a handset per handset basis using Wolfson design tools.

Please contact Wolfson for more details. w PD, July 2012, Rev 4.1

13

WM2000

TYPICAL NOISE CANCELLATION PERFORMANCE

Ambient Noise Cancellation (ANC) delivers an improvement in the clarity of a speech signal in a noisy environment. The noise cancellation performance is a measure of the extent to which the external (or ambient) noise is reduced.

The noise cancellation performance of the WM2000 depends on external factors, such as microphone and loudspeaker specifications, and also the physical design of the application handset.

To obtain meaningful performance figures for a particular application, the following considerations should be noted:

1. Measurements should be made using the same microphones and loudspeaker as in the production handset, and subject to the same acoustics as in the production handset.

2. Suitable equipment must be used, and the placement of the handset and measurement microphone must be correct, to replicate the acoustical responses of the handset to the ear chamber, ear lobe, ear canal, and head.

The noise cancellation performance at a given frequency can be calculated by measuring the difference in the acoustical power entering the ear when noise cancellation is enabled compared to when noise cancellation is disabled. The performance is measured in dB, where a negative value indicates that the WM2000 is performing a cancellation and attenuation of ambient noise. Hence a high negative value (e.g. -20dB) indicates that significant noise cancellation is taking place. An example of what can be achieved with WM2000 is shown in Figure 5.

A Brüel and Kjær (B&K) Head and Torso Simulator with proprietary modifications (contact Wolfson

Microelectronics for details) has been used for the measurements shown here. The measurement microphone was positioned inside the head and torso simulator, 40cm from the noise source and at

45 degrees orientation.

It is important to note that the frequency response will vary between different handset designs. This data has been generated using a handset designed by Wolfson.

10.00

5.00

0.00

10.00

-5.00

-10.00

-15.00

-20.00

-25.00

-30.00

-35.00

100.00

1000.00

10000.00

100000.00

ANC

Frequency / Hz

Figure 5 Typical Noise Cancellation Performance w PD, July 2012, Rev 4.1

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WM2000

AMBIENT NOISE CANCELLATION (ANC) ENGINE

The ANC Engine employs digital circuitry to process the Ambient Noise (Microphone) and Received

Voice (Line) signals, which are digitized by the two Analogue to Digital Converters (ADCs). The ambient noise signal is then filtered, sent to theDAC and mixed with the received voice signal.

The process which runs in the ANC Engine and is used to dynamically control Ambient Noise

Cancellation during a voice call is known as Ambient Noise Cancellation Control or “ANC Active”.

This mode supports normal ANC operation and implements protection algorithms to avoid overdriving the loudspeaker.

The WM2000 provides a speech clarity function in ANC Active mode which maintains a pre-defined signal-to-noise ratio (SNR) between the ambient noise and the voice call speech signal. The speech clarity function monitors the Ambient Noise (microphone) and Received Voice (line) signals and adjusts the line input volume in order to control the SNR. By ramping the volume in this way, the

WM2000 provides a ‘smart’ volume adjustment without the user having to change the audio volume manually. The speech clarity function works in conjunction with the ANC and can be tailored to specific customer requirements to achieve natural and unobtrusive results.

Other operating modes permit the ANC function to be completely bypassed, or to allow power saving

(standby) operation. The WM2000 operating modes are described in the “ANC Engine Operating

Modes” section.

The Host Microprocessor must download configuration data to the WM2000 in order to precisely define the required algorithms for achieving noise cancellation in each handset unit. As described earlier, the configuration data is tailored specifically for a given handset; this consists of handset design-specific coefficients. The driver software supporting the WM2000 device exposes high level functionality to enable easy upload of data to the device.

ANC ENGINE OPERATING MODES

The ANC Engine operating modes and mode transitions are illustrated in Figure 6 and described in the following paragraphs.

Figure 6 ANC Engine Operating Modes and Transitions w PD, July 2012, Rev 4.1

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WM2000

Shutdown Mode:

This is the unpowered state of the device. From this mode, the Power-On Reset sequence will take the WM2000 into the Device Ready state. See Power-On Reset (POR) for details of this transition.

Device Ready Mode:

This is the powered-up state of the device, following successful completion of the Power-On Reset sequence. In this state, the power supplies and Master Clock (MCLK) have been applied to the

WM2000, as detailed in the Power-On Reset (POR) section.

From this mode, the WM2000 can transition to the ANC Active mode.

ANC Active Mode (Dynamic Control of ANC):

This is the mode selected when noise cancellation is requested by the Host Microprocessor (eg. when a voice call is in progress). The algorithm is an adaptive control system for ANC, and is an essential part of the algorithms relating to prevention of excessive signals being driven into the speaker. It dynamically controls the extent to which ANC operates, depending on the real-time ambient noise conditions. There are 3 key areas of operation, according to ambient noise levels:

1. At ambient noise levels, this algorithm switches ANC off , because the voice call can be clearly heard over the low ambient noise level. Disabling ANC in this situation also prevents any feeling of left-right channel imbalance, which would otherwise be caused by ambient noise entering each ear at significantly different levels.

2. At ambient noise and receiver voice levels, ANC is fully operational

3. At ambient noise levels and/or receiver voice levels, under which conditions the combination of ANC cancellation signal and voice signal would cause the output amplifier to clip or the speaker to distort, the ANC filter and gain are progressively modified in order to reduce the speaker drive power to safe levels.

The active signal paths in ANC Active mode are as illustrated in Figure 7. Note that the precise configuration of the signal path may vary between different applications. For example, the PGA input modes and gain settings will require to be tailored for the specific electrical and acoustic requirements of a given handset. w

Figure 7 ANC Mode Signal Paths

Note that the analogue circuits are always enabled in ANC Active mode, regardless of whether ANC is enabled or disabled. Hence the power consumption is similar across all ambient noise levels.

From this mode, WM2000 can transition to Shutdown, Standby or Bypass modes.

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WM2000

Standby Mode:

This is a low power operating mode of the WM2000. The power supplies must be maintained in this mode, but MCLK can be stopped, reducing power consumption. This is the mode selected when the handset is not in use for a voice call, but is ready to be re-enabled when required. In this mode, the analogue circuits and internal RAM are disabled in order to minimise the power consumption.

In Standby mode, no audio signal paths are active

From this mode, WM2000 can transition to ANC Active mode.

Bypass Mode:

This is the mode selected when a voice call is in progress, but no noise cancellation is requested by the Host Microprocessor. ANC is not enabled in this mode. This is a lower power mode than ANC

Active mode, although the power consumption of the speaker driver still represents the largest portion of the overall power consumption. In this mode, some of the analogue circuits are disabled, and the internal RAM is also disabled. The power supplies must be maintained in this mode, but MCLK can be stopped.

The active signal paths in Bypass mode are as illustrated in Figure 8.

Figure 8 Bypass Mode Signal Paths

From this mode, WM2000 can transition to ANC Active mode. w PD, July 2012, Rev 4.1

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WM2000

ANC ENGINE MODE TRANSITIONS

Transitions between ANC Engine Operating Modes are initiated by the Host Microprocessor via the driver software for the device. The driver provides a set of functions that support transitioning the

WM2000 into the various operating modes. Each function will set the required mode control registers to transition from one mode to the next.

The mode transitions the driver software supports involve a number of intermediate transitions. It is important that the Host Microprocessor follows the complete sequence of operations for each mode transition, as the device behaviour in any of the intermediate states is undefined.

Under some transitions, it is optional whether the Hardware sequencer should configure the analogue

(Line/Mic) circuits, depending on the setting of ANA_SEQ_INCLUDE which forms part of the parameter list for each function call in the driver software. De-selecting this option allows users to define different control sequences for these circuits. If variations to the control sequences are required, users should refer to Wolfson for guidance in the required register operations. The default sequences include configuration of the analogue circuits in all relevant mode transitions.

The following mode transitions are required to support transitioning from one mode to another mode:

1. Power_up Device Ready to ANC Active

2. Power_down

3. Standby_Entry

ANC Active to Shutdown

ANC Active to Standby

4. Standby_Exit

5. Bypass_Entry

6. Bypass_Exit

Standby to ANC Active

ANC Active to Bypass

Bypass to ANC Active

The Thermal Shutdown feature is described in the Thermal Shutdown section.

Power_up Transition

The driver software exposes a Power Up function that allows the host to transition the WM2000 device from “Device Ready” state to “ANC Active”. This transition will Power Up / Set the device up ready to be used for ANC. On completion of this transition, noise cancellation will be active.

Please refer to the WM2000 Driver Software Applications Note.

Power_down Transition

This is the mode transition from “ANC Active” to “Shutdown”.

The driver software exposes a Power Down function that allows the host to transition the WM2000 device from “ANC Active“ to “Shutdown”. Once the Power_down transition has completed the power supplies to the device may be disabled.


Standby_Entry Transition

This is the mode transition from “ANC Active” to “Standby”.

The driver software exposes a function that allows the host to transition the WM2000 device from

“ANC Active” to “Standby”. Once in “Standby” the ANC_Engine will be in sleep mode until the host requests a transition back to “ANC Active” via the “Standby_Exit” transition.

On completion of transition to “Standby” MCLK may now be disabled if desired, which may help to minimise power consumption. Note that if MCLK is disabled, the Control Interface and Thermal

Shutdown circuits are also disabled.

Please refer to the WM2000 Driver Software Applications Note. w PD, July 2012, Rev 4.1

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WM2000

Standby_Exit Transition

This is the mode transition from “Standby” to “ANC Active”.

Note that, if MCLK has been disabled following the Standby_Entry transition, then MCLK must be reenabled prior to commencing the Standby_Exit transition.


“Standby” to “ANC Active”. Once in “ANC Active” the ANC Engine will be awake and Noise

Cancelling.


Bypass_Entry Transition

This is the mode transition from “ANC Active” to “Bypass”.


“ANC Active” to “Bypass”. Once in “Bypass” the ANC_Engine will be in sleep mode until the host request a transition back to “ANC Active” via “Bypass Exit”.

On completion of transition to “Bypass” MCLK may now be disabled if desired, which may help to minimise power consumption. Note that, if MCLK is disabled, then the Control Interface and Thermal

Shutdown circuits are also disabled.


Bypass_Exit Transition

This is the mode transition from “Bypass” to “ANC Active”.

Note that, if MCLK has been disabled following the Bypass_Entry transition, then MCLK must be reenabled prior to commencing the Bypass_Exit transition.


“Bypass” to “ANC Active”. Once in “ANC Active” the ANC Engine will be awake and Noise Cancelling.


ANC ACTIVE WATCHDOG COUNTER

The WM2000 incorporates a Watchdog counter to enable the Host Microprocessor to confirm that the

ANC Engine is operating correctly when in ANC Active mode. In ANC Active mode, the WATCHDOG

COUNTER field is incremented at a rate of 4kHz.

The Host Microprocessor can detect that the ANC Engine has stopped (When in ANC Active mode) by calling the appropriate function from the driver software. If two WATCHDOG reads have the same value then this indicates an error condition in the ANC Engine. w PD, July 2012, Rev 4.1

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WM2000

INPUT SIGNAL PATH

The WM2000 has two analogue input channels; one for the Received Voice (Line) path and one for the Ambient Noise (Microphone) path.

The Line input can be configured to suit the baseband processor voice output.

Each channel is routed to its own dedicated ADC, which provides the input to the Ambient Noise

Cancellation (ANC) Engine. When bypass mode is configured, the Line input is connected directly to the output driver.

The Input Signal Path settings are configured by the Internal Sequencer when the default mode transition sequences are scheduled (see “Ambient Noise Cancellation (ANC) Engine”). The precise configuration will include application-specific settings that are determined as part of the handset characterisation process. If the default sequences are modified to exclude the analogue circuit configuration (setting MODE_ANA_SEQ_INCLUDE = 0), then the registers described in this section will need to be set by the user.

AMBIENT NOISE (MICROPHONE) INPUT

A noise-cancellation application requires one or more electret condenser microphones to be connected in parallel to the Microphone input channel. The total current draw of all microphones should not exceed the available MICBIAS supply current as stated in the “Electrical Characteristics” section. The microphone bias current is provided by the WM2000 itself, as described in the

Microphone Bias section.

The only supported configuration for the microphone input is differential inverting mode, to give maximum gain and acceptable input impedance. The input impedance is critical since it affects the low cut-off frequency of the high-pass filter that results from the combination of the AC coupling capacitor and the input impedance of the device. A low cut-off frequency means that there is no significant filtering of the 20Hz - 20kHz audio frequency bandwidth.

Typically, the 3dB cut-off frequency for the microphone should be around 10Hz. The input impedance in Differential Inverting Mode is around 12k



(see “Electrical Characteristics”). Using the equation in

Figure 9 it follows that the AC coupling capacitors should be approximately 1



F (which gives a 3dB cut-off frequency of 12.4Hz).

The recommended ambient noise microphone connection in Differential Inverting configuration is illustrated in Figure 9. The two AC coupling capacitors on the MICN and MICP pins should have the same value, see “Applications Information”. The grounding arrangement is application dependent; it may be necessary to provide grounding at the microphone for optimal EMI immunity. w

Figure 9 Ambient Noise (Microphone) Input


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WM2000

MIC INPUT PGA ENABLE

The Input PGA is enabled using the register bit MIC_EN as described inTable 4.

REGISTER

ADDRESS

R61479

(F027h) ANA

MIC Control (2)

BIT LABEL DEFAULT

3 MIC_EN

Table 4 Mic Input PGA Enable

0

DESCRIPTION

Mic Input PGA Enable

0 = disabled

1 = enabled

To enable the input PGA, the reference voltage VMID, VMID buffer, and the bias current must also be enabled. These functions are controlled automatically by the WM2000 Internal Sequencer as part of the ANC Engine mode transitions explained in the “ANC (Ambient Noise Cancellation)” section, providing MODE_ANA_SEQ_INCLUDE = ‘1’.

MIC INPUT PGA CONFIGURATION

The Mic input must be configured in Differential Inverting Mode, by setting MIC_MODE [1:0] = 01, as described in Table 5.

REGISTER

ADDRESS

R61479

(F027h) ANA

MIC Control (2)


1:0 MIC_MODE [1:0] 10

DESCRIPTION

Mic Input PGA Mode

00 = Reserved

01 = Differential Inverting Mode

1X = Reserved

This bit must be cleared to 0 R61475

(F027h) ANA

MIC Control (2)

2 MIC_IN_CMAMP

Table 5 MIC Input PGA Configuration

0

In Differential Inverting Mode, the analogue input is connected via MICP and MICN pins to the inverting inputs of the internal amplifier. After gain adjustment, the two signals provide the differential signal required by the ADC. In this mode, the input impedance is 12k



.

MIC INPUT PGA VOLUME CONTROL

The mic input PGA should be configured according to the sensitivity of the microphone and the maximum sound pressure level at which the handset will be used. The optimum setting is provided as part of the Wolfson characterisation procedure since its value is interrelated with other gains throughout system. The input can be muted using MIC_MUTE. These functions are controlled automatically by the WM2000 Internal Sequencer as part of the ANC Engine mode transitions explained in the “ANC (Ambient Noise Cancellation)” section, providing MODE_ANA_SEQ_INCLUDE

= ‘1’.

The maximum output level of the input PGA is 1V

RMS

(differential). Hence, when the maximum gain is selected, the maximum input level without clipping is -28.3dBV (38.5mVRMS).

The MIC Input PGA Volume control fields are described in Table 10. w PD, July 2012, Rev 4.1

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WM2000

BIT LABEL DEFAULT DESCRIPTION REGISTER

ADDRESS

R61477 (F025h)

ANA MIC

Volume

4:0 MIC_VOL[4:0]

R61478 (F026h)

ANA MIC

Control (1)

1 MIC_MUTE

0 MIC_VOL_SHIFT

Table 6 MIC Input PGA Volume Control

0_0000

1

1

This is the gain setting of the microphone input gain block for the MICN/MICP inputs. Non-linear gain curve

MIC_VOL Inverting(dB)

5’b00000 -1.5

5’b00001 -1.3

5’b00010 -1.0

5’b00011 -0.7

5’b00100 -0.3

5’b00101 +0.0

5’b00110 +0.3

5’b00111 +0.7

5’b01000 +1.0

5’b01001 +1.4

5’b01010 +1.8

5’b01011 +2.3

5’b01100 +2.7

5’b01101 +3.2

5’b01110 +3.7

5’b01111 +4.2

5’b10000 +4.8

5’b10001 +5.4

5’b10010 +6.0

5’b10011 +6.7

5’b10100 +7.5

5’b10101 +8.3

5’b10110 +9.2

5’b10111 +10.2

5’b11000 +11.4

5’b11001 +12.7

5’b11010 +14.3

5’b11011 +16.2

5’b11100 +19.2

5’b11101 +22.3

5’b11110 +25.2

5’b11111 +28.3

Mic Mute

0 = Mic channel un-mute

1 = Mic channel mute

This bit should be cleared to 0 w PD, July 2012, Rev 4.1

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MICROPHONE BIAS

The MICBIAS output provides a low-noise reference voltage suitable for biasing one or more electret type microphone(s) via external resistor(s). Note that the maximum source current capability for

MICBIAS is quoted in the “Electrical Characteristics”. The external biasing resistance must be selected in order to set the MICBIAS current within this maximum.

The MICBIAS voltage can be enabled or disabled using the MIC_BIAS_EN control bit and the voltage can be selected using the MIC_BIAS_VSEL register bit as detailed in Table 7.


ADDRESS

R61493 (F035h)

ANA MIC Bias

Control

6

5

MIC_BIAS_EN

MIC_BIAS_VSEL

0

0

Microphone Bias Enable

0 = OFF (high impedance output)

1 = ON

Microphone Bias Voltage Control

0 = 2.0V

1 = 2.1V

(see note)

Table 7 Microphone Bias Control

These functions are controlled automatically by the WM2000 Internal Sequencer as part of the ANC

Engine mode transitions explained in the “ANC (Ambient Noise Cancellation)” section, providing

MODE_ANA_SEQ_INCLUDE = ‘1’.

Note that the MICBIAS voltage will vary with AVDD, which is internally generated by the LDO, and referenced to DCVDD; the quoted figures are valid for DCVDD=1.8V.

RECEIVED VOICE (LINE) INPUT

A noise-cancellation application requires the received voice signal from the baseband processor to be connected to the Line input channel. The line input mode can be configured to suit the baseband processor output format.

The maximum output level of the input PGA is 1V

RMS

(differential). Hence the maximum input level without clipping is dependent on the available gain range for the specified input mode.

LINE INPUT PGA ENABLE

The Input PGA is enabled using the register bit LINE_IN_EN as described in Table 8.

REGISTER

ADDRESS

R61475

(F023h) ANA

Line In Control

(2)


3

Table 8 Input PGA Enable

LINE_IN_EN 0

DESCRIPTION

Line Input PGA Enable

0 = disabled

1 = enabled

To enable the input PGA, the reference voltage VMID, VMID buffer, and the bias current must also be enabled. These functions are controlled automatically by the WM2000 Internal Sequencer as part of the ANC Engine mode transitions explained in the “ANC (Ambient Noise Cancellation)” section, providing MODE_ANA_SEQ_INCLUDE = ‘1’. w PD, July 2012, Rev 4.1

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WM2000

LINE INPUT PGA CONFIGURATION

The line input can each be configured in three different modes, which are as follows:

 Differential Non-Inverting Mode

 Single Ended (Inverting) Mode

 Differential Inverting Mode

The Input PGA mode is selected using the LINE_IN_MODE register field as described in Table 9.

(2

REGISTER

ADDRESS

R61475

(F023h) ANA

Line In Control

BIT LABEL DEFAULT DESCRIPTION

1:0 LINE_IN_MODE

[1:0]

01 Line Input PGA Mode

00 = Single Ended Inverting Mode


1X = Differential Non-Inverting Mode

Table 9 Line Input PGA Configuration

It is recommended that one of the Inverting Modes be used for the Line input; this is likely to be the best match for the baseband processor in terms of input impedance and the available gain.

SINGLE-ENDED INVERTING MODE

In Single Ended Inverting Mode, the analogue input is connected via the LINN pin to the internal amplifier, and the LINP pin is not used. A phase-inverted copy of this is generated within the WM2000 to provide the differential signal required by the ADC. This is most suited to single ended baseband processor outputs.

In this mode, the input impedance is 12k



, and the available gain is -6dB to +28.3dB. (Note that, if

LINE_IN_VOL_SHIFT is selected, then the input impedance is 21.62k



and the available gain is reduced by 4.5dB. See Table 10 for definitions of these register fields.)

Figure 10 Single-Ended Inverting Line Input w PD, July 2012, Rev 4.1

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WM2000

DIFFERENTIAL INVERTING MODE

In Differential Inverting Mode, the analogue input is connected via LINP and LINN pins to the inverting inputs of the internal amplifier. After gain adjustment, the two signals provide the differential signal required by the ADC. This is most suited to differential baseband processor outputs. In this mode, a

Common Mode noise reduction circuit may be enabled, if required; this is described in a later section.




, and the available gain is -6dB to +28.3dB. (Note that, if

LINE_IN_VOL_SHIFT is selected, then the input impedance is 21.62k



and the available gain is reduced by 4.5dB. See Table 10 for definitions of these register fields).

Figure 11 Differential Inverting Line Input

DIFFERENTIAL NON-INVERTING MODE




, and the available gain is +12dB to +30dB. As discussed in the “Input PGA Volume Control” section, the maximum input signal without clipping is -12dBV

(250mVrms).

Figure 12 Differential Non-Inverting Line Input w PD, July 2012, Rev 4.1

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WM2000

INPUT PGA VOLUME CONTROL

The volume control on the Line channel can be independently controlled using the LINE_IN_VOL register field as described in Table 10. The available gain range varies according to the selected PGA

Mode as detailed in Table 11. Note that the value ‘00000b’ must not be used in Non-Inverting Mode, as the PGA will not function correctly under this setting.

In Single Ended Inverting Mode and Differential Inverting Mode, the signal level can be reduced by

4.5dB using the LINE_IN_VOL_SHIFT control field.

The input can be muted using LINE_IN_MUTE.

It should be noted that there is no feature to ensure that volume changes are implemented glitch-free.

Therefore, it is recommended that the volume control should not be adjusted dynamically whilst the signal path is enabled; the signal should be muted at the input or output stage prior to adjusting the volume control.

The maximum output level of the input PGAs is 1V

RMS

(differential). The maximum input signal level at the external pins of the WM2000 will vary with the selected gain settings. The PGA volume settings should be chosen to ensure that a full-scale input signal is compatible with the maximum output level of the input PGAs.

In the Differential Input modes, with 0dB gain selected, the maximum (differential) input signal would be 1VRMS. With +12dB gain selected, the maximum (differential) input signal would be reduced by

12dB, ie. 0.25VRMS.

In the Single Ended to Differential Input mode, there is an inherent 6dB gain in the conversion to differential. Therefore, with 0dB gain selected, the maximum (single-ended) input signal would be

0.5V. With -1.5dB gain selected, the maximum (single-ended) input signal would be 0.6V.

The Input PGA Volume control fields are described in Table 10.

REGISTER

ADDRESS

R61473 (F021h)

ANA Line In

Volume

R61474 (F022h)

ANA Line In

Control (1)


4:0

1

LINE_IN_VOL

[4:0]

LINE_IN_MUTE

0_0000

1

Line Volume

(See Table 11 for volume range)

0 LINE_IN_VOL_S

HIFT

1

Line mute

0 = Line channel un-mute

1 = Line channel mute

Line Volume Shift

0 = Line volume as set by

LINE_IN_VOL

1 = Line volume reduced by 4.5dB

Note: this field has no effect in

Differential Non-Inverting mode

(LINE_IN_MODE=1X)

Table 10 Line Input PGA Volume Control w PD, July 2012, Rev 4.1

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00000

00001

00010

00011

00100

00101

00110

00111

WM2000

SINGLE ENDED INVERTING

MODE

DIFFERENTIAL INVERTING MODE

-1.5 dB

-1.3 dB

-1.0 dB

-0.7 dB

-0.3 dB

0.0 dB

+0.3 dB

+0.7 dB

GAIN -

DIFFERENTIAL NON-

INVERTING MODE

Not valid

+12 dB

+15 dB

+18 dB

+21 dB

+24 dB

+27 dB

+30 dB w

Table 11 Line Input PGA Volume Range


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WM2000

LINE INPUT COMMON MODE AMPLIFIER

In Differential Inverting Mode, a Common Mode amplifier can be enabled as part of the Line Input

PGA circuit. This feature provides approximately 40dB reduction in common mode noise on the differential input, which can be effective at reducing problematic interference. Since the ADC has differential signal inputs, it has an inherent immunity to common mode noise. However, the presence of Common Mode noise such as 50/60Hz AC mains “hum” can limit the usable signal range of the

ADC path.

It should be noted that the Common Mode amplifier consumes additional power and can also add its own noise to the input signal. For these reasons, it is recommended that the Common Mode Amplifier is only enabled if there is a known source of Common Mode interference.

The Common Mode amplifier is controlled by the LINE_IN_CMAMP field as described in Table 12.

Although the Common Mode amplifier may be enabled regardless of the input PGA mode, its function is only effective in the Differential Inverting Mode configuration.


ADDRESS

R61475 (F023h)

ANA Line In

Control (2)

2 LINE_IN_CMAMP 0 Line Input Common Mode

Amplifier Enable

0 = Disabled

1 = Enabled

Table 12 Line Input Common Mode Amplifier Enable

ANALOGUE TO DIGITAL CONVERTERS (ADC)

The WM2000 has two ADCs; one for the Received Voice (Line) path and one for the Ambient Noise

(Microphone) path. The ANC Engine will control the ADCs correctly, regardless of the setting of the

ANA_SEQ_INCLUDE bit. They will be enabled for ANC Active mode and disabled for all other modes to reduce power consumption. These register bits are defined in Table 13.

REGISTER

ADDRESS

R61481 (F029h)

ANA ADC 0

Control (1)


7 ADC_0_EN 0

DESCRIPTION

R61484

(F02Ch) ANA

ADC 1 Control

(1)

3

1

0

ADC_0_DISOFF

ADC_1_EN

ADC_1_DISOFF

0

0

0

Enables Noise Cancellation (MIC)

ADC

0 = disabled

1 = enabled

The ANC Engine will set this register bit to 1.

Enables Received Voice (LINE)

ADC

0 = disabled.

1 = enabled.


Table 13 ADC Control w PD, July 2012, Rev 4.1

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DIGITAL TO ANALOGUE CONVERTER (DAC)

The WM2000 has a single DAC, which converts the digital output from the ANC engine to analogue form for the output mixing stages. The ANC Engine will control the DAC correctly, regardless of the setting of the ANA_SEQ_INCLUDE bit. It will be enabled for ANC ACTIVE mode and disabled for all other modes to reduce power consumption.

REGISTER

ADDRESS

R61487

(F02Fh) ANA

DAC Control (1)


4 DAC_EN 0

DESCRIPTION

3

R61489 (F031h)

ANA DAC

Control (3)

0

Table 14 DAC Control

DACANRES

DAC_CLK_MODE

0

0

This enables the DAC

0 = disabled

1 = enabled

This connects the DAC outputs to

VMID. Can be used to optimise pop-click performance during startup and shutdown.

0 = DAC muted

1 = Normal DAC operation


Default value 0.

OUTPUT SIGNAL PATH

The audio output from the WM2000 is a mono speaker driver, suitable for driving a handset receiver through a BTL configuration.

In ANC ACTIVE mode, the output signal path uses an output PGA mixer, which combines a signal direct from the Received Voice (Line) input channel with the output from the DAC.

When Bypass mode is selected, the ANC Engine sets up a bypass signal path in order to save power by disabling selected circuits that are not required. In bypass mode, the ADCs, DAC and output PGA mixer are all disabled by the ANC Engine.

The Output Signal Path settings are configured by the Internal Sequencer when the default mode transition sequences are scheduled (see “Ambient Noise Cancellation (ANC) Engine”). The precise configuration will include application-specific settings that are determined as part of the handset characterisation process. If the default sequences are modified to exclude the analogue circuit configuration (setting MODE_ANA_SEQ_INCLUDE = 0), then the registers described in this section will need to be set by the user.

OUTPUT PGA MIXER

The Output PGA has two inputs and a single output. The inputs are the DAC path (from the ANC engine) and the LINE path (from the LINP and LINN input pins). The Output PGA circuit is enabled by setting the PGA_EN register field.

The gain of the DAC input to the PGA is controlled by PGA_DAC_GAIN as described in Table 15.

This signal can also be muted using PGA_DAC_MUTE.

Limited control of the LINE input level to the PGA is provided by PGA_LINE_0DB. This signal path can also be muted using the PGA_LINE_MUTE bit as described in Table 15. w PD, July 2012, Rev 4.1

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WM2000


ADDRESS

R61490 (F032h)

ANA PGA Gain

2:0 PGA_DAC_GAIN

[2:0]

000

R61491 (F033h)

ANA PGA

Control

3

2

1

0

PGA_EN

PGA_LINE_MUTE

PGA_DAC_MUTE

PGA_LINE_0DB

0

1

1

0

This controls the gain of the ANC input to the output PGA

000 = mute

001 = -12 dB

010 = -9 dB

011 = -6 dB

100 = -3 dB

101 = 0 dB

110 = 3 dB

111 = 6 dB

This enables the output PGA

0 = disabled

1 = enabled

This mutes the LINE input to the output PGA

0 = not muted

1 = muted

This mutes the ANC input to the output PGA

0 = not muted

1 = muted

This controls the gain of the LINE input to the output PGA.

0 = -6dB

1 = 0dB

Table 15 Output PGA Control

BYPASS PATH

It is recommended to select bypass path by requesting the ANC Engine to carry out a mode transition into Bypass Mode as detailed in the “ANC (Ambient Noise Cancellation)” section.

When Bypass mode is selected, the ANC Engine selects a bypass signal path in order to save power by disabling unnecessary circuits. The bypass signal path connects the LINE input (from the LINP and LINN pins) to the speaker output driver, as illustrated in Figure 8. In bypass mode, the input

PGAs, ADCs, DAC and output PGA mixer are all disabled.

The bypass path is selected by the ANC Engine using the SPK_BYPS field. When the bypass path is selected, the input PGA and output PGA have no effect. Note that, if PGA gain has been applied to the Received Voice (Line) signal in ANC mode, this gain will not be applied in Bypass mode. In this case, the effective signal path gain will change when bypass mode is selected or de-selected.

REGISTER

ADDRESS

R61492 (F034h)

ANA Speaker

Control


4 SPK_BYPS 0 Selects the ANC Bypass path

0 = Output is from the ANC engine and Output PGA

1 = Output is from LINP and LINN input pins

Table 16 Bypass Path Enable w PD, July 2012, Rev 4.1

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SPEAKER OUTPUT

The speaker output is derived from either the output PGA or from the bypass path as described earlier. The speaker amplifier is enabled using SPK_EN. The inputs and outputs of the speaker amplifier can be enabled independently using SPK_MUTE and SPK_OUT_EN respectively. These fields provide the pop/click control for optimum power-up and power-down sequences, which are included during ANC Engine mode transitions when ANA_SEQ_INCLUDE = 1. The SPK_OUT_EN also permits a reduction in quiescent current when the speaker is not being used.

The DC bias of the speaker output driver is controlled using the SPK_MID_ADJ register field. The DC bias should be set as close as possible to SPKVDD/2, in order to enable the largest possible unclipped audio output.

Note that the voltage set by SPK_MID_ADJ varies proportionately with DCVDD. The normal values quoted are valid for DCVDD = 1.8V.

The speaker connection is BTL and does not require the use of DC blocking capacitors; the speaker connects directly across the SPKP and SPKN output pins. The output driver is designed for a minimum speaker impedance of 16



.

The speaker output register controls are described in Table 17.

REGISTER

ADDRESS

R61492 (F034h)

ANA Speaker

Control


5 SPK_EN 0

3:2

1

0

SPK_MID_ADJ

[1:0]

SPK_MUTE

SPK_OUT_EN

00

1

0

DESCRIPTION

This enables the speaker amp

0 = disabled

1 = enabled

This adjusts the VMID of the speaker outputs. This should be set to as close to SPKVDD/2 as possible.

00 = 1.4V

01 = 1.5V

10 = 1.6V

11 = 1.7V

(see note)

This bit must be set to 0 for normal operation. It may be set to 1 by the

Internal Sequencer during power-up or power down sequences.

This enables the output from the speaker amp

0 = disabled

1 = enabled

Table 17 Speaker Output Control

Note that the Speaker DC bias levels vary with DCVDD; the quoted figures are valid for

DCVDD=1.8V. w PD, July 2012, Rev 4.1

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WM2000

LDO REGULATOR

The LDO is a linear voltage regulator which is referenced to DCVDD and generates the internal

AVDD supply at a voltage of DCVDD + 50mV. A capacitor must be attached to the LDO_OUT pin to provide decoupling.

The LDO is enabled by default, but can be disabled using the LDO_EN register bit. A small reduction in power consumption may be achieved by switching off the LDO Regulator in Device Ready or

Standby modes (see “Ambient Noise Cancellation (ANC) Engine”). However, thermal shutdown is not supported when the LDO is disabled. Control of the LDO_EN must be correctly integrated into mode transition sequences.

It is recommended that the LDO is enabled at all times.

REGISTER

ADDRESS

R61480 (F028h)

ANA MIC

Control (3)


0

Table 18 LDO Control

LDO_EN 1

DESCRIPTION

LDO enable.

0 = LDO disabled

1 = LDO enabled

SYSTEM CLOCKING

MCLK is the Master Clock signal applied to the WM2000. It is required by the ANC Engine and by the

Control Interface and by other internal circuits in some operating modes. The WM2000 incorporates in internal MCLK divider in order to support a wide range of external MCLK frequencies, as described under “Signal Timing Requirements”. The resultant signal is called SYSCLK. The MCLK Divider can be controlled using the Register bits described in the “Ambient Noise Cancellation (ANC) Engine” section.

SYSCLK is required for all Control Interface functionality. The f

SYSCLK

* Min(t1, t2) value quoted in

“Signal Timing Requirements” describe the conditions under which Read functionality is supported.

When the WM2000 reaches the “Device Ready” condition following a successful Power-On Reset, the internal MCLK Divider is enabled. If the MCLK frequency is in the range 9.5MHz - 13.5MHz, and the MCLK Divider is enabled, then the Control Interface will be limited. Read operations will not be supported across the full range of SCLK frequencies and duty cycle ratios. In this case, the MCLK

Divider should be disabled in order to allow full Read/Write Control Interface functions and full ANC operation. If the MCLK frequency is in the range 19MHz - 27MHz, then the MCLK Divider should not be adjusted from the default setting.

The ANC acoustic coefficients provided by Wolfson for a particular application have a dependency upon the MCLK frequency. Therefore, the MCLK frequency and MCLK Divider setting must be determined prior to handset characterisation. Any change in MCLK from these settings will affect the

ANC performance, and will require a new set of acoustic coefficients to be generated.

GENERAL PURPOSE INPUT/OUTPUT

The WM2000 has a single GPIO pin which may be configured as input or output. The direction of the

GPIO pin is selected using the GPIO_OE_CLR and GPIO_OE_SET bits defined in Table 19. Writing

'1' to GPIO_OE_CLR configures the GPIO pin as an input. Writing '1' to GPIO_OE_SET configures the GPIO pin as an output.

When configured as an input, the logic level of the GPIO pin can be determined by reading the

GPIO_IN register bit. The GPIO input may be inverted using the GPIO_IN_INV_CLR and

GPIO_IN_INV_SET bits defined in Table 19. Writing '1' to GPIO_IN_INV_CLR selects the noninverted GPIO input. Writing '1' to GPIO_IN_INV_SET selects inverted GPIO input.

When configured as an output, the logic level of the GPIO output pin is determined by the

GPIO_OUT_CLR and GPIO_OUT_SET bits defined in Table 19. Writing '1' to the GPIO_OUT_SET bit configures the GPIO output to logic ‘1’. Writing '1' to the GPIO_OUT_CLR bit configures the GPIO output to logic ‘0’.

The electrical characteristics of the GPIO as an output pin are determined by the GP_OD_EN bit. If this bit is set, the GPIO behaves as an open drain output: the pin is pulled to ground when set to logic

‘0’ and is tri-stated when set to logic ‘1’. If GP_OD_EN is not set, the GPIO is driven high or low according to the commanded logic state. w PD, July 2012, Rev 4.1

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REGISTER

ADDRESS

R61448 (F008h)

GPIO register

WM2000


4 GPIO_IN 0

R61449 (F009h)

GPIO

Configuration

R61472 (F020h)

ANA GPIO Pad

Control

3 GPIO_OE_CLR

2 GPIO_OE_SET

1 GPIO_OUT_CLR

0 GPIO_OUT_SET

5 GPIO_IN_INV_CLR

4 GPIO_IN_INV_SET

0 GP_OD_EN

0

0

0

0

0

0

0

This field represents the current

GPIO input value. It may be inverted, depending on the GPIO_IN_INV_* register settings

Writing ‘1’ configures the GPIO pin as an input.

Writing ‘0’ has no effect.

Read value is '0'

Writing ‘1’ configures the GPIO pin as an output.


Read value is the current status of the GPIO pin configuration:

0 = GPIO is input

1 = GPIO is output

Writing ‘1’ sets the GPIO output to ‘0’


Read value is '0'



Read value is the current status of the GPIO output level:

0 = GPIO is logic ‘0’


Writing ‘1’ selects non-inverted GPIO input


Read value is '0'

Writing ‘1’ selects inverted GPIO input


Read value is the current status of the GPIO input inversion:

0 = GPIO input is not inverted

1 = GPIO input is inverted

GPIO Output pin configuration

0 = CMOS

1 = Open-drain

In CMOS configuration, the GPIO pin is driven low or high, according to the commanded output condition.

In Open-drain configuration, the

GPIO pin is driven low for logic ‘0’ output, and is tri-stated for logic ‘1’ output.

Table 19 GPIO Control Registers w PD, July 2012, Rev 4.1

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CONTROL INTERFACE

The WM2000 is controlled by writing to registers through a 2-wire serial control interface. A control word consists of 24 bits, transmitted as 3 bytes. The first two bytes contain the address bits that select which control register is accessed. The third byte contains data, corresponding to the 8 bits in the selected control register.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM2000). The default device ID for the WM2000 is 0111 0100 (0x74h). Alternatively, the device ID can be set to

0111 0110 (0x76h) by pulling the ADDR pin high. This pin is read at the start of every 2-wire access operation; it is recommended to either pull this pin up to DBVDD or connect it to DGND, to maintain a constant device address. The LSB of the device ID is the Read/Write bit; this bit is set to logic 1 for

“Read” and logic 0 for “Write”.

The WM2000 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDA while SCLK remains high. This indicates that a device ID, register address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDA (7-bit device ID + Read/Write bit, MSB first). If the device ID received matches the device ID of the WM2000, then the WM2000 responds by pulling SDA low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode, the WM2000 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM2000, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCKL remains high. After receiving a complete address and data sequence the WM2000 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to the idle condition.

The WM2000 supports the following read and write operations:



Single

 read



Multiple write using auto-increment



Multiple read using auto-increment

SYSTEM CLOCKING DURING CONTROL INTERFACE ACCESSES

The Control Interface function requires MCLK to be running. Note that, if the MCLK frequency is in the range 9.5MHz - 13.5MHz, and the MCLK Divider is enabled, then the Control Interface capability will be limited; Read operations will not be supported across the full range of SCLK frequencies. See

“Signal Timing Requirements” for details of the supported MCLK and SCLK frequencies.

SINGLE WRITE AND READ ACCESSES

The sequence of signals associated with a single register write operation is illustrated in Figure 13.

Figure 13 Control Interface 2-wire Register Write w PD, July 2012, Rev 4.1

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The sequence of signals associated with a single register read operation is illustrated in Figure 14.

Figure 14 Control Interface 2-wire Register Read

MULTIPLE WRITE AND READ ACCESSES

The Control Interface also supports multiple register operations. Multiple Write and Multiple Read operations enable the Host Microprocessor to access sequential blocks of the data in the WM2000 register map faster than is possible with single register operations. For multiple write and multiple read operations, the auto-increment option must be enabled. This feature is enabled by default; it is described in Table 20.

REGISTER

ADDRESS

R61446 (F006h)

Interface Control


0 AUTOINC 1

DESCRIPTION

Enable Auto-Increment function

0 = Disabled

1 = Enabled

Table 20 Auto-Increment Interface Control

The signal timing of multiple register operations is consistent with single writes and reads, however the byte ordering is different, as shown below. The terminology used in the following figures is detailed in Table 21.

TERMINOLOGY DESCRIPTION

A Acknowledge

1 = Read

[White field]

[Grey field]

Data flow from bus master to WM2000

Data flow from WM2000 to bus master

Table 21 Control Interface Terminology

The byte ordering of Multiple Write and Multiple Read operations using auto-increment is shown in

Figure 15 and Figure 16.

Figure 15 Multiple Register Write using Auto-increment w PD, July 2012, Rev 4.1

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WM2000

Figure 16 Multiple Register Read using Auto-increment

SET AND CLEAR REGISTER BIT PAIRS

Some registers on the WM2000 contain pairs of register bits which are a _SET/_CLR bit pair . The purpose of this is to allow functions to be modified, while maintaining the settings of other fields within the same register, but without the need for “read-modify-write” cycles. This provides a saving on code memory and also in timing efficiency. If a Write operation is performed to such a register with only one bit set, then only a single function is affected, and other functions in the same register are unaffected.

This control configuration is provided for some System Control functions (see “Ambient Noise

Cancellation (ANC) Engine”) and also for GPIO Configuration (see “General Purpose Input/Output”).

In each case, the internal WM2000 function is cleared to 0 or set to 1 by writing to the register bits named _CLR and _SET respectively:



Write ‘1’ to the _SET bit sets the WM2000 function to 1.



Write ‘1’ to the _CLR bit clears the WM2000 function to 0.

The current value of the WM2000 function can be determined by reading from the _SET register bit.

Reading from the _CLR location has no meaning, and will always return a logic ‘0’.

EXAMPLE

One example of a bit pair is the register bits GPIO_OUT_CLR and GPIO_OUT_SET in the GPIO register (0xF008). These two register bits control the internal WM2000 GPIO_OUT function

(explained in the “General Purpose Input/Output” section on page 32). Table 22 describes the effect which Host Microprocessor operations will have on this bit pair.

HOST ACCESS

Write ‘0’ to the GPIO_OUT _CLR bit

Write ‘0’ to the GPIO_OUT _SET bit

No effect

No effect

EFFECT

Write ‘1’ to the GPIO_OUT

Write ‘1’ to the GPIO_OUT

Write ‘11’ to the _SET

Read the GPIO_OUT

Read the GPIO_OUT

/

_CLR

_SET

_CLR

_CLR

_SET

bit pair

bit

bit

bit

bit

Clear the internal WM2000 function (GPIO_OUT) to 0

Set the internal WM2000 function (GPIO_OUT) to 1

Not recommended

Always read back as ‘0’

Read back current state of the internal WM2000 function

(GPIO_OUT)

Table 22 Example of Register _SET/_CLR Bit Pair w PD, July 2012, Rev 4.1

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SOFTWARE RESET AND DEVICE ID

The WM2000 can be reset by writing to Register R61440 (0xF000). This is a read-only register field, and the contents will not be affected by writing to this Register.

The Device ID can be read back from Register R61440 (0xF000), as described in Table 23.

ID2

REGISTER

ADDRESS

R61440 (F000h)

Reset/ID1

R61441 (F001h)


7:0

7:0

SW_RESET_CHIP_I

D1 [7:0]

CHIP_ID2 [7:0]

DESCRIPTION

0010_0000 Writing to this register triggers a software reset.

Reading from this register will indicate the MS Byte of the Chip ID

- 20h

0000_0000 Reading from this register will indicate the LS Byte of the Chip ID

- 00h.

Table 23 Software Reset and Device ID

The status of the WM2000 Register Map contents following a software reset is described in Table 26.

Note that the register contents may be updated by the ANC Engine when any of the ANC Mode

Transitions is scheduled (see “Ambient Noise Cancellation (ANC) Engine”).

REGISTER

ADDRESS

0x8000 – 0x8FFF

0xF000 – 0xF092

0xF093 – 0xFFFF

DESCRIPTION REGISTER CONTENTS AFTER

SOFTWARE RESET

RAM registers

System registers

No change (see note)

Default values (see note)

Peripheral registers Default values

Table 24 Register Contents after Software Reset

Note that, within 1ms of the Software Reset, the contents of Registers 0x8FFC – 0x8FFF and 0xF005 may be modified by the internal boot-up sequence.

In order to carry out a complete reset of all WM2000 RAM registers, a power on reset is required, see the “Power-On Reset (POR)” section. w PD, July 2012, Rev 4.1

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WM2000

POWER-ON RESET (POR)

The WM2000 includes an internal Power-On Reset circuit, as shown in Figure 17, which is used to reset the device into a default state after power-up.

DCVDD is below a minimum threshold. there are further requirements which must be satisfied in order for the WM2000 to reach the “Device

Ready” state. Further mode transitions may then be scheduled as described in the “ANC (Ambient

Noise Cancellation) section”.

Figure 17 Internal Power on Reset Circuit Schematic

POWER SUPPLY SEQUENCE

The timing and sequencing of the Power-On Reset is illustrated in Figure 18. This also shows the associated requirements for reaching the “Device Ready” state.

When SPKVDD goes above the minimum threshold, V pora

, there is enough voltage for the circuit to

After SPKVDD is at full supply level, and DCVDD rises to V pord

, the internal POR device is no longer held in the Reset state.

After DBVDD rises to V porb

, 16 MCLK cycles are required in order to fully reset the digital circuit. On completion of these 16 MCLK cycles, the WM2000 will reach the “Device Ready” state. From this point, register read and write operations are supported via the Control Interface.

It is important that SPKVDD is applied to the WM2000 before DCVDD. It can be seen that since t

2 has minimum value of 0, DCVDD and DBVDD can be externally connected.

The threshold voltages and timing characteristics for Power-On Reset are listed in Table 25. See

“Electrical Characteristics” for definitions of the “Test Type” in Table 25. w PD, July 2012, Rev 4.1

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Figure 18 Power-On Reset Timing

TEST

TYPE

3

2

2

3

3

V

V

V

V pora1 pora2 porc porb t1 t2

SPKVDD rising threshold for

Internal POR active. (POR is undefined below this voltage.)

SPKVDD rising threshold for

POR circuit function.

DCVDD rising threshold for

Internal POR set high

DBVDD rising threshold for

Device Ready

Wait time between SYSVDD enabled and DCVDD enabled

Wait time between DCVDD enabled and DBVDD enabled

3 t3

V pora_off

LDO turn on time

SPKVDD falling threshold for

Internal POR active

Table 25 Power-On Reset Timing

200 mV

1.35 2.23 2.6 V

0.65 1.3 1.66 V

1.1 V

200

 s

0

 s

1.3 2.18 2.5 V w PD, July 2012, Rev 4.1

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WM2000

REGISTER DEFAULT VALUES

The status of the WM2000 Register Map contents in the “Device Ready” state is as described in

Table 26. Note that the register contents may be updated by the ANC Engine when any of the ANC

Mode Transitions is scheduled (see “Ambient Noise Cancellation (ANC) Engine”).

REGISTER

ADDRESS

0x8000 – 0x8FFF

0xF000 – 0xF092

RAM registers

System registers

AT “DEVICE READY”

FOLLOWING POR

Undefined

Default values

0xF093 – 0xFFFF Peripheral registers Default values

Table 26 Register Contents after Power-On Reset (POR)

FOLLOWING ANC

MODE TRANSITION

Set by ANC Engine

Set by ANC Engine

Default values

THERMAL SHUTDOWN

WM2000 contains a Thermal Shutdown block which provides optional protection against overheating in 2 stages:

1. WM2000 sets TP_WARN (bit 1 of 0xF03A) to ‘1’ when the temperature exceeds a lower threshold T

TP_WARN, specified in the “Electrical Characteristics” section.

2. When the temperature is greater than a second threshold T

TP_SHUT

, (specified in the

“Electrical Characteristics”), WM2000 hardware sets TP_SHUT (bit 0 of 0xF03A) to ‘1’.

The ANC Engine monitors this bit and if set to ‘1’ will invoke a power down sequence without pop-click performance considerations, within 10ms. This will leave WM2000 in

Powered Down mode. STATUS_THERMAL_SHUTDOWN_COMPLETE (bit 3 of

0x8FFC) will be set to ‘1’ by the ANC Engine once shut down. The Host Microprocessor should therefore monitor both register bits to check for complete thermal shutdown. If the

Host Microprocessor finds TP_SHUT = 1 and

STATUS_THERMAL_SHUTDOWN_COMPLETE = 0, it should perform a shutdown of

WM2000.

MCLK, DCVDD and DBVDD are all required for the thermal shutdown functionality. Without MCLK,

DCVDD or DBVDD, TP_WARN cannot be polled and the WM2000 cannot complete the thermal shutdown sequence in the case of temperature greater than T

TP_SHUT

.


ADDRESS

R61498 (F03Ah)

ANA Thermal

Protection Status

R36860 (8FFCh)

SYS_STATUS

1

0

TP_WARN

TP_SHUT

3 STATUS_THERMAL

_SHUTDOWN_COM

PLETE

Table 27 Thermal Protection Register Fields

0

0

0

A logic 1 indicates that the Thermal

Warning level has been reached


Shutdown level has been reached


Shutdown has completed w PD, July 2012, Rev 4.1

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REGISTER MAP

The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM2000 can be configured using the Control Interface. All registers not listed and all unused bits should

R61481

(F029h)

R61484

(F02Ch)

R61487

(F02Fh)

R61489

(F031h)

R61477

(F025h)

R61478

(F026h)

R61479

(F027h)

R61480

(F028h) be set to '0'. Key to characters in brackets: R = read-only, W = write-only.

REG

R61440

(F000h)

NAME

Reset/ID1

7 6 5 4 3 2 1 0 DEFAULT

SW_RESET_CHIP_ID1[7:0] 20h

ID2 CHIP_ID2[7:0] 00h

R61446

(F006h)

R61448

(F008h)

R61449

(F009h)

R61472

(F020h)

R61473

(F021h)

R61441

(F001h)

R61443

(F003h)

R61444

(F004h)

R61445

(F005h)

System Control (1)

System Control (2)

System Status

Interface Control

GPIO register

GPIO Configuration

ANA GPIO Pad Control

ANA Line In Volume

MCLK_DIV2_

ENA_CLR

MCLK_DIV2_

ENA_SET

ANC_ENA_C

LR

ANC_ENA_S

ET

ANC_INT_N_

CLR

ANC_INT_N_

SET

V_CLR

GPIO_IN_IN

V_SET

0 0 0

LR

GPIO_OE_S

ET

RAM_CLR RAM_SET 54h

GPIO_OUT_

CLR

LINE_IN_VOL[4:0]

DLE

GPIO_OUT_

SET

00h

20h

00h

R61474

(F022h)

ANA Line In Control (1)

TE

LINE_IN_VO

L_SHIFT

07h

R61475

(F023h)

ANA Line In Control (2)

AMP

LINE_IN_MODE[1:0] 01h

ANA MIC Volume 0 0 0 MIC_VOL[4:0] 00h

ANA MIC Control (1)

ANA MIC Control (2)

ANA MIC Control (3)

ANA ADC 0 Control (1) ADC_0_EN 0

ANA ADC 1 Control (1)

ANA DAC Control (1)

ANA DAC Control (3)

0 0 ADC_0_DIS

OFF

07h

HIFT

MIC_MODE[1:0] 02h

OFF

ODE

00h

02h

R61490

(F032h)

ANA PGA Gain 0 0 0 0 0 PGA_DAC_GAIN[2:0] 00h

R61491

(F033h)

ANA PGA Control

MUTE

PGA_DAC_M

UTE

PGA_LINE_0

DB

06h

ANA Speaker Control 02h R61492

(F034h)

R61493

(F035h)

R61495

(F037h)

ANA MIC Bias Control

ANA Master Bias

Control

0 MIC_BIAS_E

N

MIC_BIAS_V

SEL

AS_EN

N

MASTER_BIAS_ISEL[1:0] MASTER_BI

AS_POB_CT

RL

04h w PD, July 2012, Rev 4.1

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WM2000

REG

R61496

(F038h)

NAME

ANA IBIAS Control

7 6 5 4 3 2 1 0

AS_STARTU

P

DEFAULT

00h

R61497

(F039h)

R61498

(F03Ah)

R61499

(F03Bh)

ANA Thermal Protection

Control

ANA Thermal Protection

Status

ANA VMID Control

R61500

(F03Ch)

R61952

(F200h)

ANA RAM Power

Control

Filter Control (1)

R61954

(F202h)

Filter Control (3)

Table 28 WM2000 Register Map

0 VMID_EN VMID_RES[1:0] VMID_SOFT[1:0]

_EN

VMID_IO_EN 00h

R

IIR_ENA_SE

T

HPF1_ENA_

CLR

PD

HPF1_ENA_

SET

NC_HPF1_U

PD

HPF0_ENA_

CLR

NC_HPF0_U

PD

01h

EN

HPF0_ENA_

SET

00h

IIR_UPD 00h

Note:

1. Registers in the range 0x8FF6-8FFF are only valid if the register writes contained in “WM2000_mouse.txt” have been carried out according to the “Ambient Noise Cancellation (ANC) Engine” section. w PD, July 2012, Rev 4.1

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REGISTER BITS BY ADDRESS

REGISTER

ADDRESS

R61440 (F000h)

Reset/ID1


7:0 SW_RESET_CHIP_ID1[7:0]

DESCRIPTION

0010_0000 Writing to this register triggers a software reset.

Reading from this register will indicate the MS Byte of the Chip ID - 20h

Table 29 Register F000h Reset/ID1

REGISTER

ADDRESS

R61441 (F001h)

ID2

7:0

Table 30 Register F001h ID2

CHIP_ID2[7:0] 0000_0000 Reading from this register will indicate the LS Byte of the Chip ID - 00h.

DESCRIPTION

REGISTER

ADDRESS

R61443 (F003h)

System Control (1)


0 SYS_STBY 0

DESCRIPTION

A logic 1 commands the WM2000 to select System

Standby. In this mode, all of the internal clocks are disabled. In this mode, no other registers may be accessed. Thermal Protection is also disabled in this mode.

Writing a logic 0 to this register re-starts the internal clocks.

Table 31 Register F003h System Control (1) w PD, July 2012, Rev 4.1

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REGISTER

ADDRESS

R61444 (F004h)

System Control (2)

7 MCLK_DIV2_ENA_CLR 0

DESCRIPTION

6 MCLK_DIV2_ENA_SET

5 ANC_ENA_CLR

4 ANC_ENA_SET

3 ANC_INT_N_CLR

2 ANC_INT_N_SET

1 RAM_CLR

0 RAM_SET

1

0

1

0

1

0

0

Writing '1' disables the MCLK Divider.

Writing '0' has no effect.

Read value is always '0'.

Writing '1' enables the MCLK Divider.

Writing '0' has no effect.

Read value is the current status of the MCLK Divider:

0 = MCLK Divider Disabled

1 = MCLK Divider Enabled

Writing ‘1’ resets the ANC Engine.


Read value is always ‘0’

Writing ‘1’ enables the ANC Engine.


Read value is the current status of the ANC Engine:

0 = ANC Engine Disabled

1 = ANC Engine Enabled

Writing ‘1’ enables the ANC Interrupts.



Writing ‘1’ disables the ANC Interrupts.


Read value is the current status of the ANC Interrupt

(Active Low):

0 = ANC Interrupt Active

1 = ANC Interrupt Not Active

Writing ‘1’ disables the Internal RAM.



Writing ‘1’ enables the Internal RAM.


Read value is the current status of the Internal RAM:

0 = Internal RAM Disabled

1 = Internal RAM Enabled

Table 32 Register F004h System Control (2)

REGISTER

ADDRESS

R61445 (F005h)

System Status

0 ANC_ENG_IDLE

Table 33 Register F005h System Status

REGISTER

ADDRESS

R61446 (F006h)

Interface Control

0 AUTOINC

0

1

DESCRIPTION

A logic 1 indicates that the ANC Engine is Idle.

DESCRIPTION

Enable Auto-Increment function

0 = Disabled

1 = Enabled

Table 34 Register F006h Interface Control w PD, July 2012, Rev 4.1

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REGISTER

ADDRESS

R61448 (F008h)

GPIO register

WM2000

DESCRIPTION

4

3

2

1

0

GPIO_IN

GPIO_OE_CLR

GPIO_OE_SET

GPIO_OUT_CLR

GPIO_OUT_SET

0

0

0

0

0

Table 35 Register F008h GPIO Register

REGISTER

ADDRESS

R61449 (F009h)

GPIO

Configuration


5 GPIO_IN_INV_CLR 0

4 GPIO_IN_INV_SET 0

DESCRIPTION

Writing ‘1’ selects non-inverted GPIO input


Read value is '0'

Writing ‘1’ selects inverted GPIO input


Read value is the current status of the GPIO input inversion:

0 = GPIO input is not inverted

1 = GPIO input is inverted

Table 36 Register F009h GPIO Configuration

This field represents the current GPIO input value. It may be inverted, depending on the GPIO_IN_INV_* register settings

Writing ‘1’ configures the GPIO pin as an input.


Read value is '0'

Writing ‘1’ configures the GPIO pin as an output.


Read value is the current status of the GPIO pin configuration:

0 = GPIO is input

1 = GPIO is output



Read value is '0'



Read value is the current status of the GPIO output level:



REGISTER

ADDRESS

R61472 (F020h)

ANA GPIO Pad

Control


0 GP_OD_EN 0

DESCRIPTION

GPIO Output pin configuration

0 = CMOS

1 = Open-drain

In CMOS configuration, the GPIO pin is driven low or high, according to the commanded output condition.

In Open-drain configuration, the GPIO pin is driven low for logic ‘0’ output, and is tri-stated for logic ‘1’ output.

Table 37 Register F020h ANA GPIO Pad Control w PD, July 2012, Rev 4.1

45

WM2000

REGISTER

ADDRESS

R61473 (F021h)

ANA Line In

Volume


4:0 LINE_IN_VOL[4:0]

DESCRIPTION

0_0000 LINE IN gain setting

Inverting mode: non-linear gain curve

Non-Inverting mode: 12dB to 30dB in 3dB steps. Note that the default setting 00000 is not valid in this mode.

LIN_VOL Inverting(dB) Non-Inverting(dB)

5’b00000 -1.5 Not valid

5’b00001 -1.3 +12

5’b00010 -1.0 +15

5’b00011 -0.7 +18

5’b00100 -0.3 +21

5’b00101 +0.0 +24

5’b00110 +0.3 +27

5’b00111 +0.7 +30

5’b01000 +1.0 +30

5’b01001 +1.4 +30

5’b01010 +1.8 +30

5’b01011 +2.3 +30

5’b01100 +2.7 +30

5’b01101 +3.2 +30

5’b01110 +3.7 +30

5’b01111 +4.2 +30

5’b10000 +4.8 +30

5’b10001 +5.4 +30

5’b10010 +6.0 +30

5’b10011 +6.7 +30

5’b10100 +7.5 +30

5’b10101 +8.3 +30

5’b10110 +9.2 +30

5’b10111 +10.2 +30

5’b11000 +11.4 +30

5’b11001 +12.7 +30

5’b11010 +14.3 +30

5’b11011 +16.2 +30

5’b11100 +19.2 +30

5’b11101 +22.3 +30

5’b11110 +25.2 +30

5’b11111 +28.3 +30

Table 38 Register F021h ANA Line In Volume

REGISTER

ADDRESS

R61474 (F022h)

ANA Line In

Control (1)

1 LINE_IN_MUTE

0 LINE_IN_VOL_SHIFT

1

1

DESCRIPTION

Line mute

0 = Line channel un-mute

1 = Line channel mute

Line Volume Shift

0 = Line volume as set by LINE_IN_VOL

1 = Line volume reduced by 4.5dB

Note: this field has no effect in Differential Non-Inverting mode (LINE_IN_MODE=1X)

Table 39 Register F022h ANA Line In Control (1) w PD, July 2012, Rev 4.1

46

Production Data

REGISTER

ADDRESS

R61475 (F023h)

ANA Line In

Control (2)

3

2

1:0

LINE_IN_EN

LINE_IN_CMAMP

LINE_IN_MODE[1:0]

Table 41 Register F025h ANA MIC Volume

WM2000

0

0

01

DESCRIPTION

Line Input PGA Enable

0 = disabled

1 = enabled

Line Input Common Mode Amplifier Enable

0 = Disabled

1 = Enabled

Line Input PGA Mode

00 = Single Ended Inverting Mode


1X = Differential Non-Inverting Mode

Table 40 Register F023h ANA Line In Control (2)

REGISTER

ADDRESS

R61477 (F025h)

ANA MIC Volume


4:0 MIC_VOL[4:0]

DESCRIPTION

0_0000 This is the gain setting of the microphone input gain block for the MICN/MICP inputs. Non-linear gain curve

MIC_VOL Inverting(dB)

5’b00000 -1.5

5’b00001 -1.3

5’b00010 -1.0

5’b00011 -0.7

5’b00100 -0.3

5’b00101 +0.0

5’b00110 +0.3

5’b00111 +0.7

5’b01000 +1.0

5’b01001 +1.4

5’b01010 +1.8

5’b01011 +2.3

5’b01100 +2.7

5’b01101 +3.2

5’b01110 +3.7

5’b01111 +4.2

5’b10000 +4.8

5’b10001 +5.4

5’b10010 +6.0

5’b10011 +6.7

5’b10100 +7.5

5’b10101 +8.3

5’b10110 +9.2

5’b10111 +10.2

5’b11000 +11.4

5’b11001 +12.7

5’b11010 +14.3

5’b11011 +16.2

5’b11100 +19.2

5’b11101 +22.3

5’b11110 +25.2

5’b11111 +28.3 w PD, July 2012, Rev 4.1

47

WM2000

REGISTER

ADDRESS

R61478 (F026h)

ANA MIC Control

(1)


1 MIC_MUTE

0 MIC_VOL_SHIFT

Table 42 Register F026h ANA MIC Control (1)

1

1

Mic Mute

DESCRIPTION

0 = Mic channel un-mute

1 = Mic channel mute

This bit should be cleared to 0

REGISTER

ADDRESS

R61479 (F027h)

ANA MIC Control

(2)

3 MIC_EN 0

DESCRIPTION

2

1:0

MIC_IN_CMAMP

MIC_MODE [1:0]

0

10

Mic Input PGA Enable

0 = disabled

1 = enabled

This bit must be cleared to 0

Mic Input PGA Mode

00 = Reserved


1X = Reserved


REGISTER

ADDRESS

R61480 (F028h)

ANA MIC Control

(3)

0 LDO_EN 1 LDO enable.

1 = LDO enabled

0 = LDO disabled

DESCRIPTION


REGISTER

ADDRESS

R61481 (F029h)

ANA ADC 0

Control (1)

7 ADC_0_EN

3 ADC_0_DISOFF

Table 45 Register F029h ANA ADC 0 Control (1)

REGISTER

ADDRESS

R61484 (F02Ch)

ANA ADC 1

Control (1)

1 ADC_1_EN

0 ADC_1_DISOFF

Table 46 Register F02Ch ANA ADC 1 Control (1)

0

0

0

0

DESCRIPTION

Enables Noise Cancellation (MIC) ADC

0 = disabled

1 = enabled

This register bit must be set to 1.

DESCRIPTION

Enables Received Voice (LINE) ADC

0 = disabled.

1 = enabled.

This register bit must be set to 1. w PD, July 2012, Rev 4.1

48

Production Data

WM2000

(1)

REGISTER

ADDRESS

R61487 (F02Fh)

ANA DAC Control

4

3

DAC_EN

DACANRES

Table 49 Register F032h ANA PGA Gain

REGISTER

ADDRESS

R61491 (F033h)

ANA PGA Control

3 PGA_EN

0

0

0

DESCRIPTION

This enables the DAC

0 = disabled

1 = enabled

This connects the DAC outputs to VMID. Can be used to optimise pop-click performance during startup and shutdown.

0 = DAC muted

1 = Normal DAC operation

Table 47 Register F02Fh ANA DAC Control (1)

REGISTER

ADDRESS

R61489 (F031h)

ANA DAC Control

(3)


0 DAC_CLK_MODE

Table 48 Register F031h ANA DAC Control (3)

0

DESCRIPTION

This bit must be set to 1 for normal operation.

Default value 0.

REGISTER

ADDRESS

R61490 (F032h)

ANA PGA Gain

2:0 PGA_DAC_GAIN[2:0] 000

DESCRIPTION

This controls the gain of the ANC input to the output

PGA

000 = mute

001 = -12 dB

010 = -9 dB

011 = -6 dB

100 = -3 dB

101 = 0 dB

110 = 3 dB

111 = 6 dB

DESCRIPTION

2

1

0

PGA_LINE_MUTE

PGA_DAC_MUTE

PGA_LINE_0DB

1

1

0

This enables the output PGA

0 = disabled

1 = enabled

This mutes the LINE input to the output PGA

0 = not muted

1 = muted

This mutes the ANC input to the output PGA

0 = not muted

1 = muted

This controls the gain of the LINE input to the output

PGA.

0 = -6dB

1 = 0dB

Table 50 Register F033h ANA PGA Control w PD, July 2012, Rev 4.1

49

WM2000

REGISTER

ADDRESS

R61492 (F034h)

ANA Speaker

Control

5

4

3:2

1

0

SPK_EN

SPK_BYPS

SPK_MID_ADJ[1:0]

SPK_MUTE

SPK_OUT_EN

0

0

00

1

0

DESCRIPTION

This enables the speaker amp

0 = disabled

1 = enabled

Selects the ANC Bypass path

0 = Output is from the ANC engine and Output PGA

1 = Output is from LINP and LINN input pins

This adjusts the VMID of the speaker outputs. This should be set to as close to SPKVDD/2 as possible.

00 = 1.4V

01 = 1.5V

10 = 1.6V

11 = 1.7V

This bit must be set to 0 for normal operation. It may be set to 1 by the internal hardware sequencer during power-up or power down sequences.

This enables the output from the speaker amp

0 = disabled

1 = enabled

Table 51 Register F034h ANA Speaker Control

REGISTER

ADDRESS

R61493 (F035h)

ANA MIC Bias

Control

6

5

MIC_BIAS_EN

MIC_BIAS_VSEL

0

0

DESCRIPTION

Table 52 Register F035h ANA MIC Bias Control

REGISTER

ADDRESS

R61495 (F037h)

ANA Master Bias

Control


3

2:1

0

MASTER_BIAS_EN

MASTER_BIAS_ISEL[1:0]

MASTER_BIAS_POB_CTRL

0

10

0

DESCRIPTION

1: enables the Master Bias block. This is required for normal operation.

0: disables the Master Bias block.

This selects the master bias current, which can be used to optimise pop-click performance during startup / power down:

0b00: 50%

0b01: 75%

0b10: 100%

0b11: 150%

1: All bias supplies use fast bias. This can optimise pop-click performance during startup / power down.

0: All bias supplies use master bias. This is required for normal operation.

Table 53 Register F037h ANA Master Bias Control

Microphone Bias Enable

0 = OFF (high impedance output)

1 = ON

Microphone Bias Voltage Control

0 = 2.0V

1 = 2.1V

These values vary with AVDD, which is internally generated by the LDO referenced to DCVDD; the quoted figures are valid for DCVDD=1.8V w PD, July 2012, Rev 4.1

50

Production Data

REGISTER

ADDRESS

R61496 (F038h)

ANA IBIAS

Control

WM2000


0 MASTER_BIAS_STARTUP 0 1: Enables the fast bias. This can optimise pop-click performance during startup/power down.

0: Disables fast bias. Fast bias should be disabled for normal operation to save power.

Table 54 Register F038h ANA IBIAS Control

REGISTER

ADDRESS

R61497 (F039h)

ANA Thermal

Protection Control

1 TP_ENA

Table 55 Register F039h ANA Thermal Protection Control

REGISTER

ADDRESS

R61498 (F03Ah)

ANA Thermal

Protection Status

1

0

TP_WARN

TP_SHUT

0

0

0

DESCRIPTION

This enables the thermal protection

DESCRIPTION

A logic 1 indicates that the Thermal Warning level has been reached

A logic 1 indicates that the Thermal Shutdown level has been reached

Table 56 Register F03Ah ANA Thermal Protection Status

REGISTER

ADDRESS

R61499 (F03Bh)

ANA VMID Control

6 VMID_EN 0

5:4 VMID_RES[1:0]

3:2 VMID_SOFT[1:0]

1 VMID_BUFIO_EN

0 VMID_IO_EN

00

00

0

0

DESCRIPTION

This enables the VMID generator string, which may be used by the Internal Sequencer to optimise pop-click performance during startup/power down. It is only included in the register map for debug purposes.

This selects the value of the VMID ladder resistors, which may be used by the Internal Sequencer to optimise pop-click performance during startup/power down.

0b00: Reserved

0b01: 50k each (total 100k)



This selects the VMID Scurve generation time, which may be used by the Internal Sequencer to optimise pop-click performance during startup/power down.

00 = disabled

01 = fast

10 = nominal

11 = slow

This enables the VMID input keeper buffer, which may be used by the Internal Sequencer to optimise pop-click performance during startup/power down.

This connects VMID bias to the IO, which may be used by the Internal Sequencer to optimise pop-click performance during startup/power down.

Table 57 Register F03Bh ANA VMID Control w PD, July 2012, Rev 4.1

51

WM2000

REGISTER

ADDRESS

R61500 (F03Ch)

ANA RAM Power

Control

0 RAM_PWR_EN 1

DESCRIPTION

1: Supply power to ROM and data RAM.

0: Disable power to ROM and data RAM.

These memories should be switched off when the ANC engine is in standby mode to save power. Before clearing this bit to 0, the RAM contents must be backed up by the host.

Table 58 Register F03Ch ANA RAM Power Control

REGISTER

ADDRESS

R61952 (F200h)

Filter Control (1)

5 IIR_ENA_CLR 0

DESCRIPTION

4

3

2

1

0

IIR_ENA_SET

HPF1_ENA_CLR

HPF1_ENA_SET

HPF0_ENA_CLR

HPF0_ENA_SET

0

0

0

0

0

ANC Engine IIR Filter disable

Write '1' to disable the IIR.

Read value is '0'.

ANC Engine IIR Filter enable

Write '1' to enable the IIR.

Read value is current IIR_ENA value.

HPF1 Disable

Write '1' to disable High Pass Filter 1.

Read value is '0'.

HPF1 Enable

Write '1' to enable High Pass Filter 1.

Read value is current HPF1_ENA value.

HPF0 Disable

Write '1' to disable High Pass Filter 0.

Read value is '0'.

HPF0 Enable

Write '1' to enable High Pass Filter 0.

Read value is current HPF0_ENA value.

Table 59 Register F200h Filter Control (1)

REGISTER

ADDRESS

R61954 (F202h)

Filter Control (3)

3 NC_GAIN_UPD

2 NC_HPF1_UPD

1

0

NC_HPF0_UPD

IIR_UPD

0

0

0

0

DESCRIPTION

Write '1' to copy the standby NC gain coefficients into the active coefficient registers.

Write '1' to copy the standby NC high pass filter 1 coefficients into the active coefficient registers.

Write '1' to copy the standby NC high pass filter 0 coefficients into the active coefficient registers.

Write '1' to update the coefficients. This must be done after coefficients are downloaded.

Table 60 Register F202h Filter Control (3) w PD, July 2012, Rev 4.1

52

Production Data

WM2000

APPLICATIONS INFORMATION

The noise cancellation performance of a handset incorporating WM2000 depends on 3 key factors:



Speaker and microphone selection



Acoustics and plastics design

 design

SPEAKER AND MICROPHONE SELECTION

There are several factors which affect the suitability of a speaker or microphone for noise cancellation, including the following:

1. The frequency response of speaker and microphone components is critical, with respect to bandwidth, frequency response, phase response, speaker impedance variation, and microphone sensitivity/noise. These parameters must be measured using free field analysis.

2. The unit-unit tolerance of speaker and microphones must be within the tolerance specified by Wolfson.

3. The speaker and microphone pins (+/-) need to be labelled to ensure the phase is consistent in all handsets.

Please contact Wolfson for assistance with speaker and microphone selection.

ACOUSTICS AND PLASTICS DESIGN

There are several factors which affect the suitability of handset design for noise cancellation. Correct acoustic and plastics design optimises the response and isolation of the speaker and microphone components. Wolfson can provide applications information which covers these factors in more detail.

These factors include the following

1. In general, the speaker should be sited in the centre of the handset (i.e. an equal distance between the left and right hand sides of the handset), and at least 6mm from the top of the handset.

2. Correct placement of noise microphones with respect to the loudspeaker is required. There is a minimum and maximum distance specified, and the distance between microphone and speaker should be equal on both sides.

3. Mic placement symmetry is important with respect to speaker. As well as being placed an equal distance from the speaker, the inclusion of a jack socket or push button between one mic and the speaker can affect the performance due to imbalances in acoustic leakage within the handset body.

4. If microphones are likely to be covered by the user’s fingers during normal usage of the handset,

5. Internal acoustic sealing of speaker and mics is essential to avoid acoustic leakage between the speaker and microphone. w PD, July 2012, Rev 4.1

53

WM2000

RECOMMENDED EXTERNAL COMPONENTS

Figure 19 External Components Diagram

Notes:

1. AC coupling capacitors are required for LINP, LINN, and MICP/MICN as shown in the “Input Signal Path” section.

2. It may be possible to reduce the value of AC coupling capacitors for LINP, LINN, depending on voice bandwidth requirements.

3. SCAN_MODE must be grounded directly, not through a resistor, to avoid latch up issues. w PD, July 2012, Rev 4.1

54

Production Data

WM2000

BILL OF MATERIALS

U1

C9

C8

C10

C4

C6

C7

C5

C3

C2

C1

0.47uF 0603 SMD Ceramic Capacitor 16V X7R

1uF 0603 SMD Ceramic Capacitor 6.3V X5R


WM2000 Receiver Driver with Ambient Noise

Cancellation

0.1uF 0603 SMD Ceramic Capacitor 16V X7R





Table 61 Bill of Materials for Support Circuit

Kemet

Murata

Murata

Wolfson Microelectronics

Phycomp

0.1uF 0603 SMD Ceramic Capacitor 16V X7R Phycomp

0.1uF 0603 SMD Ceramic Capacitor 16V X7R Phycomp

Murata

Murata

Murata

Murata

NUMBER

C0603X474K4RAC

GRM188R60J105KA01D

GRM188R60J105KA01D

WM2000GECON

06032R104K7B2

06032R104K7B2

06032R104K7B2

GRM188R60J105KA01D

GRM188R60J105KA01D

GRM188R60J105KA01D

GRM188R60J105KA01D w PD, July 2012, Rev 4.1

55

WM2000

PACKAGE DIMENSIONS

B: 25 BALL W-CSP PACKAGE 2.552 X 2.602 X 0.7mm BODY, 0.50 mm BALL PITCH DM056.B

6

D

2 g A2

A

DETAIL 2

D

E

B

C

A

5 4 3 e

D1

BOTTOM VIEW

2 1

DETAIL 1 e

5

E1

4

A1

CORNER

2 X

2 X

0.10

Z

0.10

Z

E bbb Z

1

Z

A1

DETAIL 2

TOP VIEW f1

SOLDER BALL f2 h

DETAIL 1

Symbols

A

A1

A2

D

D1

E

E1 e f1 f2 g h

MIN

0.615

0.225

0.355

0.266

0.291

0.035

Dimensions (mm)

NOM

0.7

0.250

0.380

2.552 BSC

2.00 BSC

2.602 BSC

2.00 BSC

MAX

0.785

0.275

0.405

0.50 BSC

0.276

0.301

0.070

0.314 BSC

0.105

NOTE

5

NOTES:

1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING.

3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE.

4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.

5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.

6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C.


56

Production Data

WM2000

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.

ADDRESS

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: sales@wolfsonmicro.com


57

WM2000

REVISION HISTORY

DATE REV ORIGINATOR

19/07/10 4.0 PH

CHANGES

Updated to Production Data status.

Typical power consumption figures (Standby, Bypass, Powered down) updated.

Standby power consumption (front page) updated

20/07/12 4.1

26/07/12 4.1

JMacD Package Diagram updated – f1 and f2 nominal dimensions added.

JMacD Description, 3 rd

para updated, p1.1 w PD, July 2012, Rev 4.1

58

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Cirrus Logic :

WM2000ECS/RV

WM2000 - Mouser Electronics

Handset Receiver Speaker Driver with Ambient Noise

Cancellation

TEST TYPE

TERMINOLOGY

MASTER CLOCK

CONTROL INTERFACE

TYPICAL APPLICATION CONFIGURATION

ANC (AMBIENT NOISE CANCELLATION)

TYPICAL NOISE CANCELLATION PERFORMANCE

AMBIENT NOISE CANCELLATION (ANC) ENGINE

ANC ENGINE OPERATING MODES

Shutdown Mode:

Device Ready Mode:

ANC Active Mode (Dynamic Control of ANC):

Standby Mode:

Bypass Mode:

ANC ENGINE MODE TRANSITIONS

Power_up Transition

Power_down Transition

Standby_Entry Transition

Standby_Exit Transition

Bypass_Entry Transition

Bypass_Exit Transition

ANC ACTIVE WATCHDOG COUNTER

INPUT SIGNAL PATH

AMBIENT NOISE (MICROPHONE) INPUT

MIC INPUT PGA ENABLE

MIC INPUT PGA CONFIGURATION

MIC INPUT PGA VOLUME CONTROL

MICROPHONE BIAS

RECEIVED VOICE (LINE) INPUT

LINE INPUT PGA ENABLE

LINE INPUT PGA CONFIGURATION

SINGLE-ENDED INVERTING MODE

DIFFERENTIAL INVERTING MODE

DIFFERENTIAL NON-INVERTING MODE

INPUT PGA VOLUME CONTROL

LINE INPUT COMMON MODE AMPLIFIER

ANALOGUE TO DIGITAL CONVERTERS (ADC)

DIGITAL TO ANALOGUE CONVERTER (DAC)

OUTPUT SIGNAL PATH

OUTPUT PGA MIXER

BYPASS PATH

SPEAKER OUTPUT

LDO REGULATOR

SYSTEM CLOCKING

GENERAL PURPOSE INPUT/OUTPUT

CONTROL INTERFACE

SYSTEM CLOCKING DURING CONTROL INTERFACE ACCESSES

SINGLE WRITE AND READ ACCESSES

MULTIPLE WRITE AND READ ACCESSES

SET AND CLEAR REGISTER BIT PAIRS

EXAMPLE

SOFTWARE RESET AND DEVICE ID

POWER-ON RESET (POR)

POWER SUPPLY SEQUENCE

REGISTER DEFAULT VALUES

THERMAL SHUTDOWN

REGISTER BITS BY ADDRESS

SPEAKER AND MICROPHONE SELECTION

ACOUSTICS AND PLASTICS DESIGN

RECOMMENDED EXTERNAL COMPONENTS

BILL OF MATERIALS

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Cirrus Logic :

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