OpenStax-CNX module: m11386
1
Standing Waves/VSWR
∗
Bill Wilson
This work is produced by OpenStax-CNX and licensed under the
Creative Commons Attribution License 1.0
†
Abstract
This module covers the idea of voltage standing wave ratio (VSWR).
A Standing Wave Pattern
Figure 1
In making this plot (Figure 1: A Standing Wave Pattern), we have made use of the fact that the
propagation constant β can also be expressed as 2π
λ , and so for the independent variable, instead of showing
s in meters or whatever, we normalize the distance away from the load to the wavelength of the excitation
signal, and hence show distance in wavelengths. What we are showing here is called a standing wave.
There are places along the line where the magnitude of the voltage |V (s) | has a maximum value. This is
where V + and V − are adding up in phase with one another, and places where there is a voltage minimum,
where V + and V − add up out of phase. Since |V − | = |Γν ||V + |, the maximum value of the standing wave
pattern is 1 + |Γν | times |V + | and the minimum is 1 − |Γν | times |V + |. Note that anywhere on the line, the
voltage is still oscillating at eiωt , and so it is not a constant, it is just that the magnitude of the oscillating
signal changes as we move down the line. If we were to put an oscilloscope across the line, we would see an
AC signal, oscillating at a frequency ω .
A number of considerable interest is the ratio of the maximum voltage amplitude to the minimum voltage
amplitude, called the voltage standing wave ratio, or VSWR for short. It is easy to see that:
VSWR =
∗
†
Version 1.2: Jun 23, 2003 12:00 am +0000
http://creativecommons.org/licenses/by/1.0
http://cnx.org/content/m11386/1.2/
1 + |Γ|
1 − |Γ|
(1)
OpenStax-CNX module: m11386
2
Note that because |Γν | ∈ [0, 1], VSWR ∈ [1, ∞].
Although Figure 1 (A Standing Wave Pattern) looks like the standing wave pattern is more or less
sinusoidal, if we increase |Γ| to 0.8, we see that it most denitely is not. There is also a temptation to say
that the spacing between minima (or maxima) of the standing wave pattern is λ , the wavelength of the
signal, but a closer inspection of either Figure 1 (A Standing Wave Pattern) or Figure 2 (Standing Wave
Pattern with a Larger Reection Coecient), shows that in fact the spacing between features is only half
λ
a wavelength, or λ2 . Why is this? Well, φ (s) goes as −2βs and β = 2π
λ , and so every time s increases by 2 ,
φ (s) decreases by 2π and we have come one full cycle on the way |V (s) | behaves.
Standing Wave Pattern with a Larger Reection Coecient
Figure 2
Now let's go back to the Crank Diagram. At the position shown, we are at a voltage maximum, and
just equals the VSWR.
Z(sVmax )
Z0
=
VSWR
=
1+|Γν |
1−|Γν |
Z(s)
Z0
(2)
Note also that at this particular point, that the voltage and current phasors are in phase with one another
(lined up in the same direction) and hence the impedance must be real or resistive.
We can move further down the line, and now the V (s) phasor starts shrinking, and the I (s) phasor
starts to get bigger Figure 3 (Moving Further Down the Line).
http://cnx.org/content/m11386/1.2/
OpenStax-CNX module: m11386
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Moving Further Down the Line
Figure 3:
Moving further down the line from a
Vmax
If we move even further down the line, we get to a point where the current phasor is now at a maximum
value, and the voltage phasor is at a minimum value Figure 4 (Moving Even Further Down the Line). We
are now at a voltage minimum, the impedance is again real (the voltage and current phasors are lined up
with one another, so they must be in phase) and
Z (sVmin )
=
=
1
VSWR
1−|Γν |
1+|Γν |
(3)
Moving Even Further Down the Line
Figure 4:
Crank diagram at a
Vmin
The only problem we have here is that except at a voltage minimum or maximum, nding Z (s) from the
crank diagram is not very straightforward, since the voltage and current are out of phase, and dividing the
two vectors becomes somewhat tedious.
http://cnx.org/content/m11386/1.2/