A 60MHz 50W Fine-Grain Package-Integrated VR Powering a CPU from 3.3V Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Circuit Research Lab, Intel Labs, Intel Corporation Motivation y Reduce platform power delivery complexity & area y Reduce load line & save power y Enable fine-grain power management Example: Dell* XPS* M1210 Power delivery top bottom *Other names and brands may be claimed as the property of others 2 Intel Labs Package-Integrated VR Proof of Concept y Advantage of on-package 2nd VR stage – Single 3.3V input, lower current going into the package – 2-stage conversion is more efficient – Near-load VR allows fast response, reduced load line y VR test chip on the CPU package (MCP) – VR chip/w cascode bridges manufactured in 130nm CMOS – 60MHz switching frequency allows miniaturization – Mounted on modified CPU package/w package trace inductors or powdered-iron core inductors 3 Intel Labs Package-Integrated VR with Intel® Core™2 Duo Processor package trace inductors U CP CP U IV IV R R discrete inductors y Vin=3.3V, Vout=0...1.6V (VID), 10MHz...100MHz, TDC=50A / 75A peak, size=37.6mm2, 130nm CMOS y Inductors: 0508-size discrete powdered iron core or package-trace air core 4 Intel Labs FUNCTIONAL BLOCK DIAGRAM VIN Integrated VR Architecture y Type-3 compensator XBR[0] Ramp Gen. XBR[1] x0.8 OV 1.65V LVR XBR[2] 8b DAC XBR[3] VRef VDA[7:0] +/- off. PWM compensator VSNS1 GSNS1 x0.8 XBR[4] 2x Digital Ramp Gen. 2x Analog XDPSLP XPSI_B XPWGD Power Mode LUT y Progr. ramp rate y Progr. load line XVID[3] XVID[4] compensator VSNS2 GSNS2 x0.8 PWGD2 XBR[8] Ramp Gen. EN XBR[10] 8b DAC XBR[11] VRef VDA[7:0] +/- off. VID Decoder XBR[9] x0.8 OV PWM compensator UV XBR[12] VDA[7:0] [*] G.Schrom et al. APEC 2007 Intel Labs Ramp Gen. XBR[13] x0.8 OV Spread Spectrum Generator VSNS3 GSNS3 x0.8 PWGD3 XVID[0] XCLK PWM Delay XVID[2] XVID[1] XBR[7] VRef UV XVRON XVID[6] XBR[6] 8b DAC VDA[7:0] +/- off. 1.65V Bandap Reference XBR[5] x0.8 OV Test Port GND 5 VSNS0 GSNS0 x0.8 PWGD1 XVID[5] y Spread spectrum EMI control PWGD0 UV y Single-output 16-phase mode/w load balancing y Cascode bridges [*] compensator UV 1.65V LVR Control Registers y Four voltage domains, 16 phases (4x4) y Digital voltage control VIN/2 LVR XBR[14] 8b DAC VDA[7:0] +/- off. XBR[15] VRef PWM Efficiency Measurements Pkg. air core inductors 90% 90% 85% Efficiency Efficiency 85% 0508 pwdr Fe core inductors 80% 100% activation load adaptive 75% 70% 80% 100% activation load adaptive 75% 70% 0 10 20 30 40 50 60 70 80 Load Current [A] 0 10 20 30 40 50 60 70 80 Load Current [A] y Package embedded air core inductors: 84.9% y Discrete powdered Fe core inductors: 87.9% y Load adaptive bridge activation improves by >10% 6 Intel Labs Performance Output Voltage Ramp Rate 1V Performance 0.5V 1µs SpeedStep® Voltage Transitions CRL low latency: less waste Time demand available wasted Time y Fast output voltage ramp rate: >500mV/μs y Time-domain fine-grain power management saves power 7 Intel Labs Transient Performance Integrated VR 10mV 2nd droop 29mV 3rd droop 52mV MBVR 2µs 8 Intel Labs Load-line set to “0” y 2nd droop: reduced to 10mV y 3rd droop: eliminated y Reduced load line saves power Impedance Measurement 0.012 CPU/w package-integrated VR Impedance [Ohm] 0.010 CPU on std. package 0.008 0.006 0.004 0.002 0.000 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency [Hz] y Load line set to 0.5mΩ, measured 0.42mΩ [A.Waizman et al. EPEP 2004] using IFDIM method 9 Intel Labs EMI Performance EMI Level [dBµV/m] 60 Laptop with IVR/w discrete ferrite inductors Laptop with IVR/w package trace air-core inductors Unmodified laptop 50 40 FCC Limit 30 20 10 5 30M 50M 70M 100M 200M Frequency [Hz] 300M 500M 700M 1G y Laptop modified to use IVR-powered CPU y CISPR 22B test in 3m EMI chamber, EMC worst-case y Compliant with spread-spectrum enabled 10 Intel Labs Conclusion y A high-performance package-integrated VR was demonstrated powering an Intel® Core™2 Duo processor from 3.3V – Peak efficiency of 85-88% – Fast slew rate of >500mV/μs – Excellent droop & load line of <0.5mΩ 11 y A laptop modified to use the IVR-powered CPU booted successfully y The power density at 50W is 11.8kW/in3 Intel Labs