Application Note
AN35
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San Diego, CA 92121, USA
Tel: 858-731-9400
Fax: 858-731-9499
www.psemi.com
Configuring the PE42850 as an SP3T or SP5T
Introduction
Summary
PE42850 is designed to be a high power
(~30 Watts) SP5T switch. A popular use of this
switch is in land mobile radio (LMR) applications,
where the number of bands required can vary
depending on the region of operation. In order to
support these multiple use cases, unused switch
ports can be either properly terminated or left
open with no discernible effect on switch
performance.
 Configure PE42850 as an SP3T
 Compare SP3T simulated performances with
Alternatively, it is possible to optimize its TX
insertion loss performance in a lower throw SP3T
configuration by making some circuit
modifications around the RF pins. This should be
accompanied by the use of corresponding control
logic options already designed into the part.
Besides s-parameters, all other performance
specifications will remain the same as per the
datasheet, i.e. PMAX, compression, linearity,
switching time, etc. will be unchanged.
DUT only (no matching) vs transmission line
matching vs lumped inductor matching
 Show measured performance with inductor
match for SP3T
 Show simulated and measured performance
with similar methodology for SP5T
configuration
This application note details the circuit options
recommended for SP3T and SP5T operation and
has simulated and measured data to back them
up.
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AN35
Application Note
Configure PE42850 as an SP3T
To configure PE42850 as an SP3T, it is recommended to tie TX1 (Pin 2) to TX2 (Pin 4) and TX3 (Pin 21) to
TX4 (Pin 23) as shown in Figure 1.
Figure 1. Layout
TX4
(Pin 23)
TX1
(Pin 2)
High
Impedance
Trace
High
Impedance
Trace
TX3
(Pin 21)
TX2
(Pin 4)
Similar to the SP5T configuration, narrow high-Z (~100Ω) traces are used near each port to improve
impedance matching for PE42850 as an SP3T. A trace length of 250 mil is optimum for matching each port.
Alternatively, if space is a constraint, a 3.6 nH inductor can be used instead of the narrow trace at each port
to provide the required match.
The truth table is obtained from the datasheet.
Table 1. Truth Table
Path
V3
V2
V1
ANT – RX Attenuated
L
L
L
ANT – TX1
L
L
H
L
H
L
L
H
H
ANT – RX
H
L
L
ANT – TX3
H
L
H
H
H
L
H
H
H
ANT – TX2
ANT – TX1 and TX2
1
ANT – TX4
1
ANT – TX3 and TX4
Note: In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3 and
TX4 are tied respectively.
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Document No. DOC-61890-1 │ UltraCMOS® RFIC Solutions
©2014 Peregrine Semiconductor Corp. All rights reserved.
AN35
Application Note
PE42850 Performance as an SP3T
Simulation results for the SP3T case:
Figures 2–4 show circuits used to simulate SP3T performance in ADS. The first circuit (Figure 2) only
includes the SP3T s-parameter (vector de-embedded DUT-only) file. The 2nd circuit (Figure 3) includes the
SP3T s-parameter file and an ADS Microstrip Transmission line (TL), modeled after Peregrine’s PE42850
evaluation board’s thin trace, with a length of 250 mil. The 3rd circuit (Figure 4) includes the SP3T sparameter file and a 3.6 nH lumped inductor model from Coilcraft. Figure 5 shows the simulated TX insertion
losses of the aforementioned three cases. The matching is observed to significantly reduce the insertion loss,
especially at higher frequencies. There is also a significant improvement in the return loss, as shown in
Figure 6.
Comparable performance improvement is obtained by using either the inductor or TL match.
Figure 2. DUT Only
–
+
Term
Term4
Num = 4
Z = 50Ω
S-Parameters
S_Param
SP1
Start = 0.01 GHz
Stop = 2 GHz
Step = 10 MHz
4
1
+
Term
Term1
Term
Term1
Num = 1
Z = 50Ω
– Z = 50Ω
Num = 1
2
3
Ref
+
Term
Term2
Num = 2
S4P
SNP1
– Z = 50Ω
+
Term
Term3
– Num = 3
Z = 50Ω
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AN35
Application Note
Figure 3. DUT + TL Matching
–
Term
Term8
MSub
MSUB
MSub1
Num = 8
Z = 50Ω
+
H = 28.0 mil
Er = 4.3
Mur = 1
Cond = 6E+7
T = 2.1 mil
TanD = 0.01
MLIN
TL4
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
4
1
+
Term
Term5
Num = 5
Z = 50Ω
MLIN
TL6
–
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
2
3
+
Ref
S4P
SNP2
Term
Term6
MLIN
TL7
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
MLIN
TL5
–
Num = 6
Z = 50Ω
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
+
Var Eqn VAR
VAR1
Term
Term7
TxLen = 250 {t}
–
Num = 7
Z = 50Ω
Figure 4. DUT + Lumped Inductance Matching
–
+
Term
Term12
Num = 12
Z = 50Ω
CCI_0402CS
SNP10
File = “04CS3N6.S2P”
Type = 3.6 nH
4
+
Term
Term9
Num = 9
Z = 50Ω
–
1
CCI_0402CS
SNP14
File = “04CS3N6.S2P”
Type = 3.6 nH
2
3
Ref
S4P
SNP12
CCI_0402CS
SNP15
File = “04CS3N6.S2P”
Type = 3.6 nH
+
Term
Term10
–
Num = 10
Z = 50Ω
CCI_0402CS
SNP11
File = “04CS3N6.S2P”
Type = 3.6 nH
+
Term
Term11
–
Num = 11
Z = 50Ω
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Document No. DOC-61890-1 │ UltraCMOS® RFIC Solutions
©2014 Peregrine Semiconductor Corp. All rights reserved.
AN35
Application Note
Figure 5. Insertion Loss
Figure 6. Return Loss
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AN35
Application Note
Measured SP3T Performance with Inductor Match
Figure 7 shows the measured results for the SP3T with L = 3.6 nH when ANT to TX1 and TX2 is ON. The
inductor is in an 0402 package. At 870 MHz, insertion loss = 0.28 dB and return loss is around 28 dB.
Although the measured insertion loss with the discrete inductor match is higher than the simulated result, it
still results in a significant improvement over the SP5T case (see “Simulation and Measurement for SP5T
Configuration”).
Figure 7. Measured IL and RL (TX Port)
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Document No. DOC-61890-1 │ UltraCMOS® RFIC Solutions
©2014 Peregrine Semiconductor Corp. All rights reserved.
AN35
Application Note
Simulation and Measurement for SP5T Configuration
Simulation results for SP5T case:
Figures 8–10 show circuits used to simulate SP5T performance in ADS. The methodology used here is very
similar to the SP3T case. The value of the matching inductor however is reduced to 2.4 nH (and alternatively
the TL length is 200 mil, exactly as in the PE42850 EVB). Figure 11 shows the TX insertion loss of the three
cases. Again, the matching is observed to significantly reduce insertion loss, especially at higher frequencies.
This is accompanied by a significant improvement in the return loss, as shown in Figure 12.
As before, comparable performance is obtained by using either the inductor or TL match.
Figure 8. DUT Only
–
+
Term
Term6
Num = 6
Z = 50Ω
S-Parameters
S_Param
SP1
Start = 0.01 GHz
Stop = 2 GHz
Step = 10 MHz
6
+
Term
Term1
Num = 1
Z = 50Ω
1
5
2
4
3
–
+
Term
Term5
Ref
–
Num = 5
Z = 50Ω
S6P
SNP1
+
+
Term
Term2
–
Num = 2
Z = 50Ω
Term
Term4
+
–
Num = 4
Z = 50Ω
Term
Term3
–
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Num = 3
Z = 50Ω
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AN35
Application Note
Figure 9. DUT + TL Match
–
Term
Term12
+
Var Eqn VAR
VAR1
MSub
MSUB
MSub1
Num = 12
Z = 50Ω
H = 28.0 mil
Er = 4.3
Mur = 1
Cond = 6E+7
T = 2.1 mil
TanD = 0.01
MLIN
TL11
TxLen = 200 {t}
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
6
1
+
MLIN
TL7
Term
Term7
Num = 7
Z = 50Ω
–
5
2
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
MLIN
TL10
+
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
4
3
S6P
SNP8
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
MLIN
TL9
Ref
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
MLIN
TL12
Subst = “MSub1”
W = 12.0 mil
L = TxLen mil
Term
Term5
–
+
MLIN
TL8
Num = 5
Z = 50Ω
Term
Term11
–
Num = 11
Z = 50Ω
+
Term
Term10
+
–
Num = 10
Z = 50Ω
Term
Term9
Num = 9
Z = 50Ω
–
Figure 10. DUT + Lumped Inductance Match
–
Term
Term18
Num = 18
Z = 50Ω
+
CCI_0402CS
SNP17
File = “04CS3N4.S2P”
Type = 2.4 nH
6
+
Term
Term13
Num = 13
Z = 50Ω
–
1
CCI_0402CS
SNP20
5
2
File = “04CS3N4.S2P”
Type = 2.4 nH
CCI_0402CS
SNP19
File = “04CS3N4.S2P”
Type = 2.4 nH
+
Term
Term14
Num = 14
– Z = 50Ω
CCI_0402CS
SNP21
4
3
CCI_0402CS
SNP16
Ref
File = “04CS3N4.S2P”
Type = 2.4 nH
+
Term
Term17
Num = 17
– Z = 50Ω
File = “04CS3N4.S2P”
Type = 2.4 nH
S6P
SNP15
CCI_0402CS
SNP18
File = “04CS3N4.S2P”
Type = 2.4 nH
+
+
Term
Term16
Num = 16
– Z = 50Ω
Term
Term15
– Num = 15
Z = 50Ω
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AN35
Application Note
dB(S(14,13))_InductorMatch
dB(S(8,7))_TxLineMatch
dB(S(2,1))_DUT_ONLY
Figure 11. Insertion Loss
dB(S(13,13))_InductorMatch
dB(S(7,7))_TxLineMatch
dB(S(1,1))_DUT_ONLY
Figure 12. Return Loss
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AN35
Application Note
Figure 13 shows the measured results for SP5T with L = 2.4 nH at ANT and TX2. The inductor is in an 0402
package. At 870 MHz, insertion loss = 0.38 dB and return loss is around 20 dB. The measured insertion loss
with a discrete inductor match is quite close to the simulated data.
Figure 13. Measured IL and RL (TX Port)
Figure 14 shows an overlay comparison of TX insertion losses obtained in both the SP3T and SP5T setup,
and highlights the improvement of the matched SP3T over the matched SP5T. As can be seen, it is possible
to obtain better than 25% improvement over the band by using the modified layout and matching of the SP3T
configuration. While this measured data is specific to a lumped match, similar improvement is also seen with
the distributed match.
Figure 14. Measured IL (SP3T vs. SP5T)
0
40
‐0.05
35
‐0.1
‐0.15
‐0.2
‐0.25
SP3T
‐0.3
SP5T
‐0.35
IL Improvement (%)
Insertion Loss (dB)
Insertion Loss: SP3T vs SP5T (Lumped Inductor match) % Insertion Loss Improvement of SP3T over SP5T (Lumped Inductor Match)
30
25
20
15
10
% IL
Improvement
5
‐0.4
0
‐0.45
0
0.2
0.4
0.6
0.8
1
1.2
Frequency (GHz)
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1.4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Frequency (GHz)
Document No. DOC-61890-1 │ UltraCMOS® RFIC Solutions
©2014 Peregrine Semiconductor Corp. All rights reserved.
AN35
Application Note
Conclusion
This application note provides information on how to configure PE42850 as an SP3T or SP5T switch. Its
performance is optimized by providing inductive matching of a distributed or lumped element type. As an
SP3T switch, further TX insertion loss improvement can be realized by some circuit modification around the
RF pins, coupled with alternative control logic options already provided in the datasheet. In the modified SP3T
configuration, we see a >25% improvement in insertion loss compared to the SP5T configuration.
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits
described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
following U.S. Patents: http://patents.psemi.com.
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