Order N ◦ : 4479
Thesis in Co-tutele
with
University of Bordeaux
Physics Science and Engineering Doctorate School
and
University of Modena and Reggio Emilia
Information and Communications Technology Doctorate School cycle 24
Director: Giorgio Matteo VITETTA
presented by
Paolo LUCCHI
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
in: Electronics and Telecommunications
—————————
Frequency generation for mm-Wave
and satellite applications
—————————
Discussing: 8 February 2012
Commission:
Prof. Andrea BONI
Prof. Thierry PARRA
Prof. Mattia BORGARINO
Prof. Jean-Baptiste BEGUERET
Prof. Fausto FANTINI
Prof. Yann DEVAL
University
University
University
University
University
University
of
of
of
of
of
of
Parma
Paul Sabatier
Modena and Reggio Emilia
Bordeaux
Modena and Reggio Emilia
Bordeaux
Examinator
Examinator
Advisor
Advisor
N ◦ d’ordine : 4479
Tesi in Co-tutela
tra
Università di Bordeaux
Scuola di Dottorato delle Scienze Fisiche e dell’Ingegneria
e
Università di Modena e Reggio Emilia
Scuola di Dottorato dell’Informazione e della Tecnologia della Comunicazione 24 ciclo
Direttore: Giorgio Matteo VITETTA
presentata da
Paolo LUCCHI
per conseguimento del titolo di
Dottore di Ricerca
in: Elettronica e Telecomunicazioni
—————————
Generazione di frequenza per applicazioni
satellitari e a onde millimetriche
—————————
Discussa l’ 8 febbraio 2012
Commissione:
Prof. Andrea BONI
Prof. Thierry PARRA
Prof. Mattia BORGARINO
Prof. Jean-Baptiste BEGUERET
Prof. Fausto FANTINI
Prof. Yann DEVAL
Università
Università
Università
Università
Università
Università
di
di
di
di
di
di
Parma
Paul Sabatier
Modena e Reggio Emilia
Bordeaux
Modena e Reggio Emilia
Bordeaux
Esaminatore
Esaminatore
Relatore
Relatore
N ◦ d’ordre : 4479
Thèse en Co-tutele
avec
Université de Bordeaux
Ecole Doctorale des Sciences Physiques et de l’Ingenieur
et
Université de Modène et Reggio Émilie
Ecole Doctorale de l’Information et de la Technolgie de la Comunication cycle 24
Directeur: Giorgio Matteo VITETTA
présentée par
Paolo LUCCHI
Pour obtenir le grade de
Docteur
en: Électronique
—————————
Génération de fréquences pour
applications millimétrique et satellite
—————————
Soutenance prévue le 8 Février 2012
Commissions:
Prof. Andrea BONI
Prof. Thierry PARRA
Prof. Mattia BORGARINO
Prof. Jean-Baptiste BEGUERET
Prof. Fausto FANTINI
Prof. Yann DEVAL
Université de Parma
Université de Paul Sabatier
Université de Modène et Reggio Émilie
Universitéde Bordeaux
Université de Modène et Reggio Émilie
Université de Bordeaux
Rapporteur
Rapporteur
Directeur de thèse
Directeur de thèse
to Me. . .
“stay hungry, stay foolish”
Steve Jobs
Contents
Abstract
1
1 Introduction
3
2 Ku band Oscillator
2.1 DVB-S2 standard . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Forward Error Correction (FEC) and modulation . . . .
2.1.2 Adaptive Coding and Modulation for one-to-one services
2.2 CMOS oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Oscillation amplitude . . . . . . . . . . . . . . . . . . .
2.2.2 Phase noise minimization . . . . . . . . . . . . . . . . .
2.2.3 CMOS Voltage Controlled Oscillator . . . . . . . . . . .
2.3 Quadrature Voltage Controlled Oscillator . . . . . . . . . . . .
2.3.1 Circuit design . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Measurements results . . . . . . . . . . . . . . . . . . .
3 millimeter Wave PLL
3.1 Phase-Locked Loop . . . . . . . . . . . . . . . . . . .
3.1.1 PLL linear model . . . . . . . . . . . . . . . .
3.2 Frequency Divider . . . . . . . . . . . . . . . . . . .
3.2.1 Static Frequency Divider . . . . . . . . . . .
3.2.2 True Single Phase Clock . . . . . . . . . . . .
3.2.3 Regenerative frequency dividers . . . . . . . .
3.2.4 Injection Locking Frequency Dividers . . . .
3.3 Millimeter Wave IC Applications . . . . . . . . . . .
3.3.1 Millimeter wave applications at 60 GHz . . .
3.3.2 Millimeter wave automotive radar sensors . .
3.3.3 Millimeter wave imaging in the 94 GHz band
3.4 mmW PLL state of the art . . . . . . . . . . . . . .
i
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7
7
8
13
15
17
18
19
21
22
26
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31
31
33
38
38
40
42
43
44
45
53
57
60
Contents
3.5
3.6
3.7
3.8
Frequency planning . . . . . . . . . . . . . . .
60 GHz Voltage Controlled Oscillator . . . . .
3.6.1 Inversion mode MOS varactor . . . . .
3.6.2 Circuit design . . . . . . . . . . . . . .
3.6.3 Layout . . . . . . . . . . . . . . . . . .
3.6.4 Measurements results . . . . . . . . .
Divided by 2 LC prescaler . . . . . . . . . . .
3.7.1 Circuit Design . . . . . . . . . . . . .
3.7.2 Measurement Results . . . . . . . . .
Divided-by-2 Injection-Locked Ring Oscillator
3.8.1 Circuit design . . . . . . . . . . . . . .
3.8.2 Post layout simulations . . . . . . . .
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Frequency Divider
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63
64
64
66
69
70
74
74
77
82
83
84
4 Conclusions
87
Publications
89
Acronyms
91
Bibliography
ii
Frequency generation for mm-Wave and satellite applications
105
List of Figures
1.1
1.2
Frequency division duplexing transceiver block diagram . . . . . . . . . .
General block diagrams of a CPPLL . . . . . . . . . . . . . . . . . . . . .
4
4
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
Functional block diagram of the DVB-S2 System characteristic. . . . . . .
The four possible DVB-S2 constellations before physical layer scrambling.
Pictorial representation of the physical-layer framing structure. . . . . . .
Required C/N versus spectrum efficiency on the AWGN channel. . . . . .
Block diagram of a DVB-S2 ACM link. . . . . . . . . . . . . . . . . . . . .
Ideal inductor capacitor resonator. . . . . . . . . . . . . . . . . . . . . . .
Tank series and parallel losses. . . . . . . . . . . . . . . . . . . . . . . . .
(a) Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit schematic of negative resistance LC CMOS Oscillator. . . . . . . .
Schematic diagram of a CMOS Voltage Controlled Oscillator . . . . . . .
VCO which isolates the voltage across the LC tank from the VDD . . . . .
QVCO schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Small signal equivalent lumped model of an Accumulation MOS varactor
QVCO varactor C-V characteristic . . . . . . . . . . . . . . . . . . . . . .
max
. . . . . . . . . . . . . . . . . . . . .
QVCO varactor C
Cmin characteristic
VCO Inductor quality factor and lumped model. . . . . . . . . . . . . . .
QVCO microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison between measured and simulated tuning range. . . . . . . . .
Comparison between measured and simulated phase noise. . . . . . . . . .
VCO CMOS 0.13 µm state of the art. . . . . . . . . . . . . . . . . . . . . .
Simulated PLL phase noise (black curve). . . . . . . . . . . . . . . . . . .
9
10
10
12
14
15
15
15
15
17
19
21
22
23
24
25
26
26
27
28
29
29
3.1
3.2
3.3
3.4
General block diagrams of a CPPLL . . . . . .
General block diagrams of a fractional CPPLL
Generalized PLL linear model . . . . . . . . . .
Analog LFs of . . . . . . . . . . . . . . . . . . .
32
33
34
34
iii
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List of Figures
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
iv
(a) 2nd -order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) 3rd -order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3rd -order system open loop gain Bode plot . . . . . . . . . . . . . . . .
SCL based divide-by-two frequency divider . . . . . . . . . . . . . . .
SCL D latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSPC based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(a) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Register transient response . . . . . . . . . . . . . . . . . . . . .
(c) Divide-by-two frequency divider . . . . . . . . . . . . . . . . . .
(d) Divide-by-two frequency divider transient response . . . . . . . .
Regenerative divide-by-two frequency divider block diagram . . . . . .
ILFD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Worldwide frequency allocation for 60 GHz band and operation. . . . .
Atmospheric absorption of millimeter wave. . . . . . . . . . . . . . . .
Example of Wireless Personal Area Network applications. . . . . . . .
Protocol Structure of ECMA standard. . . . . . . . . . . . . . . . . . .
Frequency plan of ECMA standard. . . . . . . . . . . . . . . . . . . .
DISTRONIC radar sensor mounted on Mercedes Benz S-class vehicles.
Schematic example of Adaptive Cruise Control (ACC) operation. . . .
Possible applications for automotive radars. . . . . . . . . . . . . . . .
An example of IVC. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
An example of RVC. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
An example of body scanner operation based on millimeter waves. . .
GPR apllications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross section of I-MOS varactor. . . . . . . . . . . . . . . . . . . . . .
versus transistor length . .
Varactor minimum quality factor and CCmax
mic
Varactor quality factor and capacitance versus VT U N E . . . . . . . . . .
VCO schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductance and quality factor versus frequency. . . . . . . . . . . . . .
2π differential lumped model. . . . . . . . . . . . . . . . . . . . . . . .
VCO layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(a) VCO layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Tank layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . .
(a) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO voltage tuning range. . . . . . . . . . . . . . . . . . . . . . . . .
VCO phase noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO output spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Injection-Locked Frequency Divider schematic. . . . . . . . . . . . . .
Tank quality factor for VT U N E 0 V. . . . . . . . . . . . . . . . . . . . .
Injection-Locked LC-tank Frequency Divider tank. . . . . . . . . . . .
Frequency generation for mm-Wave and satellite applications
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34
34
35
39
39
41
41
41
41
41
43
43
45
46
47
51
51
53
54
55
56
57
58
59
64
65
66
67
67
68
68
69
69
69
70
70
70
71
72
72
74
75
76
List of Figures
3.38
3.39
3.40
3.41
3.42
3.43
3.44
3.45
3.46
4.1
(a) Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Microphotograph . . . . . . . . . . . . . . . . . . . . . . . . . . .
Injection-Locked LC-tank Frequency Divider free running frequency. .
Injection-Locked LC-tank Frequency Divider Photomicrograph. . . . .
Injection-Locked LC-tank Frequency Divider sensibility. . . . . . . . .
LC Frequency Divider measurements. . . . . . . . . . . . . . . . . . .
(a) Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Output spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . .
IL Ring Oscillator Frequency Divider block diagram. . . . . . . . . . .
Differential amplifier schematics. . . . . . . . . . . . . . . . . . . . . .
(a) Differential pair with input injection . . . . . . . . . . . . . . . .
(b) Differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency and current consumption versus bias voltage. . . . . . . . .
Locking range versus bias voltage. . . . . . . . . . . . . . . . . . . . .
Injection-Locked Ring Oscillator Frequency Divider microphotograph.
(a) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(b) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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76
76
77
78
80
80
80
80
82
82
82
82
84
85
86
86
86
Microphotograph of th cascoded VCO, ILLCFD and ILROFD. . . . . . . 88
(a) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(b) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Frequency generation for mm-Wave and satellite applications
v
List of Tables
2.1
VCO CMOS 0.13 µm state of art. . . . . . . . . . . . . . . . . . . . . . . . 28
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
International Telecommunications Union (ITU) Radio Band. . . . . .
Modulation and Coding Schemes Classes in the SC PHY. . . . . . . .
RF Channels for mmW PHY. . . . . . . . . . . . . . . . . . . . . . . .
AV HRP data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV LRP data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter spurious emissions. . . . . . . . . . . . . . . . . . . . . . .
Receiver spurious emissions. . . . . . . . . . . . . . . . . . . . . . . . .
State of the art of CMOS mmW PLLs close to 60 GHz. . . . . . . . . .
Frequency divider topology of CMOS PLL close to 60 GHz. . . . . . .
Frequency planning. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State of the art of CMOS mmW Voltage Controlled Oscillators. . . . .
LC Frequency Divider free running frequency. . . . . . . . . . . . . . .
LC Frequency Divider Locking Range . . . . . . . . . . . . . . . . . .
State of the art of CMOS mmW Injection Locking Frequency Dividers.
Ring Oscillator Frequency Divider Locking Range . . . . . . . . . . . .
vii
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44
48
49
49
49
52
52
60
61
63
73
78
79
81
85
List of Symbols
∆f
Frequency range
(Hz)
ǫ0
Permittivity of free space
(F m−1 )
ǫox
Permittivity of silicon oxide
(F m−1 )
γ
White noise coefficient
λ0
Permeability of free space
L
Phase Noise
ω0
Central angular velocity
BW
PLL bandwidth
c
Light speed
CV
Variable capacitance
(F)
Cf ix
Fix capacitance
(F)
Cox
Oxide capacitance
(F)
CSi
Capacitance of the depletion layer under the gate
(F)
CSub
Substrate capacitance
(F)
f
Frequency
(Hz)
f0
Oscillator central frequency
(Hz)
fmax
Maximum operation frequency
(Hz)
fmin
Minimum operation frequency
(Hz)
fOU T
PLL Output frequency
(Hz)
(N/A2 )
(dBc/Hz)
(rad s−1 )
(Hz)
(m s−1 )
ix
List of Symbols
fREF
PLL Reference frequency
gm
Transconductance of MOS transistor
(S)
IDC
Large-signal drain current of MOS transistor
(A)
IIN J
Large-signal injected drain current of MOS transistor
(A)
k
Boltzmann’s constant
L
Length of MOS transistor
M
Integer-N PLL division ratio
N/N + 1
Dual-modulus prescaler division ratio
PDIS
Power Dissipation
QC
Capacitances quality factor
QL
Inductor quality factor
QT
Total tank quality factor
Rp
Parallel loss resistance
(Ω)
rch
Equivalent resistance of the channel underneath the oxide
(Ω)
rg
Access resistance of the polysilicon gate
(Ω)
Rpc
Parallel capacitance resistance
(Ω)
Rpeq
Equivalent parallel resistance of the circuits
(Ω)
Rpl
Parallel inductor resistance
(Ω)
rs/d
Source/drain contact resistance
(Ω)
Rsc
Series capacitance resistance
(Ω)
Rsl
Series inductor resistance
(Ω)
T
Absolute temperature
(K)
TS
PLL settling time
V0
Output voltage at f0 frequency
(V)
VDD
Supply voltage
(V)
VGS
Peak gate-to-source voltage
(V)
Vout
Output voltage
(V)
x
Frequency generation for mm-Wave and satellite applications
(Hz)
(J K−1 )
(m)
(W)
(s)
List of Symbols
VT H
Threshold voltage of MOS transistor
(V)
VT U N E
Tuning voltage
(V)
W
Width of MOS transistor
(m)
WF
Width of a single finger in MOS transistor
(m)
Z0
Characteristic impedance
(Ω)
Zout
Output impedance
(Ω)
Frequency generation for mm-Wave and satellite applications
xi
Abstract
[EN] The research activities presented in this thesis are related to the design of analog
CMOS Radio Frequency Integrated Circuits. In particular the effort was focused on frequency synthesizers (Phase-Locked Loop) for transceiver. This work especially deals with
critical blocks such as Voltage Controlled Oscillator (VCO) and Frequency Dividers.
The first part of the thesis reports the design guidelines of a negative resistance LC-tank
VCO and the design of a 15 GHz Quadrature Voltage Controlled Oscillator. This represents the contributions to the realizations of a Phase-Locked Loop (PLL) realization
in CMOS 130 nm technology for satellite applications in collaborations with the Polytech’Nice Sophia laboratory in France.
The second part of this work reports the design contribution of a 60 GHz Phase-Locked
Loop in 65 nm CMOS technology for Wireless Personal Area Network (WPAN) applications in collaboration with the LAAS laboratory (Toulouse, France). In particular
the design efforts were devote to the blocks working at millimeter Wave (mmW) frequency such as VCO and Frequency Divider (FD). Concerning the Frequency Dividers
the Injection-Locked topology was selected for the sake of its high frequency and low
power characteristics. In particular the prescaler is an Injection-Locked LC-tank Frequency Divider (ILLCFD) followed by an Injection-Locked Ring Oscillator Frequency
Divider (ILROFD). For the VCO the negative resistance design approach has been employed. All cited circuits have been implemented and succesfully tested.
[IT] Il lavoro di ricerca presentato in questa tesi è incentrato sulla progettazione di circuiti integrati a radio frequenza in tecnologia CMOS. In particolare l’impegno e’ stato
focalizzato sui circuiti per la sintesi di frequenza (circuiti ad aggancio di fase) per ricetrasmettitori. L’attenzione è incentrata sulla progettazione dei blocchi più critici come
oscillatori controllati in tensione (VCO) e divisori di frequenza.
La prima parte della tesi presenta le linee guida per la progettazione di LC VCO a resistenza negativa e la progettazione di un oscillatore in quadratura controllato in tensione
(QVCO) a 15 GHz. Quest’ultimo rappresenta il contributo alla realizzazione di un sintetizzatore di frequenza a 15 GHz in tecnologia CMOS 130 nm per applicazioni satellitari
1
Abstract
in collaborazione con il Politecnico di Nizza (Sophia Antipolis, Francia).
La seconda parte della tesi riporta il contributo alla realizzazione di un sintetizzatore di
frequenza a 60 GHz in tecnologia CMOS 65 nm in collaborazione con i laboratori LAAS
(Tolosa, Francia) per reti senza fili ad alta velocità e corta distanza WPAN. In particolare la progettazione dei blocchi a onde millimetriche come l’oscillatore e i primi
due blocchi della catena di divisione. Per quanto riguarda i divisori di frequenza sono
state utilizzate due topologie Injection-Locked per la efficacia ad alte frequenze e il loro
basso consumo. Il prescaler é stato realizzato con una topologia oscillatore a risonatore
LC sincronizzato e il secondo blocco con oscillatore ad anello sincronizzato. Il VCO è
stato realizzato a resistenza negativa. Tutti i circuiti sopracitati sono stato testasti con
successo.
[FR] Cette thèse se concentre sur la conception de circuits intégrés radio fréquence en
technologie CMOS. En particulier, l’effort est axé sur les circuits pour la synthèse de
fréquence (boucles à verrouillage de phase) pour les émetteurs/récepteurs. L’attention se
concentre sur la conception des blocs critiques comme les oscillateurs controlé en tension
(VCO) et les diviseurs de fréquence.
La première partie de la thèse présente des directives pour la conception de VCO à résonateur LC à résistance négative et la conception d’un oscillateur en quadrature controlé
en tension (QVCO) à 15 GHz. Ce dernier représente la contribution à la réalisation d’un
synthétiseur de fréquence à 15 GHz en technologie CMOS 130 nm pour des applications
satellites réalisé en collaboration avec Polytech’Nice (Sophia Antipolis, France).
La deuxième partie de la thèse montre la contribution à la réalisation d’un synthétiseur de
fréquence 60 GHz en technologie CMOS 65 nm, en collaboration avec le laboratoire LAAS
(Toulouse, France) pour les réseaux haut débit sans fil et à courte distance WPAN. Une
attention particuliére a été portée sur la conception des blocs fonctionnant des lesbandes
millimétriques tel que l’oscillateur et les deux premiers blocs de la chaine de division.
En ce qui concerne les diviseurs de fréquence, deux topologies à injection ont été utilisées pour leur efficacité et leur basse consommation. Le prédiviseur a été concu avec
une topologie oscillateur à résonateur LC synchronisé suivi d’un oscillateur en anneau
synchronisé. Le VCO a une topologie à résistance négative. Tous les circuits ci-dessus
ont été réalisés et testée avec succès.
2
Frequency generation for mm-Wave and satellite applications
1
Introduction
The cut-off frequency increase achieved by the scaling of CMOS processes (e.g. fT
beyond 200 GHz for a 32 nm bulk process), combined with the relative low cost of these
processes with respect to other ones, has led the CMOS to dominate the Integrated
Circuits (ICs) market: as a result, monolithic CMOS transceivers have been realized
targeting several different standards [1].
A building block diagram representing an example of a monolithic frequency division duplexing transceiver is depicted in Figure 1.1. The duplexer filter separates the
transmitted frequency (fT X in blue) and the received frequency (fRX in red), allowing
to use only one antenna for both the transmission and the reception. Even though
frequency division duplexing transceivers suffer from multiple drawbacks (e.g. transmitter signal leakage into the receiver path, duplexer attenuation-quality factor trade-off,
spectral leakage to adjacent channels in transmitter output) they are employed in many
Radio Frequency (RF) systems (e.g. in cellular communications) because they isolate
the receivers from the signal produced by transmitters [1].
The received signal, capted by the antenna, is passed to the receiver path through the
duplexer filter: since its low amplitude, it first of all undergoes a low noise amplification,
performed by the Low Noise Amplifier (LNA), then it is band-pass filtered and finally it
undergoes a frequency down-conversion to baseband, performed by a mixer.
On the other side, the transmitted signal is first of all up-converted to the carrier
frequency by a mixer, then is band-pass filtered and eventually it undergoes a power
amplification, performed by the Power Amplifier (PA), to rise its power level before
transmission. Finally, the duplexer filter pass the power amplified signal to the antenna
for the transmission.
The tones used for the frequency up- and down-conversions, performed by the mixers,
are produced by the frequency synthesizer. This is a system which receives a stable and
low-noise input signal, called reference signal, and generates an output signal which is
precisely locked in phase and frequency to a reference one. The main design challenge is
to realize a low-voltage, low-power, low-cost monolithic synthesizer able to meet the constraints specified by the standard in terms of phase-noise, spurious tones, settling time,
tuning range and resolution. A common implementation of a frequency synthesizer is
3
Introdution
Receiver
fT X fRX
LNA
RX
BPF
fRX
Duplexer
Filter
Frequency
Synthesizer
FCW
fT X
BPF
PA
TX
Transmitter
Figure 1.1: Frequency division duplexing transceiver block diagram.
based on a Phase-Locked Loop (PLL) (Figure 1.2), which can be both implemented in
analog or digital form [2]. The relation between the reference and output signal frequencies is determined by the Frequency Control World (FCW) as depicted in Figure 1.2.
LF
VCO
fREF
PFD
CP
fOU T
Frequency Divider
÷M
FCW
Figure 1.2: General block diagrams of a CPPLL.
The present Ph.D. thesis addresses the design of the Phase-Locked Loop building
blocks working at high frequency, and epecially the Voltage Controlled Oscillator (VCO)
and the Frequency Divider (FD). The interface matching between these two blocks is
a critical point of every PLL. The central VCO frequency carrier must be around the
minimum input power sensitivity of the first division chain block in order to transmit all
VCO available power to the FD. The FD locking range must be larger than the VCO
frequency tuning range in order to compensate eventually frequency shifts. This Ph.D.
thesis addresses these topics in different bands and in different CMOS technologies.
4
Frequency generation for mm-Wave and satellite applications
Introdution
Chapter 2 concerns the design contribution to the realization of a 15 GHz PLL in
130 nm CMOS bulk process for Digital Video Broadcasting - Satellite (DVB-S) applications. The project has been developed in collaboration with the Polytech of NICESOPHIA ANTIPOLIS. My work was focused on the design of a 15 GHz Quadrature
Voltage Controlled Oscillator (QVCO).
Chapter 3 mainly reports the contribution to the NANOCOMM ANR project whose
aim is the realization of a low-cost, highly-integrated CMOS transmitter prototypes
sending data up to 1 Gbps in a range up to 1 m to target 60 GHz Wireless Personal
Area Network (WPAN) applications. The used technology was the CMOS bulk 65 nm
by STMicroelectronics. The project was carried out in collaboration with LAAS-CNRS
Laboratory of Toulouse. My work was focused on the design of the PLL blocks which
work at millimeter wave frequency: in particular the design of the Voltage Controlled
Oscillator (VCO) and the first two blocks of the division chain: divide-by-2 InjectionLocked LC-tank Frequency Divider (ILLCFD) and a divide-by-2 Injection-Locked Ring
Oscillator Frequency Divider (ILROFD).
The first part of each chapter is devoted to some theory and applications related to
the addressed topic.
Frequency generation for mm-Wave and satellite applications
5
Ku band Oscillator
2
This chapter reports on the Ku band standard for Digital Video Broadcasting.
The fundamental guideline for CMOS Oscillators and the Voltage Controlled
Oscillators design are presented. A 15 GHz QVCO has been designed in a
130 nm CMOS technology. The phase noise and voltage tuning range performances of the QVCO are compared with the literature.
2.1
DVB-S2 standard
The DVB-S2 standard is the second-generation specification for satellite broadcasting developed by the Digital Video Broadcasting (DVB) Project in 2003. It benefits from
more recent developments in channel coding, Low Density Parity check Codes (LDPC),
combined with a variety of modulation formats (QPSK, 8PSK, 16APSK and 32APSK).
When used for interactive applications, such as Internet navigation, it may implement
Adaptive Coding & Modulation (ACM), thus optimizing the transmission parameters
for each individual user, dependant on path conditions. Backwards-compatible modes
are available, allowing existing DVB-S set-top-boxes to continue working during any
transitional period.
The DVB-S2 system has been designed for several satellite broadband applications:
• broadcast services for standard definition TV and HDTV;
• interactive services, including Internet access, for consumer applications;
• professional applications, such as Digital TV contribution and News Gathering,
TV distribution to terrestrial VHF/UHF transmitters;
• data content distribution and Internet trunking.
It is based on a ”tool-kit” approach which allows us to cover all the application areas
while still keeping the single-chip decoder at reasonable complexity levels, thus enabling
the use of mass market products also for professional applications.
The DVB-S2 standard has been specified around three key concepts:
7
Ku band Oscillator
1. best transmission performance,
2. total flexibility,
3. reasonable receiver complexity.
To achieve the best performance complexity trade-off, quantifiable in about 30 % capacity gain over DVB-S, DVB-S2 benefits from more recent developments in channel coding
and modulation. For interactive point-to-point applications such as IP unicasting, the
adoption of the Adaptive Coding & Modulation (ACM) functionality allows to optimize
the transmission parameters for each individual user on a frame-by-frame basis, dependant on path conditions, under closed-loop control via a return channel (terrestrial or
by satellite): the result is an even greater gain of DVB-S2 over DVB-S.
DVB-S2 is so flexible that it can cope with any existing satellite transponder characteristics, with a large variety of spectrum efficiencies and associated Carrier-to-Noise
ratio (C/N) requirements. Furthermore, it is not limited to MPEG-2 video and audio
coding, but it is designed to handle a variety of advanced audiovideo formats which the
DVB Project is currently defining. DVB-S2 accommodates any input stream format,
including single or multiple MPEG Transport Streams, continuous bit-streams, IP as
well as ATM packets.
2.1.1
Forward Error Correction (FEC) and modulation
Figure 2.1 shows the DVB-S2 detailed system block diagram [3]. The FEC is the key
subsystem to achieve excellent performances by satellite, in the presence of high levels of
noise and interference. The selection process, based on computer simulations, compares
seven proposals - parallel or serially concatenated convolutional codes, product codes,
low density parity check codes (LDPC) - all using ”turbo” (i.e. recursive) decoding techniques. The winning system, based on Low Density Parity check Codes (LDPC), offeres
the minimum distance from the Shannon limit on the linear AWGN channel, under the
constraint of maximum decoder complexity of 14 mm2 of silicon (0.13 µm technology).
The selected LDPC codes use very large block lengths (64800 bits for applications not
too critical for delays, and 16200 bits). Code rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4,
4/5, 5/6, 8/9 and 9/10 are available, depending on the selected modulation and the
system requirements. Coding rates 1/4, 1/3 and 2/5 have been introduced to operate,
in combination with QPSK, under exceptionally poor link conditions, where the signal
level is below the noise level. Concatenated Bose-Chaudhuri-Hocquenghem (BCH) outer
codes are introduced to avoid error floors at low Bit Error Rate (BER).
Four modulation modes can be selected for the transmitted payload (see Figure 2.2).
QPSK and 8PSK are typically proposed for broadcast applications, since they are virtually constant envelope modulations and can be used in non-linear satellite transponders
driven near saturation. The 16APSK and 32APSK modes, mainly targeted at professional applications, can also be used for broadcasting, but these require a higher level
of available C/N and the adoption of advanced pre-distortion methods in the up-link
station to minimize the effect of transponder non-linearity. Whilst these modes are not
8
Frequency generation for mm-Wave and satellite applications
2.1 DVB-S2 standard
Figure 2.1: Functional block diagram of the DVB-S2 System characteristic.
as power-efficient as the other modes, the spectrum efficiency is much greater. The
16APSK and 32APSK constellations have been optimized to operate over a non-linear
transponder by placing the points on circles. Nevertheless their performances on a linear
channel are comparable with those of 16QAM and 32QAM respectively. By selecting
the modulation constellation and code rates, spectrum efficiencies from 0.5 to 4.5 bits per
symbol are available and can be chosen depending on the capabilities and restrictions of
the satellite transponder used. DVB-S2 has three ”roll-off factor” choices to determine
spectrum shape: 0.35 as in DVB-S, 0.25 and 0.20 for tighter bandwidth restrictions.
Framing structure
Two levels of framing structures have been designed:
• the first at the physical level (PL), carrying few highly-protected signaling bits;
• the second at base-band level, carrying a variety of signaling bits, to allow maximum flexibility on the input signal adaptation.
The first level of framing structure has been designed to provide robust synchronization
and signaling at the physical layer. Thus a receiver may synchronize (carrier and phase recovery, frame synchronization) and detect the modulation and coding parameters before
demodulation and FEC decoding. With reference to Figure 2.3, the DVB-S2 physical
layer signal is composed of a regular sequence of ”lorries” (frames): within a lorry, the
modulation and coding scheme is homogeneous, but may change (Adaptive Coding &
Modulation) in adjacent lorries. Every frame is composed of a payload of 64800 bits (or
Frequency generation for mm-Wave and satellite applications
9
Ku band Oscillator
Figure 2.2: The four possible DVB-S2 constellations before physical layer scrambling.
16200 bits), corresponding to a code block of the concatenated LDPC/BCH FEC, and a
Header (90 binary modulation symbols), containing synchronization and signaling informations. Since the PL Header is the first entity to be decoded by the receiver, it could
not be protected by the powerful LDPC/BCH FEC scheme. On the other hand, it has
Figure 2.3: Pictorial representation of the physical-layer framing structure.
to be perfectly decodable under the worst-case link conditions. Therefore, the system
designers selected a very low-rate 7/64 block code to protect it, suitable for soft-decision
correlation decoding, and minimized the number of signaling bits to reduce decoding
10
Frequency generation for mm-Wave and satellite applications
2.1 DVB-S2 standard
complexity and global efficiency loss.
The second level of framing structure, the ”baseband frame”, allows a more complete signaling functionality to configure the receiver according to the application scenarii: single or multiple input streams, generic or transport stream, Constant Coding &
Modulation (CCM) or Adaptive Coding & Modulation (ACM), and many other configuration details. Thanks to the LDPC/BCH protection and the wide length of the FEC
frame, the Base-Band (BB) Header may contain many signaling bits (80) without losing
transmission efficiency or ruggedness against noise.
Backwards-compatible modes
The large number of DVB-S receivers already installed makes it very difficult for many
established broadcasters to think of an abrupt change of technology in favour of DVB-S2 especially where there is a receiver subsidy and for free-to-air public services. In such scenarii, backwards-compatibility may be required in the migration period, allowing legacy
DVB-S receivers to continue operating, while providing additional capacity and services
to new, advanced receivers. At the end of the migration process, when the complete
receiver population has migrated to DVB-S2, the transmitted signal could be modified
to the non-backward compatible mode, thus exploiting the full potential of DVB-S2.
Optional Backwards-Compatible (BC) modes have therefore been defined in DVB-S2,
intended to send two Transport Streams on a single satellite channel. The first (High Priority, HP) stream is compatible with DVB-S receivers as well as with DVB-S2 receivers,
while the second (Low Priority, LP) stream is compatible with DVB-S2 receivers only.
Backwards compatibility can be implemented by hierarchical modulation, where the two
HP and LP Transport Streams are synchronously combined at modulation symbol level
on a non-uniform 8PSK constellation. The LP DVB-S2-compliant signal is BCH and
LDPC encoded, with LDPC code rates 1/4, 1/3, 1/2 or 3/5. Then the hierarchical
mapper generates the non-uniform 8PSK constellation: the two HP DVB-S bits define a
QPSK constellation point, while the single bit from the DVB-S2 LDPC encoder sets an
additional rotation before transmission. Since the resulting signal has a quasi-constant
envelope, it can be transmitted on a single transponder driven near saturation.
System performance
Depending on the selected code rate and modulation constellation, the system can operate at carrier-to-noise ratios from −2.4 dB (using QPSK 1/4) to 16 dB (using 32APSK
9/10), assuming an AWGN channel and ideal demodulator (see Figure 2.4). These results have been obtained by computer simulations for a Packet Error Rate of 10-7 (one
erroneous Transport Stream Packet per transmission hour in a 5 Mbit/s video service).
The distance from the Shannon limit ranges from 0.7 dB to 1.2 dB. On AWGN, the result
is typically a 20 - 35 percent capacity increase over DVB-S and DVB-DSNG under the
same transmission conditions and 2 - 2.5 dB more robust reception for the same spectrum efficiency. The DVB-S2 system may be used in ”single-carrier-per-transponder”
Frequency generation for mm-Wave and satellite applications
11
Ku band Oscillator
Figure 2.4: Required C/N versus spectrum efficiency on the AWGN channel.
or in ”multi-carriers-per-transponder” (FDM) configurations. Figure 2.4 also indicates
examples of the useful bitrate capacity RU achievable by the system in the different
modulation/coding configurations, assuming unit symbol rate RS . The symbol rate RS
corresponds to the −3 dB bandwidth of the modulated signal, while RS (1 + α) corresponds to the theoretical total signal bandwidth after the modulator, with representing
the roll-off factor of the modulation. The use of the narrower roll-off α = 0.25 and
α = 0.20 may allow a transmission capacity increase, but may also produce larger nonlinear degradations by satellite for single-carrier operation.
When DVB-S2 is transmitted by satellite, quasi-constant envelope modulations such
as QPSK and 8PSK are power efficient in the single-carrier-per-transponder configuration, since they can operate on transponders driven near saturation. 16APSK and
32APSK, which are inherently more sensitive to non-linear distortions and would require
quasi-linear transponders (i.e., with larger Output Back- Off, OBO) may be improved
in terms of power efficiency by using non-linear compensation techniques in the up-link
station. In FDM configurations, where multiple carriers occupy the same transponder,
this latter must be kept in the quasi-linear operating region (i.e., with large OBO) to
avoid excessive inter-modulation interference between signals. In this case, the AWGN
performance figures may be adopted for link budget computations.
Examples of possible uses of the system
Some examples may better clarify the functionalities and flexibility of DVB-S2. Starting
from TV broadcasting using constant coding and modulation, and variable coding and
modulation, some examples are given in the following to cover professional TV applications such as DSNG and DTT distribution to transmitters. For broadcasting services,
12
Frequency generation for mm-Wave and satellite applications
2.1 DVB-S2 standard
only down-link parameters have been evaluated, for satellite EIRPs of 51 and 53.7 dBW
at the service area contour. Conversely, for professional applications, link budget evaluations have been carried out for a typical Ku-band 36 MHz satellite with European-wide
up-link and down-link coverage. Ideal target carrier-to-noise ratios are derived from
Figure 2.4. The following link characteristics have been adopted:
• Up-link: ITU climatic zone L; frequency: 14.29 GHz; Atmospheric loss and rain
attenuation for 99.9 % of average year (a.y.): 0.2 + 5.6 dB.
• Satellite: G/T(dB K−1 ): 4.3; transmitted EIRP at saturation: 46.5 dBW.
• Down-link: ITU climatic zone K; frequency: 10.99 GHz; antenna efficiency: 60 %;
coupling loss: 0.5 dB, pointing loss: 0.5 dB; LNB noise figure: 1.1 dB; Atmospheric
loss and rain attenuation for 99.9 % a.y.: 0.1 + 2.4 dB.
2.1.2
Adaptive Coding and Modulation for one-to-one services
When DVB-S2 is used for interactive point-to-point applications like IP unicasting, its
gain over DVB-S is even greater, if Adaptive Coding & Modulation (ACM) schemes are
used. In fact ACM allows us to recover the so called ”clear sky margin” (4 dB to 8 dB of
power), typically wasted in conventional ”constant coding and modulation” satellite links,
thus doubling or even tripling the average satellite throughput and reducing dramatically
the service cost. The ACM gain versus CCM increases for critical propagation conditions:
therefore ACM is fundamental for the higher frequency bands (e.g. Ka band) and for
tropical climatic zones. Figure 2.5 shows the scheme of an ACM satellite link, composed
Figure 2.5: Block diagram of a DVB-S2 ACM link.
Frequency generation for mm-Wave and satellite applications
13
Ku band Oscillator
of an ACM Gateway (GW), the DVB-S2 ACM modulator, the up-link station, the
Satellite and the Satellite receiving Terminal (ST) connected to the ACM GW via a
return channel. The DVB-S2 ACM modulator operates at constant symbol rate, since
the available transponder bandwidth is assumed to be constant. ACM is implemented
by the DVB-S2 modulator by transmitting a TDM sequence of frames, where coding
and modulation format may change frame-by-frame. Therefore service continuity is
achieved, during rain fades, by reducing user bits while increasing at the same time the
FEC redundancy and/or modulation ruggedness.
Physical layer adaptation is achieved as follows:
• Each ST measures the channel status (available C/N+I) and reports it via the
return channel to the Gateway (GW);
• The ST reports are taken into account by the GW while selecting the assigned
protection level for data packets addressed to the ST;
• In order to avoid information overflow during fades, a user bitrate control mechanism should in principle be implemented, adapting the offered traffic to the available channel capacity. This can be implemented in various ways, according to the
specific service requirements and network architecture. The GW imposes error protection, applied to a given portion of user data via suitable interfacing mechanisms.
With respect to one-to-one services (e.g., DSNG), IP unicast links using DVB-S2
ACM must adapt the error protection on a user-per-user basis: the number of
users may be very large (e.g. up to hundreds of thousands). Furthermore, direct
source rate control may be impossible, since information sources (IP information
providers) are far from the satellite GW.
A crucial issue in ACM systems is the physical layer adaptation loop delay, as it is strictly
linked to the system capability of tracking channel variations. If loop adaptation is fast,
service continuity may be guaranteed even during fast rain fades while, at the same time,
keeping low C/N transmission margins to maximize the overall system throughput. Since
maximum C/N+I variation rates at Ka band have been estimated to be of about 0.5 dB
per second during heavy rain fades, and since the C/N distance between two adjacent
DVB-S2 protection levels is around 1 dB, control loop delays smaller than 1 second
should allow minimization of transmission packet losses.
14
Frequency generation for mm-Wave and satellite applications
2.2 CMOS oscillator
2.2
CMOS oscillator
Figure 2.6 shows a parallel ideal lossless LC tank. If the capacitor (or the inductor) is
initially charged, when the switch closes the voltage across the resonator is sinusoidal
with a constant amplitude (determined by the initial condition and by the L and C
values).
C
V0
L
Figure 2.6: Ideal inductor capacitor resonator.
The frequency of the sinusoidal waveform is simply related to the tank parameters
by the following equation:
1
(2.1)
f0 = √
2π LC
Under the hypothesis of lossless components, the inductor and capacitor continue to
exchange the stored energy each other in the form of magnetic and electric field and
the sinusoidal output voltage persists indefinitely. Obviously, the hypothesis of lossless
component is not found in practice. Figure 2.7 shows a real case of LC resonant tank,
including series losses for all components (Rsl , Rsc ) and a parallel loss (Rp ). The loss
associated with the reactive components identifies the quality factors:
ωL
Rsl
(2.2)
1
ωCRsc
(2.3)
QL =
QC =
C
Rpeq
L
Rp
Rsc
C
Rpc
L
Rpl
Rp
Rsl
(a) series losses.
(b) parallel losses.
Figure 2.7: Tank series and parallel losses.
For sufficiently large QL and QC the tank can be represented (near the resonant
frequency) by the circuit of Figure 2.7b with:
Rpl = QL ωL
Frequency generation for mm-Wave and satellite applications
(2.4)
15
Ku band Oscillator
QC
ωC
Rpc =
(2.5)
It is now useful to define the characteristic impedance Z0 and the quality factor of the
complete tank circuit QT as follows:
Z0 =
s
L
=
C
1
ω0 C
= ω0 L
(2.6)
Rpeq = Rp //Rpc //Rpl
QT =
1
QT
(2.7)
Rpeq
Rpeq
=
= ω0 CRpeq
Z0
ω0
(2.8)
1
QL
(2.9)
=
Z0
+
Rp
+
1
QC
The total tank quality QT is dominated by the lowest quality factor component. Due to
the presence of the tank losses (represented by Rpeq ) the oscillation vanishes, because part
of the energy exchanged in each cycle from the inductor to the capacitor and viceversa
is dissipated by Rpeq . To get a real oscillator, a negative conductance must be added
in parallel to the resonator to compensate the tank losses. Negative conductance (or
resistance) can be obtained with active circuits providing energy to the LC resonator,
at least equal to the energy dissipated by the tank losses in each cycle. The minimum
needed negative conductance gmc must be at least equal to the total loss conductance
1
):
( Rpeq
1
1
=
(2.10)
|gmc | ≥
Rpeq
QT Z0
To guarantee oscillations start-up under Process-Voltage-Temperature (PVT) variations
the negative conductance is designed with a factor 1.5 to 3 times larger than the required
minimum. There are several circuits able to provide negative conductance (or resistance),
leading to a wide variety of oscillator topologies [1][4]. Among them, the widely used
circuit topology of a CMOS LC tank oscillator is depicted in Figure 2.8. It is commonly
preferred for several reasons:
1. it requires a minimal number of active (and noisy) components, resulting low noise;
2. it requires a minimal number of passive components, and thus low silicon area;
3. it is very easy to insert variable capacitors to tune the output frequency;
4. it is a differential topology providing two anti-phase (180◦ shifted) output signals.
Differential circuit topologies are preferred, at radio frequency, due to the higher immunity to substrate and supply noise and, because differential circuits intrinsically remove
even order distortions.
16
Frequency generation for mm-Wave and satellite applications
2.2 CMOS oscillator
VDD
L Rpeq
C
Rpeq L
C
−gmc
Vout−
Vout+
M3
M2
M1
Vbias
Ibias
Figure 2.8: Circuit schematic of negative resistance LC CMOS Oscillator.
The differential resonator of the Figure 2.8 is composed by two LC tanks where the
parallel losses are represented by Rpeq . When the tail transistor is biased in saturation
region the circuit gives the differential negative conductance to compensate the tank
losses. The small signal differential conductance is given by: gmc = − g2m where gm is
the transconductance of the transistor M2,3 . To guarantee the oscillation start-up the
following equation must be satisfied:
|gmc |=
1
gm
≥
2
2Rpeq
(2.11)
where 2Rpeq is the total differential resistance seen across the two LC tanks. The
transconductance of each cross coupled transistor must be higher than the corresponding
LC tank loss [5].
2.2.1
Oscillation amplitude
In order to obtain a sinusoidal output voltage, the tank current must be a squarewave
ranging from - Ibias
and Ibias
filters higher
order harmonics of this current
2
2 ; the tank
is covered into a differential voltage
and only its Fourier component at f0 If0 = 2Ibias
π
by the equivalent impedance at resonance 2Rpeq = 2QT Z0 . The zero-peak differential
output voltage is then:
Voutdif f =
4
4
Ibias Z0 QT = Ibias ω0 LQT
π
π
(2.12)
We can observe the linear dependance between the oscillation amplitude and Ibias , QT ,
and Z0 . To save power and to achieve high spectral purity the total tank quality factor
value should be maximized.
Frequency generation for mm-Wave and satellite applications
17
Ku band Oscillator
Generally speaking the single ended output voltage (Vout+ and Vout− ) increases with
the increasing bias current; his value must be smaller than VDD . To increase the bias
current, the transistor M1 must be pushed in triode region, and the oscillator goes from
a current limited operation to a voltage limited operation [6].
The output voltage saturates to a value close to two times the voltage supply VDD . The
bias current at which the oscillator saturates is Ibiassat
Vsat = 2αVDD =
Therefore:
Ibiassat =
4
Ibiassat QT Z0
π
(2.13)
π αVDD
αVDD
=
2 QT Z0
ω0 LQT
(2.14)
with α < 1 [5].
2.2.2
Phase noise minimization
To arrive at the guidelines for the optimum design, we use the Leeson’s formula for the
white phase noise Lw (∆ω) at an offset frequency (∆ω) from an ω0 carrier
F
Lw (∆ω) = kT Rpeq 2
V0
ω0
QT ∆ω
(2.15)
where k is the Boltzmann’s constant, T is the absolute temperature, Rpeq is the equivalent
tank parallel resistance, V0 is the peak oscillation amplitude, QT is the tank quality factor.
F , the noise factor, is given by [7]
8
8γRpeq Ibias
+ γ gmbias Rpeq
(2.16)
πV0
9
where γ is the device white noise coefficient and gmbias is the current source transconductance. The typical Figure Of Merit (FOM) of an oscillator compares the phase noise
L, measured at a given offset frequency (∆ω) from the carrier frequency f0 normalized
to the oscillation frequency, the frequency offset and the power consumption:
F =2+
ω0
FOM = L(∆ω) − 20 log
∆ω
PDIS
+ 10 log
1 mW
(2.17)
where ∆ω = 2π∆f and PDIS is the dissipated power. The FOM allows therefore for an
homogeneous comparison between oscillators designed for different operation frequencies
and dissipated powers. As previously seen, at low bias current, while the amplitude of
oscillation is smaller than the power supply, the differential pair acts as a simple current
switch driving the resonators and Vout is expressed by Eq: 2.12. For higher currents the
output voltage saturates close to two times the supply voltage. Neglecting the noise of
the biasing transistor we can obtain:
L(∆ω) =
18



(2 + 2γ)







 2+
π 2 kT
2
16ω0 LQT Ibias
4γω0 LQT Ibias
παVDD
2
ω02
QT ∆ω
kT ω0 LQT
4(αVDD )2
2
ω02
QT ∆ω
current limited
(2.18)
voltage limited
Frequency generation for mm-Wave and satellite applications
2.2 CMOS oscillator
Eq: 2.18 shows that the phase noise decreases with Ibias in the current limited region and
increases in the voltage limited region. Therefore, minimum phase noise is achieved at
the transition of the two regions [8], when Vout = Vsat = 2αVDD (Eq: 2.13); the optimum
bias current is given by Eq: 2.14. Substituting Eq: 2.14 in Eq: 2.18 provides:
kT ω0 LQT
Lmin (∆ω) = (2 + 2γ)
4 (αVDD )2
ω02
QT ∆ω
!2
(2.19)
For a given technology, VDD and γ are fixed. The tank quality factor QT can be maximize by an optimum choise of inductor and varactor. To reduce the minimum achievable
phase noise of an oscillator, the inductor should be reduced, and the current consumption equally increased (in according with Eq: 2.14) to fall in to the optimum region of
operation [5].
2.2.3
CMOS Voltage Controlled Oscillator
Figure 2.9 shows the schematic of a CMOS Voltage Controlled Oscillator. The variable capacitors (CV ), realized with a MOS transistors, are connected in parallel with
the inductor. The gate terminals of the varactor are connected to the tank and the
drain/source terminals are connected together in a common node. This node acts as a
virtual ground for a differential signal. The tuning voltage is applied at the drain/source
terminal.
VDD
Vout−
Vout+
L
VT U N E
C
Cf ix
CV
C
M3
Cf ix
M2
M1
Vbias
Ibias
Figure 2.9: Schematic diagram of a CMOS Voltage Controlled Oscillator
Fixed capacitors (Cf ix ) represent the parasitic capacitance of interconnects, inductors, and transistors. The tuning range of a VCO is define as:
TR =
fmax − fmin
∆f
=2
f0
fmax + fmin
Frequency generation for mm-Wave and satellite applications
(2.20)
19
Ku band Oscillator
Combining Eq: 2.1 and Eq: 2.20 leads to the relationship between the tank capacitance
change and the oscillator tuning range:
∆f
1 ∆C
≈
f0
2 C
(2.21)
where ∆C = Cvarmax − Cvarmin is capacitance variation and C is the average tank
capacitance composed by the varactor capacitance (CV ) itself and the parasitic fixed
capacitance (Cf ix ). The second term of Eq: 2.21 can be rewritten as follows:
1
1 ∆C
1 ∆C
=
2 C
2 CV 1 + Cf ix
(2.22)
CV
To increase the tuning range, the effect of the parasitic fixed capacitance Cf ix must be
negligible. This goal can be achieved by reducing as much as possible the parasitic capacitance and/or by using larger value of varactor capacitance. Therefore the inductance
value must be reduced in according with Eq: 2.1 to keep constant the central oscillation
frequency. As a consequence, the tank characteristic impedance Z0 decreases and the
bias current needed to keep constant the output voltage swing increases according to
Eq: 2.12.
Usually in a CMOS circuit, the varactors are building using MOSFET transistors. Since
the varactor gates are directly connected to a DC voltage equal to voltage supply (VDD ),
the tuning voltage can range from 0 V to VDD . In addition, it is worth noticing that
the VCO of Figure 2.9 features a high sensitivity of the output frequency to changes in
the supply voltage, leading to a poor power supply noise rejection. In fact, since the
varactor gates are DC connected to the supply, supply voltage noise change provides the
same effect on the output frequency as a tuning voltage change.
To minimize this issue, several alternative topologies of CMOS Voltage Controlled Oscillator isolating the voltage across the LC tank from the supply voltage have been
presented. Some examples are depicted in Figure 2.10.
For any VCO, the dependance of the output signal on the tuning voltage is described
by the following expression:
Vout = V0 cos 2π f0 + KVCO
Z
t
VT U N E dt
−∞
(2.23)
where KVCO is the VCO gain. In case of linear relationship between the tuning voltage
and the output frequency, KVCO is expressed by:
fmax − fmin
KVCO =
VT U N Emax − VT U N Emin
20
Frequency generation for mm-Wave and satellite applications
(2.24)
2.3 Quadrature Voltage Controlled Oscillator
VDD
VDD
MP 2
Ibias
Vbias
MP 1
L
L
VT U N E
VT U N E
C
C
C
MN 2
MN 1
C
M2
M1
(b)
(a)
Figure 2.10: VCO which isolates the voltage across the LC tank from the VDD .
A larger VCO gain is rarely preferred. This is because a noise voltage present at the
tuning port of the oscillator results in a frequency modulation of the carrier and thus
in phase noise. It is intuitive that a larger tuning gain gives a larger sensitivity to noise
sources. If we assume a resistor R at the tuning port, for example the output resistance
of the tuning source, it is possible to show that a voltage noise results in a phase noise
magnitude given by [9]:
2πKVCO 2
(2.25)
L(∆ω) = 2kT R
∆ω
In addition to the case of a simple oscillator, the International Technology Roadmap for
Semiconductor (ITRS) FOM of a VCO takes into account also the tuning range [9, 5]:
ω0 TR
FOMT = L(∆ω) − 20 log
∆ω 10
2.3
PDIS
+ 10 log
1 mW
(2.26)
Quadrature Voltage Controlled Oscillator
This section provides insight on the main limitations of conventional techniques for
quadrature signals generation [5]:
1. RC-CR networks lead to high power consumption when high phase accuracy or
large tuning bandwidth are required.
2. Digital frequency dividers do not ensure high phase accuracy and are not suited
to drive large capacitive loads. In both cases typical power consumptions are well
above the tens of mW.
Frequency generation for mm-Wave and satellite applications
21
Ku band Oscillator
3. Ring Oscillator (RO) fulfills this requirement, but the notorious low spectral purity
(or better, the low phase noise FOM) of ring oscillators disqualifies this choice for
most applications in modern radio transceivers.
A more attractive approach to direct quadrature synthesis relies on the possibility of coupling two symmetric LC-tank VCOs to each other, thereby exploiting the good phase
noise performance of LC-oscillators.
In the present section a LC Quadrature Voltage Controlled Oscillator (QVCO) in
130 nm CMOS technology is investigated having in mind the idea of replacing the traditional superheterodyne architecture of the DVB-S receiver with a direct conversion
architecture where the Low Noise Block (LNB) receives the composite signal from the
satellite and provides at the output in one single step the I and Q bit stream at the base
band. The QVCO is usually the preferred solution to generate in-quadrature signals
with respect to poly-phase filters, ring oscillators, or frequency dividers.
In particular, the central frequency was fixed at 15 GHz, to evaluate the technology
capabilities not only for the ground receiver (e.g. in the Digital Video Broadcasting Satellite (DVB-S) the down-link frequency band is 10.7- 12.75GHz) but also for the on
satellite receiver (e.g. in the DVB-S the up-link frequency band is 12.9-18.4GHz).
2.3.1
Circuit design
Figure 2.11 depicts the schematic of the fully differential designed QVCO. The circuit
was biased without current mirror for sake of phase noise minimization. In addition
the lack of a current mirror allows to reduce the power consumption and to avoid the
introduction of an automatic amplitude control circuit. To fix the output voltage swing
VDD
MP 2
MN 4
MP 1
VT U N E
270
0
L
VDD
MP 4
90
C
C
MN 2
MN 1
180
270
MN 8
MP 3
VT U N E
180
MN 3
L
0
C
C
MN 6
MN 5
90
MN 7
Figure 2.11: QVCO schematic.
between current limited and voltage limited region the circuit requires a loop gain higher
22
Frequency generation for mm-Wave and satellite applications
2.3 Quadrature Voltage Controlled Oscillator
than 3:
|gmc | =
gmp + gmn
1
=
≥3
2
Rpeq
W
L
W
L
(2.27)
56 µm
130 nm
(2.28)
p
10 µm
130 nm
(2.29)
n
=
=
p
n
Eq: 2.28 and 2.29 fix the transistors size, and as a consequence the bias current to 4.5 mA
for each VCO. The cross-coupled transistors have been designed with a minimum length
to get a maximum transconductance. The inductor resonates directly with the parasitic
capacitances of the transistors. The transistors have been laid out multifinger and with a
double gate access, in order to reduce as much as possible the parasitic access resistance.
The accumulation varactors are connected with the drain of the transistors and DC
voltage close to 600 mV. Therefore the DC voltage of varactors is not directly sensible
to the voltage supply variations. Figure 2.12 shows the equivalent small signal model
which can be used to evaluate the quality factor of an accumulation MOS varactor and
to arrive at the optimum varactor design. Csub and rsub are the parasitic capacitance
G
rg
Cox
rch
CSi
Csub
rs/d
D/S
Rsub
Figure 2.12: Small signal equivalent lumped model of an Accumulation MOS varactor
and resistance of the reverse biased P-N junction of the N-well and P-type substrate.
If source and drain are tied to ground, the substrate parasitics are shorted and can
be neglected. rg , rch and rs/d are respectively the access resistances of the polysilicon
gate, the equivalent resistance of the channel underneath the oxide and the source/drain
contact resistance. Eq: 2.3 approximates the quality factor of the varactor as:
QC =
1
ωCV (rg + rch + rs/d )
(2.30)
1
+
(2.31)
where CV = C0 W L
C0 =
1
Cox
1
CSi
in which Cox and CSi are, respectively, the oxide capacitance and the capacitance of the
depletion layer under the gate, per unit area. By applying a positive voltage between
the gate and the N-well the surface is accumulated and the device capacitance equals the
oxide capacitance. If the applied voltage is reversed, the surface layer is depleted and
Frequency generation for mm-Wave and satellite applications
23
Ku band Oscillator
the series capacitance decreases. The maximum capacitance, per unit area, of the device
ǫ
corresponds to a heavily accumulated surface and equals Cox = tox
. On the other side,
a minimum value (Cdmin ) is reached when the voltage difference between the electrodes
equals the threshold voltage. Beyond this point, an inversion layer is formed under the
gate. N-type source/drain diffusions can not provide the holes required to invert the
surface layer transistor which are then thermally generated. At low frequency this effect
brings the value of the capacitance close to the oxide one. At high frequency, where the
varactor is assumed to operate, this effect is not seen and the capacitance remains at its
minimum value.
The quality factor is thus almost roughly independent of the varactor width. To
optimize the quality factor, the series resistances must be minimized with multifinger
layouts. On the other hand, increasing the number of fingers rises the fixed parasitic
capacitance of interconnects, reducing the tuning capability of the varactor. The gate
and channel resistances behave in a different way changing the gate length Lg . The
quality factor can be expressed with Eq: 2.3 and Eq: 2.30. The varactor capacitance
increases linearly with the MOS width, while all the parasitic resistances reduce linearly.
Figure 2.13 shows the simulated capacitance at 15 GHz frequency versus the gate-source
300
38
36
275
34
250
32
30
Quality Factor
28
200
26
24
175
Quality Factor
Capacitance [fF]
Capacitance
225
22
150
20
18
125
16
100
-2,0
-1,6
-1,2
-0,8
-0,4
0,0
V
TUNE
0,4
0,8
1,2
1,6
2,0
[V]
Figure 2.13: QVCO varactor C-V characteristic
voltage for the chosen 300 fF MOS varactor designed with a minimum possible length
of 0.35 µm and multifinger (20) [10]. Changing the gate voltage from −2 V to 2 V, with
the source and drain contacts connected to ground, the capacitance ranges from 109.4 fF
max
to 294.7 fF. Figure 2.14 shows the quality factor and the C
Cmin characteristics versus
24
Frequency generation for mm-Wave and satellite applications
2.3 Quadrature Voltage Controlled Oscillator
19
18
2,300
17
2,275
16
2,250
2,225
14
MAX
2,200
/C
MIN
MIN
C
13
MAX
2,150
/C
2,175
Quality Factor
12
11
2,125
C
Quality Factor
15
10
2,100
9
2,075
8
2,050
7
2,025
6
5
2,000
0,4
0,5
0,6
0,7
0,8
0,9
1,0
1,1
1,2
1,3
1,4
1,5
1,6
1,7
Length [um]
Figure 2.14: QVCO varactor
Cmax
Cmin
characteristic
the varactors length. For high quality factor the minimum length is needed; as a consequence the tuning range decreases. We can observe in Eq: 2.2 and Eq: 2.3 that for
frequencies higher than 10 GHz, QL increases with the frequency while QC decreases.
For this reason, a carefully varactor design is very important to get a good tank quality
factor.
The total fixed capacitance accounting for inductor, two cross-coupled pair and buffer
plus minimum varactor capacitance is 61.5 fF. In order to set the center frequency
around 15 GHz, a 290 pH octagonal one turn coil inductance has been selected. A compact model as that described in [6] (Figure: 2.15a) was extracted from electromagnetic
simulations carried out both with the 2D 21 electromagnetic simulator Momentum by
Agilent Technologies and with the 3D electromagnetic simulator by CST. The inductor
exhibits an inductance of about 290 pH and a maximum quality factor in the range of
27 (Figure: 2.15b). It is worth pointing out that these values of inductance and quality
factor are very close to those claimed in [11] for a 65 nm CMOS LC VCO working in the
Ku-band. The parallel between the inductor quality factor and the minimum varactor
quality factor (Eq: 2.9) gives a value close to 11 for the total tank quality factor.
For sake of good locking capability and flicker noise minimization, the coupling Nchannel transistors width was fixed equal to:
W
L
3,4,7,8
=
16 µm
0.3 µm
(2.32)
3,4,7,8
Frequency generation for mm-Wave and satellite applications
25
Ku band Oscillator
30,0
27,5
Cs
25,0
22,5
Out−
Rs
Cox
Out+
Cox
Quality Factor
20,0
Ls
17,5
15,0
12,5
10,0
7,5
5,0
Csub
Rsub
Csub
Rsub
2,5
0,0
0
5
10
15
20
25
30
35
Frequency [GHz]
(a) lumped model
(b) quality factor
Figure 2.15: VCO Inductor quality factor and lumped model.
2.3.2
Measurements results
Figure: 2.16 shows the microphotograph of the fabricated prototype. In the middle of
the chip are visible the two inductors of the VCO core. In the microphotograph are also
visible the two buffers to drive the load of the instruments. Under an experimental point
of view, the use of buffers is mandatory, in order to perform reliable measurements.
Without buffers, the losses of the external load connected to the circuit during the
characterization can degraded the VCO performances or, on the other hand, high-Q
lines connected to the pads via the coplanar probes and coaxial cables can improve
the VCO performances. The GSGSG pads for the differential in-phase (I+, I-) and in
Figure 2.16: QVCO microphotograph.
quadrature (Q+, Q-) RF output signals are visible on the top and on the bottom of
the chip, respectively. At the left side the GSG pad for the tuning voltage (VT U N E ) is
26
Frequency generation for mm-Wave and satellite applications
2.3 Quadrature Voltage Controlled Oscillator
visible. Eventually, three pads for the supply (VDD ) are distributed along the pad-ring.
The chip size is 900 · 1100 µm2 , pads enclosed. The differential output signals were
made available to the single-ended input of the Agilent E4408B spectrum analyzer using
a wideband Anaren 30070 hybrid. Figure: 2.17 reports the dependence of the output
16,0
15,8
Simulations
Measurements
Frequency [GHz]
15,6
15,4
15,2
15,0
14,8
14,6
14,4
-0,1
0,0
0,1
0,2
0,3
0,4
0,5
0,6
V
TUNE
0,7
0,8
0,9
1,0
1,1
1,2
1,3
[V]
Figure 2.17: Comparison between measured and simulated tuning range.
frequency on the tuning voltage. A difference less than 1.3 % between simulations and
measurements was obtained on the whole tuning range. The carrier frequency (f0 ) goes
from 14.6 GHz to 15.8 GHz for VT U N E ranging between 0 V and 11.2 V corresponding
to a tuning range of 7.4 %. The QVCO delivers about −20 dBm on a 50 Ω load and
it sinks 9.4 mA from a 1.2 V supply. Phase noise measurements were carried out using
an Agilent E5500 phase noise meter. Figure 2.18 shows the measured phase noise for
f0 =14.6 GHz. The QVCO exhibits a phase noise of −106 dBc/Hz at the offset frequency
(∆f) of 1 MHz, and −129.5 dBc/Hz at the offset frequency (∆f) of 10 MHz. This value
is very close to the −107 dBc/Hz at the offset frequency (∆f) 1 MHz recently claimed
for the VCO used in the PLL of a monolithic Ku-band receiver [12]. For other values of
applied VT U N E the phase noise did not change in agreement with simulations.
The performance of the fabricated QVCO has been compared with other 130 nm
CMOS VCO reported in the literature through FOM in Eq: 2.17 and the FOMT in the
Eq: 2.26.
The FOM are −178.56 dBc/Hz at the offset frequency of 1 MHz and −182.28 dBc/Hz at
the offset frequency of 10 MHz.
The FOMT are −175.91 dBc/Hz at the offset frequency of 1 MHz and −179.63 dBc/Hz
at the offset frequency of 10 MHz. The FOMT is worse then FOM because of the tuning
range. Table 2.1 and Figure 2.19 compare the designed QVCO with the state of the art
Frequency generation for mm-Wave and satellite applications
27
Ku band Oscillator
-20
-30
Simulations
-40
Measurements
Phase Noise [dBc/Hz]
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
1k
10k
100k
1M
10M
Frequency [Hz]
Figure 2.18: Comparison between measured and simulated phase noise.
of VCO designed in 0.13 µm CMOS technology.
Table 2.1: VCO CMOS 0.13 µm state of art.
Tech.
Freq.
TR
Voltage
PDISS
L @ 1 MHz
FOM
FOMT
[µm]
[GHz]
[%]
[V]
[mW]
[dBc/Hz]
[dBc/Hz]
[dBc/Hz]
[13]
0.13
4.91
15
0.8
3.2
−112
−180.8
−184.3
[14]
0.13
5
20
1.2
5.28
−117
−183.8
−189.8
[15]
0.13
5.1
[16]
0.13
11.2
[17]
0.13
[18]
[19]
THIS
Ref
5.26
1.2
3.7
−118
−186.7
−181.1
n.a.
0.8
4.8
−106
−180.2
n.a.
20
10.2
n.a.
32
−102
−173.4
−174.6
0.13
20
12
n.a.
20
−101
−174.0
−175.6
0.13
26
3.1
1.35
24
−96
−170.5
−160.3
0.13
14.6
7.4
1.2
11
−106
−178.6
−175.9
In conclusion, a 130 nm CMOS QVCO exhibiting a central frequency of 15 GHz
has been demonstrated. The phase-noise-related FOM is well aligned with other 130 nm
CMOS VCOs reported in the literature. In particular, the comparison with other CMOS
VCOs claimed in the literature for Ku-band satellite receiver, with the DVB-S standard,
28
Frequency generation for mm-Wave and satellite applications
2.3 Quadrature Voltage Controlled Oscillator
-170
[19]
-172
[18]
-174
FOM [dBc/Hz]
[17]
-176
-178
[16]
[13]
-180
This
work
-182
[14]
-184
[15]
-186
-188
2,5
5,0
7,5
10,0
12,5
15,0
17,5
20,0
22,5
25,0
27,5
30,0
Frequency [GHz]
Figure 2.19: VCO CMOS 0.13 µm state of the art.
and with commercial products implemented in SiGe BiCMOS technologies suggests that
the 130 nm CMOS technology can be evaluated with interest for the design of a DVB-S
satellite receiver front-end. Since the VCO has to be employed in a PLL, the measured
Figure 2.20: Simulated PLL phase noise (black curve).
Frequency generation for mm-Wave and satellite applications
29
Ku band Oscillator
phase noise depicted in Figure 2.18 has been therefore inserted in a PLL simulation
carried out with Matlab. The noise contributions of the pre-scaler, of the phase and
frequency detector, and of the reference have been set to typical values. The loop filter
was designed so that to obtain a PLL bandwidth of 400 kHz and a phase margin of
60◦ . Figure 2.20 shows the simulated phase noise (black curve). The white lines are
the contributions of the single building blocks. The PLL phase noise is very close to
the DVB-S phase noise specifications (open circles) at the offset frequencies of 100 kHz
and 1 MHz [20]. The simulated phase noise is higher than standard limit in the offset
frequency range 100 kHz - 1 MHz. The simulated phase noise is also comparable with the
phase noise exhibited by the TFF1004HN commercial product [21] and it is better for
offset frequencies lower than 100 kHz. As further discussion about Figure 2.20, it is worth
pointing out that the phase noise and, in particular, the tuning range specifications have
to be addressed by introducing a switched capacitor bank in the VCO topology during
the design of the final PLL [22].
The quadrature outputs measurements have not carried out because we don’t have
the instrumentations for this kind of measurements at 15 GHz.
30
Frequency generation for mm-Wave and satellite applications
millimeter Wave PLL
3
This chapter introduces the main mmW applications at 60 GHz, 77 GHz and
94 GHz. In particular, this chapter reports on the design of the VCO and the
division chain of a Phase-Locked Loop for WPAN applications. The blocks
are designed in Si CMOS 65 nm technology.
3.1
Phase-Locked Loop
Phase-Locked Loops (PLL), as mentioned earlier, have a variety of applications. However, in this work we will focus on their use as a frequency synthesizer. In a Charge-Pump
PLL (CPPLL) based frequency synthesizer [23], a frequency divider is inserted in the
feedback path, as depicted in Figure 3.1. The Phase-Frequency Detector (PFD) receives
at one input the low-frequency low-noise input signal (running at fREF ) and at the other
one the signal coming from the feedback. It compares their phase and frequency and it
generates a digital waveform at output. This digital waveform, which is a train of voltage pulses, is then transformed into a train of current pulses by the Charge-Pump (CP),
which output is averaged by the low-pass Loop Filter (LF) to produce the tuning voltage
that controls the VCO oscillation frequency, namely fOU T . As clearly seen in Figure 3.1,
the signal at frequency fOU T is not simply used as the output of the system, but is also
divided down by M (an integer number known as the frequency divider division module)
and fed back to the other input of the PFD. After a given settling time (related to the
loop bandwidth), as a result of the negative feedback action performed by the loop, the
phase and frequency of the output signal will be precisely related (locked) to the phase
and frequency of the reference signal, which is both a stable and a low-noise source.
In Figure 3.1, starting from a reference signal at frequency fREF , an output frequency
M times higher is obtained, i.e. fOU T = M · fREF . By varying the frequency divider
division module M in integer steps acting on the FCW, it is possible to vary the output
frequency fOU T with a frequency resolution equal to fREF . This architecture is thus
known as Integer-N frequency synthesizer.
In order to handle several tightly spaced channel, e.g. for the Global System for
31
millimeter Wave PLL
LF
fREF
VCO
PFD
CP
fOU T
Frequency Divider
÷M
FCW
Figure 3.1: General block diagram of a CPPLL.
Mobile communication (GSM) a channel spacing of 200 kHz is used while the received
frequency is at 1.8 GHz, it is of course desirable to increase the frequency resolution,
which in turn requires lowering the reference frequency. Stability considerations require
the loop bandwidth BW to be lower than the reference frequency (as a rule-of-thumb,
BW ≈ fREF /10 [23]), thus lowering fREF means lowering BW . Indeed, lowering the
bandwidth of the loop has some drawbacks, for instance:
• the correcting action performed by the negative feedback as a result of, let’s say, a
variation in the division module M , will be slowed down (the settling time TS of
−1
the loop is inversely proportional to its bandwidth, i.e. TS αBW
);
• the VCO phase-noise undergoes high-pass filtering while passing through the loop.
So its suppression will be poorer if the bandwidth is decreased (this is a big issue
in CMOS technology because of the high MOS flicker noise level).
To solve these problems, the constraint that the divider division module must be an
integer number has to be broken, in particular modifying (dithering) dynamically its
value such that on the average a fractional division module is produced; for this reason,
such an architecture is known as Fractional-N frequency synthesizer: in this way the
frequency resolution is no more dependent on the reference frequency.
In the end, the objective is to produce a division module that is a fractional number
by switching between N and N + 1; using an accumulator and a dual-modulus frequency
divider (also called prescaler), as depicted in Figure 3.2, allows to achieve this result:
assuming that the loop is locked and the division module is set to N , at each divider
output pulse the accumulator value is increased by n [k]; once its internal state reaches
or surpasses the full-scale, the carry output (called cO [k] in Figure 3.2) is asserted, thus
the division module is set to N + 1 for the entire cycle. The result is that, on the average,
the divider module turns out to be a fractional number [2].
32
Frequency generation for mm-Wave and satellite applications
3.1 Phase-Locked Loop
LF
fREF
VCO
PFD
CP
fOU T
Prescaler
÷N/N + 1
CK
n [k]
Σ
NAV G = N + n [k]
cO [k]
Figure 3.2: General block diagrams of a fractional CPPLL.
3.1.1
PLL linear model
Phase-Locked Loop are feedback systems which are inherently non-linear. However,
their essential operation can be approximated very well by linear analysis. In such an
analysis, the Laplace transform is a valuable tool. The concept of transfer functions,
which describe the s- domain relation between input and output of a linear circuit, is
used to analyze the open-loop and closed-loop characteristics of the PLL.
In [24], the phase of a locked PLL is described with the mathematical model depicted
in Figure 3.3 where Kφ represents the PFD, Z (s) the LF loop filter, KV CO /s is the VCO
and 1/N the frequency divider transfer functions.
Assuming that Figure 3.3 represents a general CPPLL, as it is done in [24], cutting
the feedback and taking the ratio θI /θE gives the open loop gain GLOOP :
GLOOP (s) =
Kφ Z (s) 2πKV CO
θI
=
θE
N
s
(3.1)
where Kφ = KP F D · ICP / (2π) is the gain of the PFD-CP combination and Z (s) the LF
transfer function. A 2π factor has been added to the KV CO gain to take into account
the frequency-to-phase conversion. The LF transfer function, Z (s), depends of the filter
chosen. A simple choice is a 2nd -order passive LF, depicted in Figure 3.4a; in Figure 3.4b
is depicted a 3rd -order passive LF, which is an alternative to the 2nd -order LF to be used
when a stronger spurs suppression is required. Since the VCO itself introduces a pole
in the origin in the transfer function and the 2nd -order LF adds other two poles, the
resulting overall PLL is a 3rd -order system; on the other hand, if a 3rd -order LF is used,
the resulting overall PLL is a 4th -order system.
Frequency generation for mm-Wave and satellite applications
33
millimeter Wave PLL
ΘE
ΘREF
Kφ
KV CO
s
Z (s)
ΘOU T
ΘI
1
N
Figure 3.3: Generalized PLL linear model.
ICP
VT U N E
R3
ICP
R2
VT U N E
R2
C1
C1
C3
C2
C2
(a)
(b)
Figure 3.4: Analog LFs of: (a) 2nd and (b) 3rd -order.
The 2nd -order passive LF transfer function is equal to:
1
1
//
sC2
sC1
1 + sR2 C2
s2 (C1 C2 R2 ) + s (C1 + C2 )
1
1
1 + sR2 C2
·
·
C2
s C1 + C2 1 + sR2 CC1+C
1
2
1
1 + sTZ
1
·
·
s C1 + C2 1 + sTP
1 TP 1 + sTZ
·
·
sC1 TZ 1 + sTP
Z (s) = R2 +
=
=
=
=
(3.2)
(3.3)
(3.4)
In Equation (3.3) and Equation (3.4) the zero and pole time constants, TZ = R2 C2 and
TP = R2 C1 C2 / (C1 + C2 ) respectively, have been defined. As expected, the 2nd -order
LF transfer function contains two poles. Substituting Equation (3.4) in Equation (3.1)
for Z (s), the 3rd -order open loop gain GLOOP useful in the design process is obtained:
GLOOP (s) =
2πKφ KV CO
1
TP 1 + sTZ
·
·
·
sN
sC1 TZ 1 + sTP
(3.5)
which, if plotted versus the frequency, assumes the general form sketched in Figure 3.5.
34
Frequency generation for mm-Wave and satellite applications
3.1 Phase-Locked Loop
−20 dB/dec
−40 dB/dec
0 dB
|GLOOP | (dB)
−40 dB/dec
1
2·π·TP
1
2·π·TZ
GLOOP (◦ )
f (Hz)
PM
−180◦
1
2·π·TZ
BW
1
2·π·TP
f (Hz)
Figure 3.5: 3rd -order system open loop gain Bode plot.
In Figure 3.5 both the phase margin P M and the bandwidth BW are highlighted.
The LF component can be designed to achieve the target P M and BW as follows: from
the inspection of Figure 3.5, the phase margin P M is defined as the difference between
−180◦ and the open loop transfer function phase at the frequency corresponding to a
0 dB gain. In order to insure stability, the phase margin must be chosen between 30◦
and 70◦ : choosing higher phase margin gives higher stability but with a slower transient
response.
Since s = jω, Equation (3.5) is equivalent to:
GLOOP (jω) = −
2πKφ KV CO TP 1 + jωTZ
·
ω 2 N C1 TZ
1 + jωTP
(3.6)
The magnitude of the open loop gain is then equal to:
|GLOOP
q
1 + (ωTZ )2
2πKφ KV CO TP
q
(ω)| =
·
ω 2 N C1 TZ
1 + (ωTP )2
(3.7)
On the other hand, the phase of the open loop gain is then equal to:
GLOOP (ω) = 180 + arctan (ωTZ ) − arctan (ωTP )
(3.8)
which has the trend expected from Figure 3.5.
In order to compute the frequency value for which the phase reaches the maximum
in term of TZ and TP , the derivative of Equation (3.8) must be computed. First of all,
recall the notable derivative from mathematical analysis:
f ′ (x)
d
arctan (f (x)) =
dx
1 + f 2 (x)
Frequency generation for mm-Wave and satellite applications
(3.9)
35
millimeter Wave PLL
Then, the derivative of Equation (3.8) is taken and set equal to zero:
d
GLOOP (2πBW ) = 0
dω
TZ
TP
=0
(3.10)
2 −
1 + (2πBW TZ )
1 + (2πBW TP )2
√
which, solved for the bandwidth, gives BW = 1/ 2π TZ TP . Substituting ω = 2πBW
in Equation (3.8) and the resulting equation in the phase margin definition, i.e.
P M , −180 + GLOOP (BW ):
P M = arctan (2πBW TZ ) − arctan (2πBW TP )
(3.11)
and then applying the tangent operator at both the members:
tan (P M ) = tan [arctan (2πBW TZ ) − arctan (2πBW TP )]
(3.12)
Applying the trigonometric identity:
tan (α − β) =
tan α − tan β
1 + tan α · tan β
(3.13)
into left side of Equation (3.12):
tan [arctan (2πBW TZ )] − tan [arctan (2πBW TP )]
1 + tan [arctan (2πBW TZ )] · tan [arctan (2πBW TP )]
2πBW TZ − 2πBW TP
=
(3.14)
1 + (2πBW )2 TZ TP
√
From Equation (3.10) BW = 1/ 2π TZ TP , then Equation (3.14) simplifies in:
tan (P M ) =
2 · tan (P M ) = 2πBW TZ − 2πBW TP
(3.15)
i
h
and substituting TZ = 1/ (2πBW )2 TP into Equation (3.15) gives the second order
equation:
(2πBW )2 TP2 + 2 · tan (P M ) · (2πBW ) TP − 1 = 0
(3.16)
Solving Equation (3.16) for TP and discarding the negative solution (since it is a time
constant its value is bounded to values greater than 0):
TP =
q
1 + tan2 (P M ) − tan (P M )
2πBW
=
sec (P M ) − tan (P M )
2πBW
(3.17)
√
where the identity 1 + tan2 α = 1/ cos α = sec α has been exploited.
Since TP has been calculated and BW is known, TZ is found as:
TZ =
36
1
(2πBW )2 TP
Frequency generation for mm-Wave and satellite applications
(3.18)
3.1 Phase-Locked Loop
To summarize, for given phase margin and bandwidth values, the pole and zero time
constants are found using Equations (3.17) and (3.18), respectively.
The following step, which allows to synthesize a LF which satisfies to the P M and BW
constraints when inserted in the loop, i.e. it introduces a zero and a pole at respectively
1/ (2πTZ ) and 1/ (2πTP ), is to compute C1 , C2 and R2 . From Figure 3.5, for a frequency
equal to BW , the magnitude of the open loop gain is unitary; therefore substituting
ω = 2πBW in Equation (3.7) and equating the result to one allows to compute the value
of C1 :
|GLOOP (2πBW )| = 1
q
1 + (2πBW TZ )2
2πKφ KV CO TP
q
C1 =
·
·
(2πBW )2 N TZ
1 + (2πBW TP )2
(3.19)
Furthermore, recall that TZ = R2 C2 and TP = R2 C1 C2 / (C1 + C2 ). Solving the ratio
TZ /TP for C2
TZ
−1
(3.20)
C2 = C1
TP
while solving TZ for R2 :
R2 =
TZ
C2
(3.21)
This method allows to design a LF for given values of open loop bandwidth BW ,
phase margin P M , VCO gain KV CO , CP current ICP , PFD gain and divider division
module N , so in the end to synthesize the required CPPLL.
If a 3rd -order LF is used, the attenuation introduced is [24]:
h
i
αdB = 20 log (2πfREF R3 C3 )2 + 1
that can be solved for the time constant TP 3 = R3 C3 :
TP 3 =
q
(3.22)
αdB
10 20 − 1
2πfREF
(3.23)
The additional pole must be lower than the reference frequency, in order to significantly
attenuate the spurs, but must be at least 5 times higher than the loop bandwidth, or
the loop will almost assuredly become unstable.
In order to compensate for the added low-pass section, the filter component values
are recalculated using the new open loop unity gain frequency, BC [24]:
BC =
tan (P M ) · (TP + TP 3 )
h
2π (TP + TP 3 )2 + TP TP 3
s
i·

(TP + TP 3 )2 + TP TP 3
 1+
− 1
tan (P M ) · (TP + TP 3 )
Frequency generation for mm-Wave and satellite applications
(3.24)
37
millimeter Wave PLL
Then, also TZ is modified as follows:
TZ =
1
(2πBC ) (TP + TP 3 )
(3.25)
2
and C1 as:
TP Kφ KV CO
·
C1 =
TZ (2πBC )2 N
v
u
u
u
· th
h
1 + (2πBC TZ )2
1 + (2πBC TP )2
ih
i
1 + (2πBC TP 3 )2
i
(3.26)
On the other hand, C2 and R2 are still derived from Equations (3.20) and (3.21), respectively.
The only component values that still remain to be determined are therefore C3 and
R3 : being bounded by Equations (3.22) and (3.23), their values are somewhat arbitrary.
As a rule of thumb C3 can be chosen equal to C1 /10 otherwise TP 3 will interact with the
primary poles of the filter. Likewise, R3 must be chosen at least twice the value of R2 .
Although not exact, the linear assumptions used in this design technique provide
good results for loop filter bandwidths of up to one-fifth of the reference rate [24, 2].
3.2
Frequency Divider
Frequency Divider (FD) can be categorized into digital or analog. The digital class
of dividers is sub-divided into static and dynamic FDs whereas the analog consist of
regenerative or Miller divider and Injection-Locked (IL) Frequency Divider.
3.2.1
Static Frequency Divider
Static FD (SFD) are one of the most widely used class of dividers [25, 26]. They are
usually based on an edge-triggered flip-flop in a negative feedback loop. The flip-flop
is composed of two master and slave D-latches which are driven by anti-phase clock
pulses. Figure 3.6 shows a standard Static FD. The dividing operation is achieved by
connecting the inverted slave outputs to master D-latch inputs. Seen as a two stage
ring oscillator, static frequency dividers can provide highly matched quadrature outputs
which are required in the two step down-conversion in a transceiver.
In principle, any type of latch can be utilized in a SFD. However, traditional CMOS
rail-to-rail implementations lead to long rise and fall times, resulting in low operation frequencies. In addition, the single-ended structure also suffers from supply noise coupling,
potentially introducing jitter in the output. MOS current mode logic (MCML or just
CML) sometimes also referred to as source coupled logic SCL, is a better alternative for
D-latch implementation [27]. This logic family is characterized by, firstly, small voltage
swings thus reducing the rise and fall times and enhancing the operation frequency. Secondly, the differential and current steering nature of MCML reduces the switching and
supply noise resulting in a spur-free synthesizer output spectrum and lastly, it consumes
38
Frequency generation for mm-Wave and satellite applications
3.2 Frequency Divider
D latch 1
D1
Q1
D1
Q1
D latch 2
CK1 CK1
D2
Q2
D1
Q2
CK2 CK2
CK
CK
Figure 3.6: SCL based divide-by-two frequency divider.
VDD
RL
D
D
CK
RL
M3
M4
Q
Q
M5
M6
M1
M2
CK
ISS
Figure 3.7: SCL D latch.
a constant current, hence the name static frequency divider. A D-latch based on MCML
logic is shown in Figure 3.7. The maximum operation frequency of the SFD depends on
the propagation delay from input D to output Q in a D-latch and can be estimated by:
fmax ≤
1
τdp
(3.27)
where τdp is the propagation delay. In a differential circuit (such as CML logic) τdp for
rising and falling edge is identical and in first order, proportional to the charging time
constant τL , i.e.,
τdp ∝ τL = RL CL
(3.28)
where RL is the load resistance and CL is the total capacitance at the output node
Frequency generation for mm-Wave and satellite applications
39
millimeter Wave PLL
consisting of parasitic contribution from the latch transistors M4 − M6 , output buffer
transistors (not shown in Figure 3.7) and layout interconnects. It is evident that, to
maximize speed, τL or RL and CL should be minimized. However, there is a tradeoff between the two passive values. If RL decreases, the gain gm RL of the transistors
M3 − M4 also decreases. In order to compensate this decrease, larger transistors are
required to boost the gm thus increasing the total capacitance. On the other hand if CL
is reduced by using smaller transistors, RL needs to be increased to maintain a sufficient
output voltage swing. Techniques such as inductive peaking [25, 28], distributed loading
and LC-tank loading [29] have been employed to increase the bandwidth of SFDs.
A large number of static frequency dividers have been reported in the frequency
range up to 40 GHz [25, 28, 30, 31, 32, 33, 34] and a few implementations above 60 GHz
[2].
3.2.2
True Single Phase Clock
The True Single Phase Clock (TSPC) logic was firstly proposed in [35], to overcome
the problems of the clocked CMOS logic which requires a non-overlapping pseudo twophase clock to work properly; in the end this means that four clock signals have to be
distributed and between these two pairs no overlap should occur. Of course, clock skews
in the system will cause serious problems, which are exacerbated with the increasing of
the operating speed. On the other hand, TSPC logic requires only one clock signal, thus
avoiding the skew problem present in the clocked CMOS logic.
In Figure 3.8a is proposed a TSPC positive-edge triggered register, while in Figure 3.8c is proposed a TSPC divide-by-two frequency divider. The TSPC positive-edge
triggered register of Figure 3.8a works as follows: when CK is low MP 1 is ON thus the
series of MN 1 , MP 1 and MP 2 behaves as an inverter, sampling the data D and inverting
it at node G3 . Furthermore, since CK is low MN 2 is OFF. As a consequence, even if G3
is high, the pull-down network is OFF: the only path for the current is through MP 3 ,
thus when CK is low MP 3 pre-charges node D3 to VDD . As a consequence, both MN 5
and MP 4 are OFF because the gate of MN 5 is held low by the CK while the gate of
MP 4 is held high by D3 and therefore the output Q is holding the previous state being
floating (high-impedance level).
To sum up, when CK is low:
• the inverter MN 1 , MP 1 and MP 2 is ON and thus it samples and inverts the input
D at node G3 ;
• the inverter MN 2 , MN 3 and MP 3 is OFF and thus MP 3 is pre-charging node D3
at VDD ;
• the inverter MN 4 , MN 5 and MP 4 is OFF and thus the output Q is floating, i.e.
the output of the previous state is held stable.
On the clock rising edge, the inverter MN 2 , MN 3 and MP 3 evaluates the data at
node G3 because MP 3 is now OFF while MN 2 is ON, so the value of D3 depends on
40
Frequency generation for mm-Wave and satellite applications
3.2 Frequency Divider
the logic level at node G3 : if G3 is high then D3 is discharged to ground, otherwise D3
stays at VDD . The inverter MN 4 , MN 5 and MP 4 is now ON because MN 5 is turned ON
by the high CK: the level of D3 is then inverted and transferred to the output Q (the
input data D has undergone three inversions and thus it is copied in its complementary
form at output Q).
During the positive clock phase there is one criticality: if data D is high, since the
MN 1 , MP 1 and MP 2 inverter pull-up network is OFF, node G3 is discharged to ground
by MN 1 . As a consequence, the input must be kept stable until the value at node G3
has propagated correctly to node D3 : this is the hold time of the register. The overall
propagation delay, on the other hand, is roughly equal to three times the delay of one
inverter.
(V)
VDD
D
MP 3 3
MP 2
D
MP 1
G3
CK
MP 4
D
Q
MN 3
MN 5
MN 2
MN 4
G3
D3
MN 1
Q
0
CK
(b) Transient response of Figure 3.8a.
(a) Register.
OU T
(V)
VDD
CK
MP 2
MP 1
T 2T 3T 4T 5T 6T 7T 8T 9T
t (s)
G3
MN 1
D
MP 3 3
MP 4
G3
MN 3
MN 5
D3
MN 2
MN 4
OU T
0
CK
(c) Divide-by-two frequency divider.
T 2T 3T 4T 5T 6T 7T 8T 9T
t (s)
(d) Transient response of Figure 3.8c.
Figure 3.8: TSPC based: (a) register and (c) divide-by-two frequency divider.
Passing from the TSPC register described to a divide-by-two-frequency divider is
quite simple: it is enough to connect nodes Q and D with a feedback, as in Figure 3.8c.
In Figure 3.8d it is depicted the divider transient response: assume that CK is low; as a
result, MP 3 keeps D3 at VDD . As soon as the clock goes high, MN 4 and MN 5 turn ON
lowering OU T . At the next clock negative pulse, at t = 1.5T , since OU T and CK are
both low, MP 1 and MP 2 turn ON so G3 goes high. At t = 2T , when CK is high, MN 2
Frequency generation for mm-Wave and satellite applications
41
millimeter Wave PLL
and MN 3 turn ON lowering D3 , then OU T will go high (after an inverter propagation
delay); after another inverter propagation delay also MN 1 will turn ON lowering G3 .
The next clock negative pulse charges D3 to VDD by means of MP 3 . At 3T , when both
CK and D3 are high, MN 4 and MN 5 turn ON lowering OU T . Then at t = 3.5T , when
both CK and OU T are low, MP 1 and MP 2 turn ON again so G3 goes high. At the next
clock pulse the result is that D3 goes low, so OU T goes high and the cycle will start
again from the beginning.
The transistors’ sizing is of course critical to achieve a correct functionality. There
are no general guidelines, but the following example helps in focusing a problem related
to the TSPC register and explain how to correct it if, from simulation results, it turns out
that the TSPC register is affected by this kind of problem. Consider the following case:
CK low, D low (which means G3 high) and also Q low [36] (Q is obtained by inverting
Q with an inverter). As explained, node D3 is pre-charged to VDD , thus MN 4 turns ON.
When CK goes high, both D3 and Q begin to discharge: D3 discharges through MN 2
(that is ON since CK is high) and MN 3 (that is ON since G3 is high by hypothesis) while
Q discharge through MN 4 (that is ON since D3 is pre-charged to VDD ) and MN 5 (that
is ON since CK is high). Once D3 is low enough, Q is pulled high by MP 4 . This results
in a glitch in the output which may cause fatal errors. To avoid this problem, care must
be taken in increasing the relative strength of the MN 2 − MN 3 pull-down network with
respect to that of the MN 4 − MN 5 pull-down network, so that D3 discharges faster then
Q.
Also in [35] the sizing of the transistors is discussed: neither there design guidelines
are given since this is a complex problem because the speed of a CMOS circuits depends
in a complex way on the sizes as they influence both the current capability and the
capacitance. The general rule is to just keep the transistors length as small as possible
(it is limited by the process), whereas the widths are optimized for speed; often, the
speed versus width function does not show an optimum but is monotonic: in such cases
the cost must be taken into account.
For simple structures, as an inverter chain, general rules exist for sizing: for example,
each inverter has devices that are three times larger than the previous inverter devices.
But for more complex structure it is not possible to obtain analytical results, so the best
thing to do is to vary the device sizes in a simulator or to use a computer tool developed
for automatic speed optimization through device sizing [2].
3.2.3
Regenerative frequency dividers
The working principle of regenerative frequency dividers can be explain with the aid of
Figure 3.9 [37]: one input of the mixer is fed with the input frequency fin , while the
other input with the output frequency fout . As a consequence, at the output of the
mixer two tones at fin ± fout appear, with lower amplitudes with respect to the input
fin because of the mixer action (this is why an amplifier with gain A is inserted in the
chain).
The action of the Low-Pass Filter (LPF) is to remove the tone at fin + fout so just
42
Frequency generation for mm-Wave and satellite applications
3.2 Frequency Divider
mixer
LPF
fin ± fout
fin
A
fout
Figure 3.9: Regenerative divide-by-two frequency divider block diagram.
the fin − fout frequency survives at the output of the loop; at the output node therefore
holds the relation:
fin
fin − fout = fout ⇒ fout =
(3.29)
2
As clear from Figure 3.9, this kind of dividers require many building blocks, so they are
not suited for low-power applications.
3.2.4
Injection Locking Frequency Dividers
Figure 3.10 depicts the model for an Injection-Locked Oscillator (ILO) proposed in [38].
If one supposes to ground the input signal vin , the model describes a free-running oscillator: for example, in a cross-coupled LC oscillator, the nonlinear block f (e), which
models all the nonlinearities of the system, is the cross-couple pair while the Band-PassFilter (BPF), which is a frequency selective block, is the LC tank. The output of the
nonlinear block is spectrally rich but the BPF extracts from it just the desired tone and
feeds it back to the input, closing the loop.
When vin is grounded, the system oscillates if the loop satisfies the Barkhausen
oscillation criteria:
(
|GLOOP | = 1
(3.30)
GLOOP = 0
where GLOOP is the loop gain. If a non-zero input is applied and the system has to keep
oscillating, the Barkhausen oscillation criteria must be indeed met.
If the goal is to realize an ILO that operates as a divide-by-two frequency divider,
the BPF must be tuned to fout . In addition, since a division-by-two must be achieved
so that fin = 2fout , the nonlinearity must be of the second order.
BPF
e
u
v
f (e)
f
in
out
Figure 3.10: Injection Locking Frequency Divider block diagram.
The advantage of this family of dividers is their low-power consumption because of
the reactive components used in the BPF which conserves the energy instead of wasting
it. On the other hand, the reactive components are also a disadvantage in the integrated
Frequency generation for mm-Wave and satellite applications
43
millimeter Wave PLL
realization because they use a large die area and also because they limit the bandwidth
[2].
3.3
Millimeter Wave IC Applications
The expression millimeter Wave (mmW) designates a RF band having a wavelength of
ten to one millimeter. According to the International Telecommunications Union (ITU)
radio regulations resumed in Table 3.1, it corresponds to the region of Extremely High
Frequency (EHF: 30 GHz to 300 GHz).
Table 3.1: International Telecommunications Union (ITU) Radio Band.
Nr
Symbol
Desigantion
Frequency Range
Wavelangth Range
1
ELF
2
SLF
Extremely Low Frequency
3 Hz to 30 Hz
100 000 km to 10 000 km
Super Low Frequency
30 Hz to 300 Hz
10 000 km to 1000 km
3
ULF
Ultralow Frequency
300 Hz to 3000 Hz
1000 km to 100 km
4
VLF
Very Low Frequency
3 kHz to 30 kHz
100 km to 10 km
5
LF
Low Frequency
30 kHz to 300 kHz
10 km to 1 km
6
MF
Medium Frequency
300 kHz to 3000 kHz
1 km to 0.1 km
7
HF
High Frequency
3 MHz to 30 MHz
100 m to 10 m
8
VHF
Very High Frequency
30 MHz to 300 MHz
10 m to 1 m
9
UHF
Ultrahigh Frequency
300 MHz to 3000 MHz
1 m to 0.1 m
10
SHF
Super High Frequency
3 GHz to 30 GHz
1 m to 0.1 m
11
EHF
Extremely High Frequency
30 GHz to 300 GHz
0.1 mm to 1 mm
In the context of microelectronics it is more useful to consider the wavelength in a
silicon oxide layer that is roughly half the wavelength in open space, according to the
well-known relation:
1
1
c
λ0
λ0
λox = √
= √ √
= √
=√
≈
f ǫox ǫ0 µ0
f ǫox ǫ0 µ0
f ǫox
ǫox
1.9
(3.31)
where the relative permittivity of silicon oxide ǫox is assumed to be equal to 3.6 and
frequency-independent.
A more appropriate placement of the millimeter wave band is therefore in the 15-158 GHz
range. In particular, we will consider as millimeter wave the electromagnetic spectrum
between 60 GHz to 110 GHz.
As a matter of fact, electronics at lower frequencies (at least up to 20-30 GHz) can rely
over the traditional radiofrequency design methods and techniques. On the contrary design of silicon-based integrated circuits operating in the 60-110 GHz range, requires the
development of a dedicated methodology capable to address the numerous difficulties
44
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
emerging along with the frequency increase.
Very recently the same design methodology has been gradually extended to higher frequency known as sub-millimeter wave or terahertz radiation, opening the way to the
so-called terahertz-electronics that however will not be considered in this thesis.
During the last few years, the interest towards mmWs has rapidly grown, leading to
the development of a large number of potential applications. As well, the recent improvements in silicon-based technologies like CMOS and BiCMOS processes have made
possible the realization of low-cost implementations of microelectronic systems operating
in the millimeter wave band.
Without any presention of being exhaustive, the next three sections give an overview of
the most common applications in millimeter wave band such as Wireless Personal Area
Network (WPAN), high data rate wireless communications at 60 GHz, short and long
range radar at 77-79 GHz, and imaging systems at 94 GHz [39].
3.3.1
Millimeter wave applications at 60 GHz
The 60GHz band [40, 41] has attracted the interest of researchers in the past several
years, as it offers ample and license-free bandwidth. This advantage becomes more
evident when considering that the availability of about 7 GHz of unlicensed bandwidth
is guaranteed in many countries worldwide, as shown in Figure 3.11. For example, the
range from 57 GHz to 64 GHz is currently available in the US, while 59 GHz to 66 GHz
are available in Japan. Furthermore 60 GHz band is less restrict in terms of power limits
when compared to other concurrent wideband systems, like Ultra-Wideband (UWB), for
instance. These characteristics make 60 GHz technology particularly suited for gigabit
wireless applications that currently are technically constrained at lower frequency.
Figure 3.11: Worldwide frequency allocation for 60 GHz band and operation.
Frequency generation for mm-Wave and satellite applications
45
millimeter Wave PLL
As depicted in Figure 3.12, the atmospheric absorption presents a peak at 60 GHz
due to oxygen absorption that puts a severe limit on the distance that 60 GHz transmissions can handle - at least in the case of low-power applications - limiting it to
close-range communications. In home-space, however, oxygen absorption is not a big
problem, so 60 GHz is beginning to look like a useful way to provide dramatic speed-ups
over traditional Wireless Local Area Networks (WLANs) and is particularly indicated for
Wireless Personal Area Network (WPAN)s. A WPAN is designed to provide short-range
(<10 m), very-high-speed (>2 Gb/s) multi-media data services to computer terminals
and consumer appliances located in rooms, office space, "hot spots" and kiosks.
Figure 3.12: Atmospheric absorption of millimeter wave.
Wireless PANs will provide higher data rates, and shorter range, than comparable
WLANs but long enough to cover the size of most offices, medium-size conference rooms,
and rooms in personal home. Various electronic devices could be interconnected, including laptops, cameras, and monitors. Potential applications include wireless display,
wireless docking station, and wireless streaming of data from one device to the other.
A 60 GHz link could be used to replace various cables used today in the office or home,
including gigabit Ethernet (1 Gbps), USB 2.0 (480 Mbps), or IEEE 1394 (800 Mbps).
Currently, the data rates of these connections have precluded wireless links, since they
require so much bandwidth. While other wireless standards are evolving to address this
46
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
market (802.11n and UWB), 60 GHz is still a viable candidate.
Figure 3.13: Example of Wireless Personal Area Network applications.
Besides oxygen absorption in open-space, different materials affect the propagation
of 60 GHz signals in different ways and, whereas plasterboard or drywall absorption is
not much greater than in the case of 2.4 GHz signals, other materials, on the contrary,
cause a big fall-off in signal strength. Also human skin, for instance, absorbs 60 GHz
radiation pretty efficiently and crossing a link between a computer and a media player
synchronized over a 60 GHz system would break it.
To reduce the effect of absorption loss, many solutions such as directional antennas or
beamforming techniques are currently investigated. If sufficient directionality is guaranteed in transmission, then atmospheric and material properties could also prove more of
a benefit than a limitation, since they can prevent the signal from leaking into adjacent
environment, reducing the risk of interference and enhancing security [39].
Standards and Regulations for 60 GHz WPAN applications
Several attempts of standardization have been recently proposed or are still in course
of definition. For example, the IEEE 802.15 Task Group 3c is working since 2005 on
the Wireless Personal Area Network (WPAN), leading to the definition of the IEEE
802.15.3c standard in September 2009 [42, 43]. Besides, Wireless HD [44], the Wireless
Gigabit Alliance (WiGig)[45], the IEEE 802.11ad working group [46] and the ECMA387 [47] have been also making standardization efforts on the 60 GHz frequency band.
A detailed description of these documents is beyond the interest of this thesis; however
Frequency generation for mm-Wave and satellite applications
47
millimeter Wave PLL
the most important features of the IEEE and the ECMA standards are briefly described
hereafter.
IEEE Std 802.15.3c is an amendment to IEEE Std 802.15.3 that defines a Physical
Layer (PHY) operating in the millimeter Wave band and the necessary modifications to
the Medium Access Control (MAC) changes to support this PHY.
The PHY defines three operational modes as follows:
• Single Carrier (SC) mode optimized for low power and low complexity.
• High-Speed Interface (HSI) mode optimized for low-latency bidirectional data
transfer.
• Audio/Visual (AV) mode optimized for the delivery of uncompressed, high-definition
video and audio.
For devices that implement the mmW PHY, at least one of the three PHY modes is
required. In addition, to promote coexistence and interoperability, a Common Mode
Signaling (CMS) is defined based on a low data rate SC PHY mode.
The single carrier mode in mmW PHY (SC PHY) provides three classes of modulation
and coding schemes targeting different wireless connectivity applications. As summarized in Table 3.2, Class 1 is specified to address the low-power low-cost mobile market
while maintaining a relatively high data rate of up to 1.5 Gb/s; Class 2 is specified
to achieve data rates up to 3 Gb/s; Class 3 is specified to support high performance
applications with data rates in excess of 3 Gb/s.
Table 3.2: Modulation and Coding Schemes Classes in the SC PHY.
Class
Categorization
1
Data rate < 1.5 Gb/s
2
1.5 Gb/s < Data rates < 3 Gb/s
3
Data rates > 3 Gb/s
The SC PHY supports a wide range of modulations, π2 BPSK, π2 QPSK, π2 8-PSK, π2
16-QAM, pre-coded MSK, pre-coded GMSK, on-off keying (OOK), and Dual Alternate
Mark Inversion (DAMI). It operates on four RF channels, as defined in Table 3.3. A
compliant implementation shall support at least 1 channel from the channels allocated
for operation by its corresponding regulatory body.
48
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
Table 3.3: RF Channels for mmW PHY.
Start Freq.
Center Freq.
Stop Freq.
[GHz]
[GHz]
[GHz]
1
57.24
58.32
59.40
2
59.40
60.48
61.52
3
61.56
62.64
63.72
4
63.72
64.80
65.88
Channel ID
The high speed interface mode of mmW PHY (HSI PHY) is designed for devices
with low-latency, bidirectional high-speed data and uses Orthogonal Frequency Division
Multiplexing (OFDM). HSI PHY supports a variety of modulation and coding schemes
(MCSs) using different frequency-domain spreading factors, modulations, and LDPC
block codes.
The Audio/Visual (AV) PHY is implemented with two PHY modes, the High-Rate PHY
(HRP) and Low-Rate PHY (LRP), both of which use Orthogonal Frequency Division
Multiplexing (OFDM). The data rates supported by the HRP and the LRP are defined
in Table 3.4 and Table 3.5, respectively.
Table 3.4: AV HRP data rates.
HRP mode index
0
Modulation
QPSK
Data rate [Gb/s]
0.952
1
QPSK
1.904
2
16-QAM
3.807
3
QPSK
1.904
4
16-QAM
3.807
5
QPSK
0.952
6
QPSK
1.904
Table 3.5: AV LRP data rates.
LRP mode index
Modulation
0
1
2
3
Data rate [Gb/s]
0.952
BPSK
1.904
3.807
1.904
Frequency generation for mm-Wave and satellite applications
49
millimeter Wave PLL
Different PHYs are a result of demands of different market segments. For example,
one usage model is for kiosk applications. This usage model requires 1.5 Gb/s at a 1 m
range. The SC-PHY can provide such a data rate at that short range with less complexity thus lower cost than an OFDM PHY. Another usage model is required by the
streaming of uncompressed video. Due to the nature of uncompressed video signals, a
special PHY, the AV PHY, was selected to provide high throughput. A third usage
model involves an ad-hoc system to connect computers and devices around a conference
table. In this usage model, all of the devices in the WPAN will have bidirectional, NonLIne-Of-Sight (NLOS) high speed, low-latency communication, which is provided for by
the HSI PHY.
Besides the suggestions for MAC and physical level, IEEE standard specifies also an
optional beam forming protocol that can support a multitude of antenna configurations such as single antenna element, sectored antennas, switched antennas, and onedimensional (1-D) and two-dimensional (2-D) beam forming antenna arrays.
The ECMA 387 standard defines three device types as follows:
• A type A device offers video streaming and WPAN applications in 10 m range
line of sight/not line of sight multipath environments. It uses high gain trainable
antennas. This device type is considered as the ’high end’ - high performance
device.
• A second type, type B device offers video and data applications over shorter range
(1-3 m) point to point line of sight links with non-trainable antennas. It is considered as the ’economy’ device and trades off range and not line of sight performance
in favor of low cost implementation and low power consumption.
• The third type, type C device is positioned to support data only applications over
point to point line of sight links at less than 1 m range with non-trainable antennas
and no QoS guaranties. This type is considered as ’bottom end’ device providing
simpler implementation, lowest cost and lowest power consumption
The A, B, and C devices can interoperate with their own types independently and
can coexist and interoperate with the other types leading to the implementation of
heterogeneous network solution that provides interoperability between all device types.
As depicted in Figure 3.14, each one of the three device types corresponds to a different
organization of the PHY layer. The three PHYs converge into a single MAC level
based on the ECMA-368 standard, with the necessary changes to support directional
communication in 60GHz band.
50
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
Figure 3.14: Protocol Structure of ECMA standard.
The Type A PHY includes two general transmission schemes, namely Single Carrier Block Transmission (SCBT), also known as Single Carrier with Cyclic Prefix, and
OFDM; the Type B PHY has been designed using a simplified single carrier transmission
scheme with a common beaconing mode based on differentially encoded BPSK modulation (DBPSK), thus allowing for both simple coherent and non-coherent demodulation
and minimizing the implementation overhead to support interoperability with type A
devices; the Type C PHY uses the simplest single carrier transmission scheme based on
the Amplitude-Shift-Keying (ASK) modulation scheme.
The standard specifies four frequency channels each with a symbol rate of 1.728 GigaSymbols/second and with a separation of 2.160 GHz, as suggested in Figure 3.15. All
device types follow the same frequency plan.
Figure 3.15: Frequency plan of ECMA standard.
Frequency generation for mm-Wave and satellite applications
51
millimeter Wave PLL
European regulation of WLANs and WPAN system operating in the 60 GHz band is
provided by the European Telecommunications Standards Institute (ETSI). The technical characteristics of these applications are described in [48] and the specific technical
requirements are defined in [49]. The most important features can be summarized as
follows:
• frequency band is defined from 57 GHz to 66 GHz;
• the maximum spectral power density shall be limited to 13 dBm/MHz for indoor
usage and to −2 dBm/MHz for indoor/outdoor;
• the maximum output power level, Effective Isotropic Radiated Power (EIRP), shall
be limited to 40 dBm for indoor usage and to 25 dBm for indoor/outdoor;
• the limit level of unwanted emissions in the spurious domain for transmitter are
reported in Table 3.6 (measured with 0 dBi antenna gain);
• the limit level of unwanted emissions in the spurious domain for receiver are reported in Table 3.7 (measured with 0 dBi antenna gain);
• the use of an integral antenna (that is an antenna designed as a fixed part of the
equipment, without the use of an external connector and that, therefore, cannot
be disconnected from the equipment by a user with the intent to connect another
antenna) is required, to provide interference protection;
• a medium access protocol shall be implemented by the equipment and shall be
active under all circumstances, in order to facilitate spectrum sharing with other
devices in the wireless network [39].
Table 3.6: Transmitter spurious emissions.
Frequency band
Measurement bandwidth
30 MHz to 1 GHz
100 kHz
Field Strenght at 3 m [dBµV/m]
59
1 GHz to 132 GHz
100 MHz
65
Table 3.7: Receiver spurious emissions.
52
Frequency band
Measurement bandwidth
30 MHz to 1 GHz
100 kHz
Field Strenght at 3 m [dBµV/m]
38
1 GHz to 132 GHz
100 MHz
48
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
3.3.2
Millimeter wave automotive radar sensors
The first experimental applications of radar in the automotive industry date back to the
1950s and yet in 1970s automotive radars were the object of systematic investigations
[50, 51].
Years after years, safety has been one of the main concerns in the development of car
industry, leading to several structural improvements capable to reduce the consequences
of accidents on the driver and the passengers. In such a context, the introduction of
radars represents a disruptive event, focusing on accident avoidance and prevention that,
undeniably, are preferred to any system of crash protection.
Nowadays, the so-called autonomous or a Adaptive Cruise Control (ACC) is probably
the most common application of automotive radar and is used to assist the driver and to
augment its comfort. Practically speaking, a radar sensor is mounted behind the front
Figure 3.16: DISTRONIC radar sensor mounted on Mercedes Benz S-class vehicles.
bumper of a vehicle at a height of less than 1 m, where it is able to interrogate the road
ahead and the adjacent traffic lanes forward of the vehicle location (Figure 3.16). Using
this radar, the control system within the vehicle adjusts the cruise speed in response to
a slower vehicle in a merging lane, or when following a vehicle in the same lane, in order
to maintain the driver’s selected minimum separation distance behind the other vehicle
(Figure 3.17). An ACC system can constantly provide the driver with information about
traffic situation in the environment, making driving less strenuous, especially in flowing
traffic and in critical context like on motorways or dual carriageways.
ACC today uses Long-Range Radar (LRR) operating between 76 GHz and 77 GHz with
a maximum bandwidth of 1 GHz. It uses distance scanning, which requires an operating
range of approximately 150 m and is used at vehicle velocities not below 30 km/h. One
or multiple narrow lobes control or scan the driving path in front of the car to determine
the distance to the vehicle driving ahead for maintaining a constant minimum safety
distance.
In 1999 Mercedes-Benz has been the first car manufacturer who introduced radar-based
ACC system in its S-class vehicles [52]. Since then, radar based ACC systems are available in many high and mid-class models such as BMW 7 series, Jaguar (XKR, XK6),
Cadillac (STS, XLR), Audi A8, VW Phaeton, Mercedes E, CL, CLK, SL class, BMW
Frequency generation for mm-Wave and satellite applications
53
millimeter Wave PLL
5 and 6 series, Audi A6, Nissan (Cima, Primera), Toyota (Harrier, Celsior), Lexus (LS,
GS), Honda (Accord, Inspire, Odyssey) and their functionality have been gradually extended, including also pre-crash sensing and collision mitigation.
Besides radar-based equipments, also competing and complementing technologies in vehicular surround sensing and surveillance like Lidar, ultrasonics, and video-cameras have
been tested since the first 1990s to implement parking aid, collision warning, and ACC as
well. However, radar seems still to be the key technology for driver assistance and safety
applications, due to its inherent advantages like weather independence and direct acquisition of range and velocity especially when compared to alternative sensors like video,
laser, and ultrasonics. More recently, in 2003 - whereas European car manufacturers
Figure 3.17: Schematic example of Adaptive Cruise Control (ACC) operation.
offer radar systems only for ACC systems so far, their Japanese competitors Honda and
Toyota introduced an active brake assist for collision mitigation (in addition to ACC)
based on 77 GHz Long-Range Radar (LRR) technology. In contrast to the only smooth
deceleration capability of an ACC system (because ACC is only marketed as a comfort
feature), the active brake assist provides much higher braking forces for deceleration,
when a threatening situation is identified and the driver starts breaking but maybe not
as strong as it would be necessary to avoid a crash. This shows the trend from "comfort
only" functions to active safety systems with radar sensing technologies that serve both
the comfort and the safety domain.
As a matter of fact, car companies and suppliers are currently working on the development of the next generations of LRR at 77 GHz that will show improvements with respect
54
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
to maximum and minimum range, wider field of view, improved range and angular resolution and accuracy, self alignment, and blockage detection capability. In addition to
forward-looking LRR, Ultra-Wideband (UWB) Short Range Radar (SRR) sensors with
coverage up to 30 m are under development for a variety of further applications that will
result in significant improvements of road safety.
Short range radar and Ultra-Wideband sensors can enable a variety of applications such
as:
• Support of ACC with Stop and Go functionality
• Collision warning
• Collision mitigation
• Blind spot monitoring
• Parking aid
• Lane change assistant
• Rear crash collision warning
LRR and SRR devices can be used to combine their functionalities creating a protection
wall all around the vehicle that is referred to in the literature as a "safety belt" for cars
(Figure 3.18).
Figure 3.18: Possible applications for automotive radars.
Beside LRR and SRR systems, a complementary branch of potential applications of
millimeter wave technology to the automotive industry is given by the next-generation
road vehicle communication. Many companies are currently working on the implementation of millimeter wave sensors capable to support inter-vehicle (IVC) (Figure 3.19)
and/or vehicle to roadside and roadside to vehicle (RVC) (Figure 3.20) communication.
Frequency generation for mm-Wave and satellite applications
55
millimeter Wave PLL
Next-generation cars will be able to exchange data - concerning, for example, their relative position or information and warning about weather and traffic status - with the
surrounding vehicles and with beacons placed on the roadside at regular intervals along
all inter-urban trunk routes and at strategic location (e.g. junctions) on more minor
roads and in urban areas.
A huge number of applications of inter-vehicle and roadside to vehicle communication
can be realized and are investigated by various project and groups; some examples are:
• Traffic information
• Collision avoidance
• Work zone safety warning
• Vehicle and cargo tracking
• Electronic license plate
• Repair-service record
• Parking, fuel, or fast food payment
• Disaster and emergency warning and control
More in general, IVC and RVC systems can be considered as part of a wider context,
concerning the so-called Intelligent Transportation Systems (ITS) which represent the
application of information and communications technology to transport infrastructure
and vehicles, in an effort to manage factors that typically are at odds with each other,
such as vehicles, loads, and routes to improve safety and reduce vehicle wear, transportation times, and fuel consumption.
Figure 3.19: An example of IVC.
56
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
Figure 3.20: An example of RVC.
An exhaustive description of all the potential applications of millimeter wave to the
automotive industry is beyond the aim of this thesis. Nevertheless, in conclusion of this
brief overview, it is important to remark that the applications currently available, as the
examples discussed here above, are substantially based on compound-semiconductors
technologies. The considerably elevated cost of these technologies has therefore prevented the large diffusion of automotive radar equipments so far, relegating them to
the high and mid-class market segments. Moreover, in the particular case of intervehicle communication, implementation cost is a concern, as it prevents an adequate
diffusion of inter-communicating devices. Nowadays, thanks to the recent improvements
in silicon-based technologies it is possible to realize low-cost and high-volume production
of systems and circuits for automotive radar operating at millimeter wave frequencies
[39].
3.3.3
Millimeter wave imaging in the 94 GHz band
The upper portion of the millimeter wave spectrum has been traditionally exploited for
applications in the field of astronomy. Recently, further improvements of the related
technology have turned the interest of industry on the development of terrestrial applications based on millimeter wave imaging [53, 54].
As a matter of fact, the property of millimeter wave imaging systems to see through
materials that are opaque to more conventional imaging wavebands (visible, IR and UV)
makes them remarkably useful for many scientific and industrial applications.
In particular, millimeter waves can readily penetrate common clothing materials and
are reflected from the human body and any concealed items. For this reason they can
be efficiently used in the field of security and defense, for the detection of concealed
weapons or explosives. Furthermore, since millimeter wave imaging uses low-power and
not-ionizing radiations, it results to be safer when compared to concurrent technologies
based on X-rays and is better suited for the implementation of body scanner used for
example for airport security screening. In such a context, it is possible to reveal not only
weapons and explosives, but also any object hidden on the body, like drugs and contraband stuff. The personal scanner uses harmless coherent radar waves from a millimeter
wave antenna array to illuminate the person under surveillance. Then the reflected signal
from the body or from any object on the body is collected by the array and processed
to form high-resolution three-dimensional images like that of Figure 3.21.
Frequency generation for mm-Wave and satellite applications
57
millimeter Wave PLL
Figure 3.21: An example of body scanner operation based on millimeter waves.
Following a similar approach it is possible to realize many other applications of
millimeter Wave as ground penetrating radar Ground Penetrating Radar (GPR) imaging, and wall probing systems like inner-wall imaging, through-wall imaging, throughconcrete imaging.
Ground Penetrating Radar (GPR) (Figure 3.22) is a geophysical method that uses radar
pulses to image the subsurface and detects the reflected signals from subsurface structures. GPR can be used in a variety of media, including rock, soil, ice, fresh water,
pavements and structures. It can detect hidden objects, changes in material, and voids
and cracks, without drilling, probing, or digging. The applications of GPR imaging
cover a large number of fields as engineering, where it is used for non-destructive testing
of structures and pavements, for example to map defects such as voids, moisture and
cracking or to determine pavement type and thickness in the context of highway and
airport runway inspection without traffic interruption; archeology, where it is used to
map archeological structures and sites; military, for landmine detection; geophysical, for
ground investigation in order to trace foundations and other obstructions, and to locate
geological hazards that may pose a risk to construction activity or human habitation;
or environmental protection, where GPR can be used to define landfills, contaminant
plumes, and remediation sites.
Also wall probing systems can be useful for non-destructive structural test, to map buried
utility cables, pipes and ducts or to measure the depth to buried utilities, so making
58
Frequency generation for mm-Wave and satellite applications
3.3 Millimeter Wave IC Applications
maintenance interventions simpler, reducing costs and the risk of accidental damage to
power and gas lines.
(a) Surface mapping of an underground storage
(b) Roadway inspection.
tank.
Figure 3.22: GPR apllications.
Many of the applications discussed so far are currently realized using concurrent
technologies (like UWB in the range from 30 MHz to 12.4 GHz in the case of GPR).
Nevertheless, all of them can be potentially supported by millimeter wave systems operating in the frequency range around 94 GHz.
The importance of 94 GHz band is given by the fact that the atmospheric absorption
reaches a minimum level precisely at 94 GHz, as depicted in Figure 3.12. Besides imaging, millimeter wave technology can be applied also to the implementation of a Cloud
Profiling Radar (CPR) employed in satellite missions to investigate cloud structure and
its variability. By using the 94 GHz frequency range it is possible to penetrate ice clouds
with negligible attenuation and obtain a profile of cloud characteristics.
Moreover, the capability of 94 GHz signals to propagate through fog, clouds, rain, and
even sandstorms with irrelevant attenuation can be exploited to design millimeter wave
sensor capable to improve the aviation safety and facilitate airport ground control in
extremely poor visibility [39].
Frequency generation for mm-Wave and satellite applications
59
millimeter Wave PLL
3.4
mmW PLL state of the art
Advances in nanoscale CMOS technology have made it feasible to implement mmW Band
circuits in CMOS for applications such as 60 GHz WPAN, 77 GHz anti-collision systems,
94 GHz imaging systems.
Due to the evolution of wireless communication, the transceivers operating at multigigahertz are required for the high-speed and broadband communications. In order
to satisfy these increasing demands, the unlicensed millimeter band between 59 and
66 GHz is released for those applications. In the high-speed communication system, it
is necessary for the clock generator to generate a very high frequency clock, such as
60 GHz.
In the recent years, several very high frequency clock generators have been realized
in advanced CMOS technologies. However it is still a big challenge to implement the
CMOS Phase-Locked Loop at millimeter Wave frequency while maintaining the sufficient
performance to match the application requirements.
Table 3.8: State of the art of CMOS mmW PLLs close to 60 GHz.
Tech.
Frequency
Divider
Voltage
Power
POU T
L
Area
[nm]
Range [GHz]
Ratio
[V]
[mW]
[dBm]
[dBc/Hz]
[mm2 ]
[55]
130
49.5 to 50.5
1024
1.5
57
-10
[56]
90
61.1 to 63.1
1024
1.2
78
-7
[57]
90
58 to 60.4
256/258
1.2
60
-
[58]
90
74.64 to 75.32
64
1.45
88
-16
[59]*
130
62 to 66.1
128
1.5
89
-
[60]
130
50.8 to 53
256
1.5
87
-
[61]*
90
59.6 to 64
256
1.2
26.3
-
[62]
65
95 to 96.5
256
1.2
47
-
[63]
65
70 to 78
1024-1984
1.0
65
-
[64]
45
57 to 66
512-8184
1.1
76
-
[65]
90
49.68 to 56.16
1840-2080
1.0
60
-
[66]
90
60.2 to 62.4
768
1.5
106.6
-
Ref
−72
@1 MHz
−80
@1 MHz
−85.1
@1 MHz
−88
@1 MHz
−74.5
@1 MHz
−107
@10 MHz
−112
@10 MHz
−75 to −75.86
@1 MHz
−83
@1 MHz
−75
@1 MHz
−80.1
@1 MHz
−93
@10 MHz
1.16x0.75
0.6x0.6
0.95x1
0.8x1
1.33x0.9
0.93x1
0.93x1
1x0.7
0.16
(core)
0.82
1.1
1.1
*VCO Push-Push
60
Frequency generation for mm-Wave and satellite applications
3.4 mmW PLL state of the art
To design such ultra-high-speed PLL implies a robust VCO together with properly
arranged dividers, whose operation locking ranges need to be overlapped with each other.
At such high frequencies, connecting blocks with perfect frequency alignment in a loop
is much more challenging than making blocks individually. It is because any unexpected
parasitic may cause significant frequency shift in the VCO or dividers, prohibiting the
loop from lock.
Table 3.9: Frequency divider topology of CMOS PLL close to 60 GHz.
Ref
Tech.
Locking Range
[nm]
[GHz]
Divider Ratio
[55]
130
49.5 to 50.5
1024
[56]
90
61.1 to 63.1
1024
Divider Topology
÷2 ILLCFD
÷512 CML
÷4 ILROFD
÷16 CML
÷16 CML
÷2 CML
[57]
90
58 to 60.4
256/258
÷4/5 CML
÷32 CML
÷2 ILLCFD
[58]
90
74.64 to 75.32
64
÷4/5 MILLER
÷32 CML
÷32 CML
[59]*
130
62 to 66.1
128
[60]
130
50.8 to 53
256
÷2 ILLCFD
÷8 CML
÷2 CML
÷4/5 CML
÷32 CML
÷2 CML
[61]*
90
59.6 to 64
256
CML
TSPC
DFF
÷2 ILLCFD
÷2 ILFD
[62]
65
95 to 96.86
256
÷2 ILFD
÷4 CML
÷4 TSPC
[63]
65
70 to 78
1024-1984
[64]
45
57 to 66
512-8184
÷2 ILLCFD
CML
÷4 ILLCFD
÷2 CML
÷64to1023 SCL
÷2ILLCFD
[65]
90
49.68 to 56.16
1840-2080
÷8 CML
÷5 DFF
÷(23, 24, 25, 26) DFF
÷3ILLCFD
[66]
90
60.2 to 62.4
1840-2080
÷3 ILROFD
÷128 DFF
*VCO Push-Push
Frequency generation for mm-Wave and satellite applications
61
millimeter Wave PLL
Table 3.8 shows the state of the art of millimeter Wave Phase-Locked Loops in CMOS
technology. The most utilized technology for the mmW PLL is the 90 nm [56, 57, 58,
61, 65, 66] following by the 130 nm in [55, 59, 60]. The literature also reported two PLL
in 65 nm in [62, 63] and one synthetizer in 45 nm in [64]. A fractional PLL has been
presented in [57, 63, 64, 65]. The voltage supply range is from 1.0 V to 1.5 V and the
power consumption ranges from 26.6 mW to 106.6 mW.
The Table 3.9 shows in detail the composition of the division chain of the previously
shows mmW PLLs. Focusing the attention on the first block of the division chain we can
observe that in [55, 56, 58, 59, 62, 63, 64, 65, 66] the prescaler has been realized with an
Injection-Locked (IL) Frequency Divider (FD) topology for the sake of its high frequency
and low power characteristics. In particular [55, 58, 59, 62, 63, 64, 65, 66] utilize a divideby-2 ILLCFD, composed by a LC oscillator working around half of the input frequency.
This kind of FD uses one inductor, therefore occupies large area. For silicon save, a
divide-by-4 inductorless IL Ring Oscillator Frequency Divider (ROFD) is proposed in
[56]; the circuit is composed by a Ring Oscillator working around 15 GHz in free running
condition, and locked at one-fourth of injected RF frequency. In [57, 60, 61] the prescaler
is realized with a CML topology. A latch-type divider is reported in [57, 60], but it also
uses several inductors, and consumes large area. In [61] an inductorless CML topology
is presented, but the prescaler input signal is half than the PLL output frequency.
CML Frequency Divider is wider used in the following divider stage where the input
frequency is lower [55, 56, 57, 59, 60, 61, 63, 64, 65]. Also in the second stage of the
division chain [62, 66] utilize an IL topology, respectivelly ILROFD in [66] and ILLCFD
in [62]. Finally a dual modulus divide-by-4/5 Miller divider is proposed in [60].
For the rest of the division chain, that works at low frequency, a D-Flip-Flop (DFF)
FD and CML FD are widely used.
A negative resistance LC-tank (LC) Voltage Controlled Oscillator (VCO) is employed
in [55, 56, 57, 58, 59, 62, 63, 64, 65, 66] for it high spectral purity and because its requires
a minimal number of passive components, and thus low silicon area. A differential
Colpitts oscillator topology has been adopted in [60, 61]. All cited VCOs work at the
PLL output frequency except in [59, 61] where mmW output frequency is generated by
VCO Push-Push topology.
62
Frequency generation for mm-Wave and satellite applications
3.5 Frequency planning
3.5
Frequency planning
In the present thesis, effort have been done on the design of a part of a millimeter
Wave Phase-Locked Loop in CMOS 65 nm technology for Wireless Personal Area Networks. The following section shows the design of the circuits and how they works at
high frequency:
1. 60 GHz Voltage Controlled Oscillator in the section 3.6
2. first stage of the division chain at 60 GHz (prescaler) in the section 3.7
3. second stage of the division chain at 30 GHz in the section 3.8
Table 3.10 reports the specifications of each block and the chosen topology. In particular the VCO should work from 57 GHz to 63 GHz to satisfied to the WPAN standard.
The prescaler input frequency goes from 55 GHz to 65 GHz, with a minimum frequency
margin between the output VCO frequency and prescaler (Injection-Locked LC-tank
Frequency Divider) operation frequency in order to compensate eventual frequency shift.
Same consideration hold for the prescaler and the second stage of the division chain
(Injection-Locked Ring Oscillator Frequency Divider). In the present thesis a voltage
supply of 1.2 V has been selected.
Table 3.10: Frequency planning.
block
VCO
1 stage
2 stage
Topology
LC VCO
LC-tank Voltage Controlled Oscillator
ILLCFD
Injection-Locked LC-tank Frequency Divider
ILROFD
Injection-Locked Ring Oscillator Frequency Divider
Operation Frequency
57 GHz to 63 GHz
55 GHz to 65 GHz
25 GHz to 35 GHz
Frequency generation for mm-Wave and satellite applications
63
millimeter Wave PLL
3.6
60 GHz Voltage Controlled Oscillator
This section will present the VCO design that will be utilized in the 60 GHz proposed
synthesizer. Among the LC-VCO topologies, the negative gm topology is chosen for this
design due to its simple structure and easily available differential outputs [55, 56, 57,
58, 59, 62, 63, 64, 65, 66]. The losses of the resonator in this topology are compensated
by placing transistors in positive feedback (cross-coupled) which generates the required
negative resistance to initiate oscillation.
3.6.1
Inversion mode MOS varactor
Figure 3.23 shows the cross section of an inversion mode N-MOS (I-MOS) variable capacitor. A Metal-Oxide-Semiconductor structure is opened on the P substrate, with two N+
Figure 3.23: Cross section of I-MOS varactor.
diffusion providing the minority carriers when the surface layer is inverted. The contacts
(D/S) to the N+ diffusion are connected together and the capacitor is controlled by the
voltage applied between the Gate and Drain/Source (VCT RL ) terminals.
An I-MOS VCO, employing N-MOS cross coupled pairs, allows a full exploitation of
the C-V varactors characteristic keeping both the control terminals within the voltage
range allowed by the technology.
The operation of the I-MOS varactor is as follows. Let us assume the gate voltage is
the maximum available voltage, i.e. the supply voltage VDD , and the bulk is connected
to ground. When VCT RL is equal to VDD the channel is strongly inverted and the capacitance is mainly the oxide capacitance Cox · W · L. The capacitance seen from the gate
is hence given by the series of the gate oxide and the depletion oxide capacitances, the
latter being smaller than the former. Note that, because the gate-bulk voltage is always
positive, this configuration does not allow the device to operate in accumulation mode,
resulting in a strictly monotonic C-V characteristic.
64
Frequency generation for mm-Wave and satellite applications
3.6 60 GHz Voltage Controlled Oscillator
However, this simple model does not take into account the overlap capacitance that,
in modern CMOS technologies, is not a negligible fraction of the oxide capacitance. For
minimum length device, the overlap capacitance is greater that the depletion one and
represents the minimum varactor capacitance.
The main limit of the tank quality factor (QT ) at mmW frequencies is the varactor
quality factor QC . For this reason, maximizing QC is very important. The Gate resistance is proportional to the channel length L, the quality factor increases as L1 , therefore
the quality factor is maximum with the minimum length device. Usually the device is
made up of several wide finger in parallel, in order to reduce the gate resistance. On the
other hand, the fixed parasitic capacitance takes more relevance by reducing the finger
width, thus reducing the achievable tuning range. WF = 1 µm has been chosen as a
trade-off between varactor quality factor and tuning range [67].
max
Figure 3.24 shows the QC and C
Cmin ratio of a varactor of WT OT = 15 µm simulated
for several gate lengths at 60 GHz. The minimum QC largely decreases with increasing
the gate length, while the tuning ratio increases. It is worth noticing that, in order to
achieve a high QC at 60 GHz, a minimum length is mandatory. Figure 3.25 shows the
simulated C-V and Q-V characteristics, for a varactor structure with 15 finger of 1 µm
width and minimum length.
13
10
12
9
11
Quality Factor
8
9
7
8
/C
max
min
6
6
max
/C
min
C
7
5
C
Minimum quality factot
10
5
4
4
3
3
2
2
1
1
0
0,0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
Length [um]
Figure 3.24: Varactor minimum quality factor and
Cmax
Cmic
versus transistor length
Frequency generation for mm-Wave and satellite applications
65
millimeter Wave PLL
22
21,0
20,5
21
20,0
20
19,5
19,0
19
18
18,0
Capacitance
Quality Factor
17,5
17
17,0
16
16,5
16,0
15
Quality Factor
Capacitance [fF]
18,5
15,5
14
15,0
14,5
13
14,0
12
13,5
13,0
11
0,0
0,2
0,4
0,6
0,8
V
TUNE
1,0
1,2
1,4
1,6
1,8
[V]
Figure 3.25: Varactor quality factor and capacitance versus VT U N E .
3.6.2
Circuit design
Figure 3.26 shows the N-MOS cross-coupled pair VCO topology [68]. In order to maximize the frequency tuning range, tank capacitance should be maximized. As a consequence a small inductance would penalize the oscillation amplitude for a given bias
current. To achieve a differential voltage amplitude of 700 mV the bias current must be
set to 9 mA. Consequently, the following aspect ratio of the transistors M2,3 has been
chosen.
12 µm
W
=
(3.32)
L 2,3
65 nm 2,3
The transistors have been laid out with minimum length, with a WF = 1 µm and double
gate access, in order to find the best trade-off between the gate resistance and the fixed
capacitance.
The varactor is composed with a parallel of ten I-MOS with a WT OT = 15 µm and
WF = 1 µm. The varactor was laid out in two sections: analog and digital. The analog
section, controlled by a control voltage from 0 V to 1.8 V, is composed by a parallel
of three I-MOS for reducing the parasitic series gate resistance in order to improve the
varactor quality factor QC . The digital section, controlled by three bits line, is composed
by seven I-MOS connected in parallel. The combination of analog and digital tuning
varactors splits the frequency range of the VCO in several sub-bands. Each sub-band is
activated by a circuit show in Figure 3.26; when the voltage on BIT terminals is equal to
VDD the circuit connect the drain/source terminals of the selected varactors to ground.
Viceversa when the voltage on BIT terminals is equal to ground the the circuit connects
66
Frequency generation for mm-Wave and satellite applications
3.6 60 GHz Voltage Controlled Oscillator
the drain/source terminals of the selected varactors to VDD . This approach allows a lower
VCO gain in each sub-band, with benefits to supply noise rejection and minimization of
AM to PM conversion, as a consequence. The required frequency tuning range is close
VDD
VDD
Bit
L
7xDigital
VT U N E
T ank−
C
C
M3
T ank+
T ank−
M2
T ank+
Bit
Analog
M1
Vbias
Ibias
T ank−
VT U N E
T ank+
Figure 3.26: VCO schematic.
to 10 % with a central frequency of 60 GHz; the frequency range spans therefore from
57 GHz to 63 GHz. The fixed tank capacitance due to inductor, cross-coupled pairs and
buffer parasitic plus maximum varactor capacitance is 150 fF; this value loads to 51 pH
inductance for a 57 GHz oscillation frequency.
Figure 3.27 shows the designed inductor geometry. The inductor has been designed
only in metal 7 and without shield. As in the other parts of the chip uses a ground
plane, this one has been laid out in metal 1 and metal 2 only at 11 µm of distance
from the inductor in order to reduce the coupling between the inductor and the ground
plane. Figure 3.28 shows the inductance and its quality factor simulated with the HFSS
Figure 3.27: Inductor geometry.
electromagnetic simulator. Near 60 GHz the inductance value is close to 50 pH and the
quality factor is close to 17.
Frequency generation for mm-Wave and satellite applications
67
millimeter Wave PLL
300
20
250
18
200
16
150
12
50
10
0
8
Quality Factor
-50
Quality Factor
Inductance [pH]
14
100
6
Inductance
-100
4
-150
2
-200
0
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
Frequency [GHz]
Figure 3.28: Inductance and quality factor versus frequency.
A differential lumped equivalent 2π model (seen in Figure 3.29) has been extracted,
in order to integrate the inductor into spectre simulations.
Cp
Rpp
Lp
Rp
Lp
CenterT ap
Ls
Ls
Rs
Out−
Cox
Csub
Rp
Rs
Cox
Rsub
Csub
Out+
Cox
Rsub
Csub
Rsub
Figure 3.29: 2π differential lumped model.
The total tank quality factor which is equal to the inductor quality factor in parallel
with the minimum varactor quality factor (Eq: 2.9) gives a value close to 7 for the total
tank quality factor.
The circuit of the VCO has been laid out very compact and carefully in order to minimize the connection lengths between the devices. In this way the HFSS electromagnetic
simulations of parasitic inductances were not necessary. The parasitic capacitances were
extracted with STAR-RCXT.
68
Frequency generation for mm-Wave and satellite applications
3.6 60 GHz Voltage Controlled Oscillator
3.6.3
Layout
Figure 3.30a shows the layout of the designed VCO. The varactors are placed inside the
inductor accesses and very close to the cross coupled pair. Also the buffers are laid out
near the inductor accesses in order to minimize the metal interconnections. Figure 3.30b
shows in detail the varactors structure described in the previous section 3.6.2. We can
observe the analog tuning composed by three I-MOS and the digital tuning composed
by seven I-MOS.
(a) VCO Layout.
(b) Varactors layout.
Figure 3.30: VCO layout.
Frequency generation for mm-Wave and satellite applications
69
millimeter Wave PLL
3.6.4
Measurements results
Figure 3.31a shows the photomicrograph of the prototype implemented in the 65 nm
CMOS technology from STMicroelectronics. The circuit was integrated with differential
buffers loaded with the same tank VCO. One output has been connected to a singleended GSG pad for the measurements and the other was connected to a 50 Ω resistance
for sake of load symmetry. The chip size is 910 · 850 µm2 including pads and the core of
the circuit Figure 3.31b is 150 · 80 µm2 .
(a) microphotograph.
(b) core.
Figure 3.31: VCO microphotograph.
Figure 3.32 shows the measured and simulated circuit tuning range. The measured
carrier frequency (f0 ) goes from 71.87 GHz to 81.44 GHz for VT U N E ranging between 0 V
and 1.8 V corresponding to a tuning range of 12.4 %.
The STAR-RCXT extracted simulation carrier frequency (f0 ) goes from 56.85 GHz
to 63.72 GHz corresponding to a tuning range of 11.4 %. As stated above, the VCO was
designed using the STAR-RCXT tool for the extraction of the parasitic capacitances.
Figure 3.32 shows that the STAR-RCXT extraction simulated carrier frequency is as
required by the spec’s.
The comparison with the measurements demonstrates that the STAR-RCXT simulations provide an overestimation of the parasitic capacitances; the real parasitic capacitances in the fabricated prototype are lower then forecasted by STAR-RCXT, resulting,
therefore, in a higher center frequency and a wider tuning range. In order to depth
investigate this issue, a further parasitic capacitances extraction has been carried out
using the PEX tool of Calibre. Figure 3.32 shows that for PEX extracted simulations
the carrier frequency (f0 ) goes from 63.30 GHz to 71.5 GHz corresponding to a tuning
range of 12.3 %. The Calibre forecast is closer to the experimental results, giving further
evidence of the fact that STAR-RCXT suffers from an overestimation of the parasitic
70
Frequency generation for mm-Wave and satellite applications
3.6 60 GHz Voltage Controlled Oscillator
capacitances.
Nevertheless, even Calibre is not able to reproduce the measured center frequency
and tuning range. The sketched general frame suggests that electromagnetic simulations
are needed for a more accurate estimation of the parasitic capacitances.
82
80
78
76
74
Frequency [GHz]
72
70
68
66
64
62
60
58
56
Measurements
54
Calibre Simulations
STAR-RCXT Simulations
52
50
0,0
0,2
0,4
0,6
0,8
V
TUNE
1,0
1,2
1,4
1,6
1,8
[V]
Figure 3.32: VCO voltage tuning range.
The circuit core power consumption is 15.6 mW for a voltage supply of 1.2 V. The
measured sinked current of 13 mA is higher than the simulated one of 9 mA. This
increase is due to the fact that the fabricated oscillator works at a higher frequency than
the simulated one. Figure 3.33 shows the measured phase noise for f0 =71.8 GHz. The
VCO exhibits a phase noise of −116 dBc/Hz at the offset frequency (∆f) of 10 MHz. The
FOM is −181.2 dBc/Hz and FOMT is −183.1 dBc/Hz at the same offset frequency.
Figure 3.34 shows the measured output spectrum with a 500 MHz span.
Frequency generation for mm-Wave and satellite applications
71
millimeter Wave PLL
Figure 3.33: VCO phase noise.
Figure 3.34: VCO output spectrum.
72
Frequency generation for mm-Wave and satellite applications
3.6 60 GHz Voltage Controlled Oscillator
Table 3.11 compares the designed VCO with the state of the art of VCO designed
at mmW frequency. In conclusion a 65 nm CMOS VCO exhibiting a central frequency
Table 3.11: State of the art of CMOS mmW Voltage Controlled Oscillators.
Ref.
Pub.
[69]
ISSCC2006
[70]
[68]
[71]
[72]
Tech.
f0
TR
Voltage
PDIS
L
FOM
FOMT
[nm]
[GHz]
[%]
[V]
[mW]
[dBc/Hz]
[dBc/Hz]
[dBc/Hz]
130
59
5.8
1.5
9.8
-89 @1 MHz
−174.5
−169.8
JSSC2006
90
60
0.2
1.0
1.9
-100 @1 MHz
−192.8
−158.8
RFIC2008
65
54
11.4
RFIC2008
MWCL2008
130
130
1.2
7.2
-118 @10 MHz
−184.1
−185.2
62.1
9.9
1
3.9
-91 @1 MHz
−180.5
−180.7
59.1
10.3
1
3.9
-95 @1 MHz
−185.0
−184.9
69.8
4.5
0.6
4.3
-98.8 @1 MHz
−189.3
−182.5
69.8
4.5
0.6
4.3
-115.5 @1 MHz
−186.0
−179.2
-95.3 @1 MHz
−174.9
−174.3
-95 @1 MHz
−186.1
−184.9
15
-99 @1 MHz
−182.2
−186.8
[73]
EuMIC 2009
65
60.29
9.3
1.2
[74]
TMTT2011
90
64
9.9
0.6
[75]
TMTT2011
65
56
16.9
1.2
SiRF2011
90
58.4
WORK
65
77
[76]
THIS
36
3.2
4.3
1.2
55
-106.2 @1 MHz
−184.1
−176.7
12.4
1.2
15.6
-116 @10 MHz
−181.3
−183.1
of 77 GHz has been designed. The phase-noise-related FOM is well aligned with other
CMOS bulk VCOs reported in the literature, in particular for mmW applications.
Unfortunately the VCO was designed to work around 60 GHz for WPAN standard.
The circuit exhibits a good performance for the automotive radar standard. The redesign
of inductor is needed to restore the central frequency at 60 GHz.
Frequency generation for mm-Wave and satellite applications
73
millimeter Wave PLL
3.7
Divided by 2 LC prescaler
For very high frequency applications the Injection Locking Frequency Divider (ILFD) is
a widely used solution [55, 56, 58, 59, 62, 63, 64, 65, 66]. To accommodate the severe
tradeoffs between the input frequency and the operation range, different types of dividers
can be employed. Generally speaking, the ILFD achieves the highest operation frequency
due to the simplest structure, but with the narrowest locking range.
3.7.1
Circuit Design
The first stage is realized as a simple LC-tank structure, where the biasing is established
by a current mirror and the cross-coupled pair gives a negative resistance to compensate
the tank losses (Figure 3.35). In this case, the input signal is directly applied to the gate
of the NMOS current mirror transistor.
VDD
Vout−
Vout+
L
R
R
VT U N E
C
C
M3
M2
M1
RFIN
IDC
Figure 3.35: Injection-Locked Frequency Divider schematic.
The LC-tank works at half frequency of the signal input. For this FD topology, the
locking range is set to (Eq:3.33)[77]:
LR ≈
2f0 IIN J
3QT IDC
(3.33)
where f0 is the center frequency, QT is the total tank quality factor, IDC is the DC
current, and IIN J is the injection current. We can observe that the locking range is
directly proportional to the injection current. For this reason, an optimum matching
between VCO and ILLCFD is needed to maximize the current injection. Furthermore
the amplitude of the output voltage oscillation is directly proportional to the tank quality
factor. In the locking bandwidth, the oscillation amplitude is given by (Eq:3.34)[77]:
74
Frequency generation for mm-Wave and satellite applications
3.7 Divided by 2 LC prescaler
IIN J
4
cos (2φ)
(3.34)
Vout = Zout IDC 1 +
π
3IDC
where Zout = 2πf0 QT L and φ is the phase shift between the input and the output
signals. The tank quality factor has been reduced from 12 to 2 (Figure 3.36) with two
identical series resistors [78], connected between the tank and the cross-coupled pair, in
order to improve the locking range.
55,0
52,5
Q=2
50,0
Q=12
Amp [dB]
47,5
45,0
42,5
40,0
37,5
35,0
32,5
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Frequency [GHz]
Figure 3.36: Tank quality factor for VT U N E 0 V.
A trade-off exists therefore between the locking range and the output voltage signal
amplitude. A careful layout has been done, in order to reduce as much as possible the
capacitive parasitics. As a consequence the inductance value is large enough to generate
the needed amplitude voltage to drive the second stage of the division chain without
buffering. The required output voltage set the DC current to 3 mA. The aspect ratio of
the transistors M2 and M3 is chosen to provide a small signal loop gain higher or equal
to one and half (Eq:3.35), to fullfill the self oscillation start-up condition:
gm2,3
1
=
≥ 1.5
(3.35)
|gmc | =
2
Rpeq
where gmc is the small signal differential transconductance of the circuit, gm2,3 is the
transconducance of the transistor M2,3 and Rpeq is the total differential resistance across
the LC tank. To minimize the capacitance associated to the transistors and to achieve
the highest transconductance, the minimum gate length is required. The transistor ratio
is therefore set to:
30 µm
W
=
(3.36)
L 2,3
65 nm 2,3
Frequency generation for mm-Wave and satellite applications
75
millimeter Wave PLL
The tail transistor M1 has been designed, even in this case, with the minimum length
for the maximum transconductance. The width has been chosen, in order to find an
optimum value of input impedance and a higher injection efficiency. The biasing voltage
is VGS = 0.3 V ≈ VT H .
W
50 µm
=
(3.37)
L 1
65 nm 1
The RF MOS transistor must be designed with short fingers to be functional at millimeter wave frequencies. Indeed, the gate serial resistance is responsible for the degradation
of fmax . Our transistor exhibits a finger width (WF ) ranging from 1 µm to 2 µm to
keep high performances at 60 GHz and to have a trade-off between the transistors performances and a compact layout, in order to reduce as much as possible the connections
between the current mirror and the differential cross-coupled pair. In addition, the increase of the gate resistance of the cross-coupled differential pair helps to decrease the
total tank quality factor (Eq: 3.33).
During the design, Process-Voltage-Temperature (PVT) variations have also been
taken into account as follows: a ±10% variation of the supply voltage VDD = 1.2 V and
an operating temperature range between −40 ◦C and 125 ◦C. To compensate for the
frequency shift, a varactor was added in parallel to tune the FD free running frequency.
The layout of the tank connections have been made in top metal with a minimum width
in accordance with the maximum current allowed in the Design Rules Manual (DRM).
For this reason, the tank connections are very tiny and consequently very inductive and
(a) Layout.
(b) Microphotograph.
Figure 3.37: Injection-Locked LC-tank Frequency Divider tank.
resistive. The parasitic capacitances have been extracted with Star-RCXT. This tool
is not able to extract the parasitic inductances and the extracted resistances are not
accurate. Therefore, 3D electromagnetic simulations have been carried out with the
Ansoft HFSS electromagnetic simulator, in order to precisely control the tank resonance
frequency and quality factor. Each connection brings 5 pH and 2 Ω of parasitic inductance and resistance at the circuit output node. This value of resistance includes the
76
Frequency generation for mm-Wave and satellite applications
3.7 Divided by 2 LC prescaler
transistor accesses, the metal lines, and the resistance accesses. To achieve a total tank
quality factor of two the value of the resistance must be equal to 10 Ω. Therefore the
chosen value is set to 8 Ω. Even if the tank circuit does not work at mmW frequency, the
contribution of the parasitic inductances is not negligible. Figure 3.38 shows the impact
of the tank parasitic inductances in the FD free running frequency. For sake of mea39,5
39,0
38,5
Simulations Star-RCXT
Simulations Star-RCXT+HFSS
38,0
Frequency [GHz]
Measurements
37,5
37,0
36,5
36,0
35,5
35,0
34,5
34,0
33,5
0,0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
V
0,9
TUNE
1,0
1,1
1,2
1,3
1,4
1,5
1,6
1,7
1,8
[V]
Figure 3.38: Injection-Locked LC-tank Frequency Divider free running frequency.
surements, the test chip has been designed to operate around 70 GHz; as a consequence,
the free running frequency of the FD is close to 36 GHz. The total fixed capacitance for
inductor, cross-coupled pair and buffer plus the minimum varactor capacitance is 90 fF.
In order to set the center frequency around 36 GHz, a 230 pH octagonal one turn coil
differential inductance has been selected. The inductance value keeps into account the
parasitic inductances extracted through electromagnetic simulations.
3.7.2
Measurement Results
Figure 3.39 shows the photomicrograph of the prototype implemented in the 65 nm
CMOS technology from STMicroelectronics. The circuit was integrated with two common drain buffers. One output has been connected to single-ended GSG pad for the
measurements and the other is connected to a 50 Ω resistance for sake of load symmetry. The chip size is 650 · 700 µm2 including pads. The ILLCFD consumes 3.6 mW
from a 1.2 V supply, excluding buffers. Figure 3.38 shows the simulated and the measured free running frequency of the circuit with a control voltage ranging between 0 V
Frequency generation for mm-Wave and satellite applications
77
millimeter Wave PLL
Figure 3.39: Injection-Locked LC-tank Frequency Divider Photomicrograph.
and 1.8 V. The Star-RCXT postlayout simulated free running frequency goes from
35.72 GHz to 39.03 GHz, the Star-RCXT+HFSS postlayout simulated free running frequency goes from 34.50 GHz to 38.16 GHz, and the measured free running frequency goes
from 34.11 GHz to 38.11 GHz. The maximum frequency difference between Star-RCXT
simulations and measurements is equal to 1.61 GHz for a control voltage of 0 V with
a relative error of 4.51 %. The introduction of the electromagnetic simulation carried
out by HFSS reduces the maximum frequency variation from 1.61 GHz to 0.39 GHz and
the maximum relative error from 4.51 % to 1.14 % and provides a very good agreement
between simulations and measurements.
Table 3.12: LC Frequency Divider free running frequency.
fmin
fmax
∆fmax
ǫ
[GHz]
[GHz]
[GHz]
[%]
Star-RCXT
35.72
39.03
1.61
4.51
Star-RCXT+HFSS
34.50
38.16
0.39
1.14
Measurements
34.11
38.11
-
-
Table 3.13 summarized the measured and simulated locking range (Eq:3.38, Eq:3.39)
78
Frequency generation for mm-Wave and satellite applications
3.7 Divided by 2 LC prescaler
for a control voltage of 0 V, 1 V, 1.2 V, 1.5 V and 1.8 V.
LR[GHz] = fmax − fmin
LR[%] = 2 ·
(3.38)
fmax − fmin
· 100
fmax + fmin
(3.39)
With 0 dBm input power and VDD =1.2 V, the proposed ILLCFD Locking Range, in
the best case, is 10.5 GHz (65.3 GHz to 75.8 GHz) or 14.88 % of the center frequency.
The total measured Locking Range of the circuit is 15.7 GHz (63.5 GHz to 79.2 GHz) or
22.00 % of the center frequency. Even in this case, we can observe a very good agreement
between simulations and measurements.
Table 3.13: LC Frequency Divider Locking Range
(b) Measurements.
(a) Simulations.
VT UN E
fmin
fmax
LR
LR
VT UN E
fmin
fmax
LR
LR
[V]
[GHz]
[GHz]
[GHz]
[%]
[V]
[GHz]
[GHz]
[GHz]
[%]
0
63.2
73.0
9.8
14.39
0
63.5
72.3
8.8
12.96
1.0
64.0
74.5
10.5
15.16
1.0
64.5
74.0
9.5
13.72
1.2
65.3
76
10.7
15.15
1.2
65.3
75.8
10.5
14.88
1.5
67.5
77.7
10.2
14.05
1.5
68.5
78.4
9.9
13.48
1.8
68.9
78.5
9.6
13.03
1.8
69.2
79.2
10.0
13.48
TOT
63.2
78.5
15.3
21.59
TOT
63.5
79.2
15.7
22.00
Figure 3.40 shows the input sensitivity of the Frequency Divider for several values of
control voltage.
Frequency generation for mm-Wave and satellite applications
79
millimeter Wave PLL
2
0
-2
-4
-6
Input Power [dBm]
-8
-10
-12
-14
-16
-18
-20
V
= 0 V
-24
V
= 1.0 V
-26
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
-22
TUNE
TUNE
TUNE
-28
TUNE
-30
-32
TUNE
-34
62
64
66
68
70
72
74
76
78
80
82
84
Frequency [GHz]
Figure 3.40: Injection-Locked LC-tank Frequency Divider sensibility.
(a) Phase Noise.
(b) Output spectrum.
Figure 3.41: LC Frequency Divider measurements.
Figure 3.41a shows the Frequency Divider phase noise measurement compared with
the phase noise of input signal source. The phase noise of the Frequency Divider is 6 dB
lower than the phase noise of the source, suggesting that the circuit does not contribute
significantly to the total phase noise. The Figure 3.41b shows the output spectrum in
free running mode close 34 GHz and the output signal at 34.5 GHz with an input signal
80
Frequency generation for mm-Wave and satellite applications
3.7 Divided by 2 LC prescaler
of 0 dBm at 69 GHz.
A comparison with the state of art Injection-Locked LC-tank Frequency Divider has
been reported in the following Table 3.14 using the following Figure Of Merit:
F OM =
LR[GHz]
PDIS
(3.40)
Table 3.14: State of the art of CMOS mmW Injection Locking Frequency Dividers.
Tech.
LRf
LR
Input Power
Voltage
Power
FOM
[nm]
[GHz]
[%]
[dBm]
[V]
[mW]
[GHz/mW]
[79]
90
85.2 to 96.2
12.13
0
1.2
3.5
[79]
90
99 to 105
5.88
0
1.2
[80]
65
81.5 to 85.9
5.1
0
1.55
[81]
65
93.5 to 109.1
15.3
0
1.1
[82]
65
48.5 to 62.9
25.9
0
[83]
65
82 to 94
13.6
0
[84]
65
104 to 112.8
[85]
65
128.24 to 137
6.6
[86]
65
132.7 to 142.5
[87]
130
[88]
90
[89]
65
[90]
[91]
THIS WORK
Ref.
3.3
12
3.14
1.82
0.36
5.5
2.84
1.2
1.65
8.72
0.56
3.92
3.06
< −5
1.2
7.2
1.22
0
1.1
5.5
1.59
6.6
< −4
1.1
5.28
1.85
66.4 to 76
13.6
4
1
4
2.4
51 to 74
36.8
0
0.5
3
7.6
158 to 195
20.96
0
1
2.5
130
59.6 to 67
11.69
0
0.8
1.6
4.63
90
52.7 to 64.8
20.60
0
1.2
8.6
1.41
65
63.5 to 79.2
22.00
0
1.2
3.6
4.36
8.14
14.8
The circuit is well aligned with other CMOS bulk Injection-Locked LC-tank Frequency Divider reported in the literature. In particular for the PLL the inductor resizing
is needed to restore the central frequency to 60 GHz.
Frequency generation for mm-Wave and satellite applications
81
millimeter Wave PLL
3.8
Divided-by-2 Injection-Locked Ring Oscillator Frequency
Divider
For the second stage of the division chain we select a divide-by-2 inductor-less InjectionLocked Ring Oscillator Frequency Divider (ILROFD). Figure 3.42 shows the circuit
block diagram of the circuit. The ILROFD is composed of four-stage series connected
with resistive load, which is another candidate to avoid inductors or active load; because
in our process, the parasitic capacitance of the PMOS is larger than the resistances
parasitic capacitances. For a ring oscillator, large parasitic capacitances cause high
current consumption to oscillate at the same oscillation frequency. So we select resistive
load in this design.
To guarantee the same impedance at the output of each amplifier stage another
amplifier stage was connected as output buffer.
Vbias
+
−
+
−
+
−
+
−
+
−
−
+
−
+
−
+
−
+
−
+
RF+
RF−
Figure 3.42: IL Ring Oscillator Frequency Divider block diagram.
VDD
VDD
RD
RD
Out+
In+
Vbias
RFIN
RD
Out−
M3
Rbias
M2
Out+
In−
In+
M1
Ibias
(a) Differential pair with injection signal.
RD
Vbias
Out−
M3
Rbias
M2
M1
Ibias
(b) Differential pair and output buffer.
Figure 3.43: Differential amplifier schematics.
82
In−
Frequency generation for mm-Wave and satellite applications
3.8 Divided-by-2 Injection-Locked Ring Oscillator Frequency Divider
3.8.1
Circuit design
The closed loop transfer function of Ring Oscillator show in the Figure 3.42 is:
Vout
H(s)
(s) =
Vin
1 + H(s)
The transfer function of each stage is given by: −
H(s) = 1+
A0 4
1+
s
ω0
(3.41)
A0 , we have for the loop gain:
s
ω0
(3.42)
4
The circuit oscillates only if the frequency-dependent phase shift equal to 180◦ therefore
each stage contributes 45◦ . The frequency at which this occurs is given by
ωosc
arctan
ω0
= 45◦
(3.43)
and hence:
ωosc = ω0
(3.44)
The minimum voltage gain per stage must be such that the magnitude of the loop gain
at ωosc is equal to unity:
A0
r
(3.45)
2 = 1
ωosc
1 + ω0
√
(3.46)
A0 = 2
The voltage gain for the schematic show in Figure 3.43b at the first order is given by:
A0 ≈ gm2,3 RD
s
gm2,3 ≈
(3.47)
W2,3
Ibias
L2,3
(3.48)
W2,3
Ibias RD
L2,3
(3.49)
2µn Cox
Combining Eq 3.47 and Eq 3.48 we obtain:
A0 ≈
s
2µn Cox
For a given technology µn , Cox are fixed. Eq 3.46 shows that needed gain for the
oscillation start-up (Eq 3.48), at the first order, only depends of RD , W2,3 , L2,3 and Ibias
.
RD = 600 Ω
(3.50)
W
L
2,3
=
10 µm
65 nm
(3.51)
2,3
Frequency generation for mm-Wave and satellite applications
83
millimeter Wave PLL
Ibias ≈ 670 µA
(3.52)
Eq 3.50, Eq 3.51 and Eq 3.52 show the chosen resistor load, transistors size and bias
current in order to fix the frequency of the designed RO (Figure 3.42) around 15 GHz and
to have a best trade-off between output node capacitance and current consumption. To
keep high performance with minimum current consumption, and to reduce the transistor
capacitance minimum length is required for the differential couple transistors. The bias
voltage is directly connected to gate of the transistor M1 .
W
L
=
1
4 µm
65 nm
(3.53)
1
The differential output signal given by the ILLCFD is directly injected on the gate of
transistor M1 of the odd stage amplifier (Figure 3.43a). Even in this case for high
injection efficiency a minimum transistors length is mandatory.
The double injection increases the divider Locking Range [92] and provides the same
charge at the prescaler output.
3.8.2
Post layout simulations
Figure 3.44 shows the post layout simulations of total current consumption and oscillation frequency versus the bias voltage. The oscillation starts for a voltage bias of 0.4 V
with a current consumption of 2.7 mA with a voltage supply of 1.2 V at 12.4 GHz.
The frequency of this voltage controlled ring oscillator goes form 12.4 GHz to 17.1 GHz
for a voltage bias ranging from 0.4 V to 1.1 V and a current consumption from 2.7 mA
to 8.4 mA.
18,0
9
17,5
8
Current consumption
17,0
7
16,5
Current [mA]
15,5
5
15,0
4
14,5
14,0
3
Frequency [GHz]
16,0
6
13,5
2
13,0
Frequency
1
12,5
12,0
0
-0,1
0,0
0,1
0,2
0,3
0,4
0,5
0,6
V
bias
0,7
0,8
0,9
1,0
1,1
1,2
1,3
[V]
Figure 3.44: Frequency and current consumption versus bias voltage.
84
Frequency generation for mm-Wave and satellite applications
3.8 Divided-by-2 Injection-Locked Ring Oscillator Frequency Divider
Table 3.15: Ring Oscillator Frequency Divider Locking Range
Vbias
f0
fmin
fmax
LR
LR
IT OT
[V]
[GHz]
[GHz]
[GHz]
[GHz]
[%]
[mA]
0.4
12.4
17.7
33.0
15.3
60.4
2.68
0.5
13.7
18.3
38.0
19.7
69.8
3.95
0.6
14.9
21.3
39.1
17.7
58.7
5.24
0.7
15.7
24.5
38.6
14.1
44.7
6.39
0.8
16.3
27.6
37.9
10.3
31.5
7.26
0.9
16.9
30.4
37.2
6.8
20.1
7.83
1.0
16.9
32.4
36.6
4.2
11.9
8.36
1.1
12.4
32.2
34.2
2.0
5.1
8.48
80
20
70
18
16
14
50
12
40
10
30
8
20
6
Locking Range [GHz]
Locking Range [%]
60
Loking range [%]
4
10
Locking range [GHz]
2
0
0
0,3
0,4
0,5
0,6
0,7
0,8
V
bias
0,9
1,0
1,1
1,2
1,3
[V]
Figure 3.45: Locking range versus bias voltage.
Frequency generation for mm-Wave and satellite applications
85
millimeter Wave PLL
Figure 3.45 shows the locking range versus the bias voltage with a differential input
signal of 300 mV . The optimum bias value is 0.5 V with a total power consumption of
4.8 mW. Table 3.15 shows the summary of the locking range for each value of bias voltage.
Figure 3.46 shows the photomicrograph of the prototype implemented in the 65 nm
CMOS technology from STMicroelectronics. The chip size is 620 · 950 µm2 including
pads. The effective core chip area is 25 · 35 µm2 .
(a) Chip microphotograph.
(b) Core Microphotograph.
Figure 3.46: Injection-Locked Ring Oscillator Frequency Divider microphotograph.
The post layout simulations are in good agreement with the pecifications reported
in the section 3.8.
86
Frequency generation for mm-Wave and satellite applications
4
Conclusions
This last part summarizes the results presented in the Ph.D. thesis. The main topics
have been handled. In particular the frequency generation at 15 GHz and 60 GHz for
DVB-S and WPAN applications, respectively. For the second topic two kinds of injection
locked frequency dividers have been designed.
In Chapter 2, the Voltage Controlled Oscillator (VCO) is discussed and a 15 GHz
130 nm CMOS Quadrature Voltage Controlled Oscillator (QVCO) is presented, which
is used in a Ku band frequency synthesizer. At f0 =14.6 GHz the QVCO exhibits a
phase noise of −106 dBc/Hz at the offset frequency (∆f) of 1 MHz. The FOM of
−178.56 dBc/Hz is well aligned with other 130 nm CMOS VCOs reported in the literature.
In Chapter 3, frequency synthesizers are discussed and the millimeter wave VCO and
Injection Locking Frequency Divider blocks are presented.
Concerning the VCO, the measured carrier frequency (f0 ) goes from 71.87 GHz to
81.44 GHz for VT U N E ranging between 0 V and 1.8 V corresponding to a tuning range
of 12.4 %. The measurements of Voltage Controlled Oscillator (VCO) reveal a frequency shift versus the simulations. At f0 =71.8 GHz the VCO exhibits a phase noise of
−116 dBc/Hz at the offset frequency (∆f) of 10 MHz. The FOM is −181.2 dBc/Hz and
the FOMT is −183.1 dBc/Hz. The phase-noise-related FOM is well aligned with other
CMOS bulk VCOs reported in the literature, in particular for mmW applications.
Concerning the Injection Locking Frequency Divider two kinds of divider have been
designed: an Injection-Locked LC-tank Frequency Divider (ILLCFD) and a InjectionLocked Ring Oscillator Frequency Divider (ILROFD).
• Concerning the ILLCFD, it consumes 3.6 mW from a 1.2 V supply, excluding
buffers. With 0 dBm input power and VDD =1.2 V, the proposed ILLCFD Locking
Range is 15.7 GHz (63.5 GHz to 79.2 GHz) or 22 % of the center frequency. The
measurements of Injection-Locked LC-tank Frequency Divider (ILLCFD) present
very good agreement with the simulations and are well aligned with the state of
the art claimed in the literature.
• The proposed ILROFD is just back from the foundry and will be tested as soon as
87
Conclusions
possible. The post layout simulations show good performances with a total power
consumption of 4.8 mW.
(a) Chip microphotograph.
(b) Core Microphotograph.
Figure 4.1: Microphotograph of th cascoded VCO, ILLCFD and ILROFD.
Finally, the last contribution of the present Ph.D. thesis has been the integration on
the same die of the designed VCO, ILLCFD, and ILROFD. A microphotograph of the
fabricated prototype is depicted in Figure 4.1. The chip will be test as soon as possible.
All designed circuits shows a good performance in millimeter wave band. The critical
blocks of the PLL for WPAN applications have been designed. Next step is the design
of the rest of division chain, Phase-Frequency Detector (PFD), Charge-Pump (CP), ad
Loop Filter (LF).
88
Frequency generation for mm-Wave and satellite applications
Publications
Journals
• Paolo Lucchi, Davide Dermit, Gilles Jacquemod, Jean Baptiste Begueret, and Mattia Borgarino. “15 GHz quadrature voltage controlled oscillator in 130 nm CMOS
technology”. International Journal of Microwave and Wireless Technologies, 2011.
Conferences
• F. Benabdeljelil, G. Jacquemod, W. Tatinian, Lucchi, P., M. Borgarino, and L.
Carpineto. “Comparison between RTW VCO and LC QVC 12 GHz PLLs”. In
IEEE 9th International New Circuits and Systems Conference (NEWCAS), 2011,
pages 93 -96, june 2011.
• Lucchi, P., M. Borgarino, J. B. Begueret, and G. Jacquemod. “Low phase noise
130 nm CMOS ring VCO”. In IEEE 9th International New Circuits and Systems
Conference (NEWCAS), 2011, pages 89 -92, june 2011.
• Dermit D., Ducati F., Balsamo D., Lucchi P., Borgarino M., and Jacquemod G.
“A 130 nm CMOS tunable digital frequency divider for dual-band microwave radiometer”. In 16th IEEE International Conference on Electronics, Circuits, and
Systems (ICECS), 2009, pages 203 -206, dec. 2009.
• F. Chiesi, D. Dermit, P. Lucchi, M. Borgarino, and G. Jacquemod. “15GHz Dualmodulus 130 nm CMOS Digital Frequency Divider”. In SAME - Sophia Antipolis
MicroElectronics forum, Sophia Antipolis (France), September 2009.
• F. Ducati, F. Chiesi, D. Dermit, G. Manni, P. Lucchi, F. B. Abdeljelil, F. Sala, M.
Borgarino, G. Jacque- mod, and W. Tatinian. “Ku-BAND PLL FUNCTIONAL
BLOCKS”. In SAME - Sophia Antipolis Micro- Electronics forum, Sophia Antipolis
(France), September 2008.
89
Acronyms
ACC
Adaptive Cruise Control
ACM
Adaptive Coding & Modulation
AM
Amplitude Modulation
APSK
Amplitude and Phase-Shift-Keying
ASK
Amplitude-Shift-Keying
ATM
Asynchronous Transfer Mode
AV
Audio/Visual
AWGN
Additive White Gaussian Noise
BB
Base-Band
BC
Backwards-Compatible
BCH
Bose-Chaudhuri-Hocquenghem
BER
Bit Error Rate
BiCMOS Bipolar Complementary Metal Oxide Semiconductor
BPF
Band-Pass-Filter
BPSK
Binary PSK
CCM
Constant Coding & Modulation
CML
Current Mode Logic
CMOS
Complementary MOS
CMS
Common Mode Signaling
91
Acronyms
CP
Charge-Pump
CPPLL
Charge-Pump PLL
CPR
Cloud Profiling Radar
C/N
Carrier-to-Noise ratio
DAMI
Dual Alternate Mark Inversion
DBPSK
Differential BPSK
DC
Direct Current
DFF
D-Flip-Flop
DK
Design Kit
DRM
Design Rules Manual
DSNG
Digital Satellite News Gathering
DVB
Digital Video Broadcasting
DVB-S
Digital Video Broadcasting - Satellite
DVB-S2
Digital Video Broadcasting - Satellite - Second Generation
ECMA
European Computer Manufacturers Association
EHF
Extremely High Frequency
EIRP
Effective Isotropic Radiated Power
ELF
Extremely Low Frequency
ETSI
European Telecommunications Standards Institute
FCW
Frequency Control World
FD
Frequency Divider
FDM
Frequency Division Multiplex
FEC
Forward Error Correction
FOM
Figure Of Merit
GMSK
Gaussian MSK
GPR
Ground Penetrating Radar
GSG
Ground-Signal-Ground
92
Frequency generation for mm-Wave and satellite applications
Acronyms
GSGSG
Ground-Signal-Ground-Signal-Ground
GSM
Global System for Mobile communication
HDMI
High Definition Multimedia Interface
HRP
High-Rate PHY
HEMT
High Electron Mobility Transistor
HSI
High-Speed Interface
HF
High Frequency
IC
Integrated Circuit
IEEE
Institute of Electrical and Electronics Engineers
IL
Injection-Locked
ILO
Injection-Locked Oscillator
I-MOS
inversion mode N-MOS
ITRS
International Technology Roadmap for Semiconductor
ITU
International Telecommunications Union
ITS
Intelligent Transportation Systems
ILFD
Injection Locking Frequency Divider
IR
infrared
IVC
inter-vehicle
LC
LC-tank
ILLCFD
Injection-Locked LC-tank Frequency Divider
ILROFD
Injection-Locked Ring Oscillator Frequency Divider
LDPC
Low Density Parity check Codes
LF
Loop Filter
LPF
Low-Pass Filter
LNA
Low Noise Amplifier
LNB
Low Noise Block
LR
Locking Range
Frequency generation for mm-Wave and satellite applications
93
Acronyms
LRP
Low-Rate PHY
LRR
Long-Range Radar
MAC
Medium Access Control
MCML
MOS Current Mode Logic
MF
Medium Frequency
MOS
Metal-Oxide-Semiconductor
MPEG
Moving Picture Experts Group
MOSFET MOS Field-Effect Transistor
MSK
Minimum-Shift Keying
mmW
millimeter Wave
NLOS
Non-LIne-Of-Sight
OBO
Output Back-Off
OFDM
Orthogonal Frequency Division Multiplexing
PA
Power Amplifier
PCB
Printed Circuit Board
PFD
Phase-Frequency Detector
PHY
Physical Layer
PLL
Phase-Locked Loop
PM
Phase Modulation
PSK
Phase-Shift Keying
PVT
Process-Voltage-Temperature
QAM
Quadrature Amplitude Modulation
QPSK
Quadrature PSK
QVCO
Quadrature Voltage Controlled Oscillator
RF
Radio Frequency
RO
Ring Oscillator
ROFD
Ring Oscillator Frequency Divider
94
Frequency generation for mm-Wave and satellite applications
Acronyms
RVC
roadside to vehicle
SC
Single Carrier
SCBT
Single Carrier Block Transmission
SCL
Source Coupled Logic
SFD
Static FD
SHF
Super High Frequency
SLF
Super Low Frequency
SRR
Short Range Radar
TR
Tuning Range
TSPC
True Single Phase Clock
ULF
Ultralow Frequency
UV
ultraviolet
UHF
Ultrahigh Frequency
USB
Universal Serial Bus
UWB
Ultra-Wideband
VCO
Voltage Controlled Oscillator
VHF
Very High Frequency
VLF
Very Low Frequency
WPAN
Wireless Personal Area Network
WLANs
Wireless Local Area Networks
Frequency generation for mm-Wave and satellite applications
95
Bibliography
[1] B. Razavi, RF Microelectronics, 1st ed.
Hall, 1998.
Upper Saddle River, NJ, USA: Prentice
[2] D. Dermit, “CMOS Digital Phase-Locked Loops and Power Amplifiers,” Ph. D.
dissertation, Universitá degli Studi di Modena e Reggio Emilia, 2011.
[3] “Etsi en 302 307 v1.2.1: Digital video broadcasting (dvb); second generation
framing structure, channel coding and modulation systems for broadcasting,
interactive services, news gathering and other broadband satellite applications
(dvb-s2),” 2009-08. [Online]. Available: http://www.etsi.org
[4] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed.
York, NY, USA: Cambridge University Press, 2004.
New
[5] A. Mazzanti, “Analysis and Design of Injection Locked CMOS Oscillators for Radio
Frequency Quadrature Generation,” Ph. D. dissertation, Universitá degli Studi di
Modena e Reggio Emilia, 2005.
[6] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE
Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717 –724, may 1999.
[7] J. Rael and A. Abidi, “Physical processes of phase noise in differential LC oscillators
,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2000,
pp. 569 –572.
[8] F. Svelto and R. Castello, “A bond-wire inductor-MOS varactor VCO tunable from
1.8 to 2.4 GHz ,” IEEE Transactions on Microwave Theory and Techniques, vol. 50,
no. 1, pp. 403 –407, jan 2002.
[9] P. Kinget, Analog circuit design: (X)DSL and other communication systems; RF
MOST models; integrated filters and oscillators. Kluwer Academic Publishers, 1999,
ch. Integrated GHz voltage controlled oscillators, pp. 353 – 381.
97
Bibliography
[10] M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp.
1018 –1024, jul 2001.
[11] S. Toso, A. Bevilacqua, M. Tiebout, N. Da Dalt, A. Gerosa, and A. Neviani, “A
0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS,” IEEE
Journal of Solid-State Circuits, vol. 45, no. 7, pp. 1295 –1304, july 2010.
[12] K. Miyashita, “A plastic packaged Ku-band LNB with very high susceptibility to
supply PLL in 0.18um CMOS,” in Topical Meeting on Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), jan. 2010, pp. 188 –191.
[13] C. T. Fu and H. Luong, “A 0.8V CMOS quadrature LC VCO using capacitive
coupling,” in IEEE Asian Solid-State Circuits Conference (ASSCC), nov. 2007, pp.
436 –439.
[14] B. Fahs, W. Ali-Ahmad, and P. Gamand, “A Two-Stage Ring Oscillator in 0.13µm CMOS for UWB Impulse Radio,” IEEE Transactions on Microwave Theory
and Techniques, vol. 57, no. 5, pp. 1074 –1082, may 2009.
[15] S. Zafar, M. Awan, and T. Zulkifli, “5-GHz low-phase noise quadrature VCO in
0.13µm RF CMOS process technology,” in IEEE 10th Annual Wireless and Microwave Technology Conference (WAMICON), april 2009, pp. 1 –4.
[16] Y. Han, L. Larson, and D. Lie, “A low-voltage 12GHz VCO in 0.13-µm CMOS for
OFDM applications,” in Topical Meeting on Silicon Monolithic Integrated Circuits
in RF Systems (SiRF)- Digest of Papers, jan. 2006, p. 4 pp.
[17] C.-Y. Jeong and C. Yoo, “5-GHz Low-Phase Noise CMOS Quadrature VCO,” IEEE
Microwave and Wireless Components Letters, vol. 16, no. 11, pp. 609 –611, nov.
2006.
[18] M. Hossain and A. Carusone, “CMOS Oscillators for Clock Distribution and
Injection-Locked Deskew,” IEEE Journal of Solid-State Circuits, vol. 44, no. 8,
pp. 2138 –2153, aug. 2009.
[19] M. Tormanen and H. Sjoland, “A 26-GHz LC-QVCO in 0.13-µm CMOS,” in AsiaPacific Microwave Conference (APMC), dec. 2007, pp. 1 –4.
[20] “A companion guide to dvb-s2, tandberg television (uk),” 2004. [Online]. Available:
http://www.arctekhd.com/news/stories/DVBS-2_guide.pdf
[21] “Integrated mixer oscillator pll for satellite lnb, tff1004hn/n1 datasheet, rev. 01,”
2008.
[22] P. Lucchi, D. Dermit, G. Jacquemod, J. B. Begueret, and M. Borgarino, “15 GHz
quadrature voltage controlled oscillator in 130 nm CMOS technology,” International
Journal of Microwave and Wireless Technologies, 2011.
98
Frequency generation for mm-Wave and satellite applications
Bibliography
[23] F. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849–1858, Nov. 1980.
[24] W. Keese, “An analysis and performance evaluation of a passive
filter design technique for charge pump phase-locked loops,” May
1996, national Instrument Application Note 1001. [Online]. Available:
http://www.national.com/an/AN/AN-1001.pdf
[25] H. Cheema, R. Mahmoudi, M. Sanduleanu, and A. van Roermund, “A Ka Band,
Static, MCML Frequency Divider, in Standard 90nm-CMOS LP for 60 GHz Applications,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), june
2007, pp. 541 –544.
[26] H.-D. Wohlmuth, D. Kehrer, and W. Simburger, “A high sensitivity static 2:1 frequency divider up to 19 GHz in 120 nm CMOS,” in IEEE Radio Frequency Integrated
Circuits Symposium (RFIC), 2002, pp. 231 –234.
[27] B. Kim, D. Helman, and P. Gray, “A 30-MHz hybrid analog/digital clock recovery
circuit in 2-µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 25, no. 6, pp.
1385 –1394, dec 1990.
[28] H. Knapp, H.-D. Wohlmuth, M. Wurzer, and M. Rest, “25 GHz static frequency
divider and 25 Gb/s multiplexer in 0.12 µm CMOS,” in IEEE International SolidState Circuits Conference (ISSCC) - Digest of Technical Papers, vol. 1, 2002, pp.
302 –468 vol.1.
[29] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “50 GHz static frequency divider in
130 nm CMOS,” Electronics Letters, vol. 44, no. 4, pp. 285 –286, 14 2008.
[30] J.-O. Plouchart, J. Kim, H. Recoules, N. Zamdmer, Y. Tan, M. Sherony, A. Ray,
and L. Wagner, “A power-efficient 33 GHz 2:1 static frequency divider in 0.12-µm
SOI CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), june
2003, pp. 329 – 332.
[31] G. von Buren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, and H. Jackel,
“A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm
CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC) - Digest
of Technical Papers, feb. 2006, pp. 2462 –2471.
[32] B. Liang, D. Chen, B. Wang, D. Cheng, and T. Kwasniewski, “A 43-GHZ static frequency divider in 0.13 µm standard CMOS,” in Canadian Conference on Electrical
and Computer Engineering (CCECE), may 2008, pp. 000 111 –000 114.
[33] J.-Y. Chang and S.-I. Liu, “A 4-54GHz Static Frequency Divider with Back-Gate
Coupling,” in International Symposium on VLSI Design, Automation and Test
(VLSI-DAT), april 2007, pp. 1 –4.
Frequency generation for mm-Wave and satellite applications
99
Bibliography
[34] H. Matsumura, “80-GHz and 40-GHz frequency dividers in 65-nm CMOS,” in Asia
Pacific Microwave Conference (APMC), dec. 2009, pp. 297 –300.
[35] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE Journal of
Solid-State Circuits, vol. 24, no. 1, pp. 62–70, Feb. 1989.
[36] J. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design
Perspective, 2nd ed. Upper Saddle River, NJ, USA: Prentice Hall, 2002.
[37] R. Miller, “Fractional-frequency generators utilizing regenerative modulation,” Proceedings of the IRE, vol. 27, pp. 446–457, July 1939.
[38] H. Rategh and T. Lee, “Superharmonic injection-locked frequency dividers,” IEEE
Journal of Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[39] R. R. Severino, “Design Methodology for Millimeter Wave Integrated Circuits: Application to SiGe BiCMOS LNAs,” Ph. D. dissertation, Université de Bordeaux,
2011.
[40] A. M. Niknejad and H. Hashemi, mm-Wave Silicon Technology: 60 GHz and Beyond.
Springer; 1 edition, 2008.
[41] S. Yong, P. Xia, and A. Garcia, 60GHz Technology for Gbps WLAN
and WPAN: From Theory to Practice. Wiley, 2011. [Online]. Available:
http://books.google.co.ke/books?id=2QoQ1GXOxW0C
[42] X. Zhu, A. Doufexi, and T. Kocak, “On the performance of IEEE 802.15.3c
millimeter-wave WPANs: PHY and MAC,” in 2010 6th Conference onWireless
Advanced (WiAD), june 2010, pp. 1 –6.
[43] “IEEE Standard for Information Technology - Telecommunications and Information
Exchange Between Systems - Local and Metropolitan Area Networks - Specific Requirements Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer
(PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs)
Amendment 1: Mac Sublayer,” IEEE Std 802.15.3b-2005 (Amendment to IEEE
Std 802.15.3-2003), pp. 01 –146, 2006.
[44] “WirelessHD,” 2010. [Online]. Available: http://www.wirelesshd.org/
[45] “Wireless
Gigabit
Alliance,”
http://wirelessgigabitalliance.org/
2010.
[Online].
Available:
[46] “IEEE 802.11 Working Group, Very High Throughput in 60 GHz.” [Online].
Available: http://www.ieee802.org/11/Reports/tgad_update.htm
[47] “Standard ECMA-387. High Rate 60 GHz PHY, MAC and HDMI PAL.” [Online].
Available: http://www.ecma-international.org/
100
Frequency generation for mm-Wave and satellite applications
Bibliography
[48] “ETSI Standards "Electromagnetic compatibility and Radio spectrum Matters
(ERM); Technical characteristics of multiple gigabit wireless systems in the 60GHz
range System Reference Document (TR 102 555 Ver. 1.1.1),” Feb. 2009. [Online].
Available: http://www.etsi.org/WebSite/Technologies/AutomotiveRadar
[49] “ETSI Standards "Broadband Radio Access Networks (BRAN); 60 GHz MultipleGigabit WAS/RLAN Systems; Harmonized EN covering the essential requirements
of article 3.2 of the R&TTE Directive (EN 302 567 Ver. 1.1.1),” Feb. 2009. [Online].
Available: http://www.etsi.org/WebSite/Technologies/AutomotiveRadar
[50] M. Schneider, “Automotive Radar - Status and Trends,” in German Microwave
Conference, april 2005, pp. 144 –147.
[51] D. Grimes and T. Jones, “Automotive radar: A brief review,” Proceedings of the
IEEE, vol. 62, no. 6, pp. 804 – 822, june 1974.
[52] J. Wenger and S. Hahn, “Long Range and Ultra-Wideband Short Range Automotive
Radar,” in ICUWB 2007. IEEE International Conference on Ultra-Wideband, 2007,
sept. 2007, pp. 518 –522.
[53] D. Liu, U. Pfeiffer, and J. Grzyb, Advanced millimeter-wave technologies:
antennas, packaging and circuits. J. Wiley & Sons, 2009. [Online]. Available:
http://books.google.co.ke/books?id=t5d4-_h1TBQC
[54] D. Woolard, W. Loerop, and M. Shur, Terahertz Sensing Technology:
Emerging scientific applications & novel device concepts, ser. Selected topics
in electronics and systems. World Scientific, 2003. [Online]. Available:
http://books.google.com/books?id=QgwPrSBDROUC
[55] C. Cao, Y. Ding, and K. O, “A 50-GHz Phase-Locked Loop in 0.13-µm CMOS,”
IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1649 –1656, aug. 2007.
[56] H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, and R. Fujimoto, “A
60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS,” in 33rd
European Solid State Circuits Conference (ESSCIRC), 11-13 2007, pp. 472 –475.
[57] C. Lee and S. luan Liu, “A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS,”
in IEEE International Solid-State Circuits Conference (ISSCC) -Digest of Technical
Papers, 11-15 2007, pp. 196 –596.
[58] J. Lee, M. Liu, and H. Wang, “A 75-GHz Phase-Locked Loop in 90-nm CMOS
Technology,” IEEE Journal of Solid-State Circuits., vol. 43, no. 6, pp. 1414 –1426,
june 2008.
[59] K.-H. Tsai and S.-I. Liu, “A 62-66.1GHz phase-locked loop in 0.13um CMOS technology,” in IEEE International Symposium on VLSI Design, Automation and Test
(VLSI-DAT), 23-25 2008, pp. 113 –116.
Frequency generation for mm-Wave and satellite applications
101
Bibliography
[60] C. Lee, L.-C. Cho, J.-H. Wu, and S.-I. Liu, “A 50.8-53-GHz Clock Generator Using
a Harmonic-Locked PD in 0.13-µm CMOS,” IEEE Transactions on Circuits and
Systems II: Express Briefs,, vol. 55, no. 5, pp. 404 –408, may 2008.
[61] C. Marcu, D. Chowdhury, C. Thakkar, J.-D. Park, L.-K. Kong, M. Tabesh, Y. Wang,
B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, E. Alon, and A. Niknejad, “A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband
Circuitry,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3434 –3447,
dec. 2009.
[62] K.-H. Tsai and S.-I. Liu, “A 43.7mW 96GHz PLL in 65nm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC) - Digest of Technical Papers,
8-12 2009, pp. 276 –277,277a.
[63] Z. Xu, Q. Gu, Y.-C. Wu, H.-Y. Jian, F. Wang, and M.-C. Chang, “An integrated
frequency synthesizer for 81-86GHz satellite communications in 65nm CMOS,” in
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), may 2010, pp. 57
–60.
[64] K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, “A 57-to-66GHz quadrature
PLL in 45nm digital CMOS,” in IEEE International Solid-State Circuits Conference
(ISSCC) - Digest of Technical Papers, feb. 2009, pp. 494 –495,495a.
[65] F. Barale, P. Sen, S. Sarkar, S. Pinel, and J. Laskar, “A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS,” IEEE Microwave
and Wireless Components Letters, vol. 20, no. 7, pp. 411 –413, july 2010.
[66] H.-K. Chen, T. Wang, and S.-S. Lu, “A Millimeter-Wave CMOS Triple-Band PhaseLocked Loop With A Multimode LC-Based ILFD,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 5, pp. 1327 –1338, may 2011.
[67] S. Bozzola, “Insights into the Dasign of mm-Wave CMOS Receiver for GB/s Applications,” Ph. D. dissertation, Universitá degli Studi di Pavia, 2010.
[68] S. Bozzola, D. Guermandi, A. Mazzanti, and F. Svelto, “An 11.5 % frequency tuning,
184 dBc/Hz noise FOM 54 GHz VCO,” in IEEE Radio Frequency Integrated Circuits
Symposium (RFIC), april 17 2008, pp. 657 –660.
[69] C. Cao and K. O, “Millimeter-wave voltage-controlled oscillators in 0.13- µm CMOS
technology,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1297 – 1304,
june 2006.
[70] D. Huang, W. Hant, N.-Y. Wang, T. Ku, Q. Gu, R. Wong, and M.-C. Chang, “A
60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric
for Size, Loss and Noise Reduction,” in IEEE International Solid-State Circuits
Conference (ISSCC) - Digest of Technical Papers, feb. 2006, pp. 1218 –1227.
102
Frequency generation for mm-Wave and satellite applications
Bibliography
[71] J. Borremans, M. Dehan, K. Scheir, M. Kuijk, and P. Wambacq, “VCO design for
60 GHz applications using differential shielded inductors in 0.13 µm CMOS,” in
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), april 17 2008, pp.
135 –138.
[72] H.-K. Chen, H.-J. Chen, D.-C. Chang, Y.-Z. Juang, and S.-S. Lu, “A 0.6 V, 4.32
mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13µm
CMOS,” IEEE Microwave and Wireless Components Letters, vol. 18, no. 7, pp. 467
–469, july 2008.
[73] P. Sakian, E. v. d. Heijden, H. Cheema, R. Mahmoudi, and A. van Roermund, “A
57-63 GHz quadrature VCO in CMOS 65 nm,” in European Microwave Integrated
Circuits Conference (EuMIC), sept. 2009, pp. 120 –123.
[74] L. Li, P. Reynaert, and M. Steyaert, “A 60-GHz CMOS VCO Using CapacitanceSplitting and Gate-Drain Impedance-Balancing Techniques,” IEEE Transactions on
Microwave Theory and Techniques, vol. 59, no. 2, pp. 406 –413, feb. 2011.
[75] J. Gonzalez, F. Badets, B. Martineau, and D. Belot, “A 56-GHz LC-Tank VCO
With 17 % Tuning Range in 65-nm Bulk CMOS for Wireless HDMI,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 5, pp. 1359 –1366, may
2010.
[76] A. Katz, O. Degani, and E. Socher, “Design and optimization of a low-noise crosscoupled fundamental VCO in 90nm CMOS for 60GHz applications,” in IEEE 11th
Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
jan. 2011, pp. 13 –16.
[77] A. Mazzanti, P. Uggetti, and F. Svelto, “Analysis and design of injection-locked LC
dividers for quadrature generation,” IEEE Journal of Solid-State Circuits, vol. 39,
no. 9, pp. 1425 – 1433, sept. 2004.
[78] S. Shekhar, G. Balamurugan, D. Allstot, M. Mansuri, J. Jaussi, R. Mooney,
J. Kennedy, B. Casper, and F. O’Mahony, “Strong Injection Locking in Low-Q
LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver,”
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp.
1818 –1829, aug. 2009.
[79] K. H. Tsai, L. C. Cho, J. H. Wu, and S. L. Liu, “3.5mW W-Band Frequency Divider
with Wide Locking Range in 90nm CMOS Technology,” in IEEE International SolidState Circuits Conference (ISSCC). Digest of Technical Papers., feb. 2008, pp. 466
–628.
[80] L. Cho, K. Tsai, C.-C. Hung, and S. I. Liu, “81.5-85.9 GHz injection-locked frequency divider in 65 nm CMOS,” Electronics Letters, vol. 44, no. 16, pp. 966 –968,
july 2008.
Frequency generation for mm-Wave and satellite applications
103
Bibliography
[81] L. C. Cho, K. H. Tsai, C. C. Hung, and S. L. Liu, “93.5-109.4GHz CMOS injectionlocked frequency divider with 15.3% locking range,” in IEEE Symposium on VLSI
Circuits, 2008, june 2008, pp. 86 –87.
[82] K. Takatsu, H. Tamura, T. Yamamoto, Y. Doi, K. Kanda, T. Shibasaki, and
T. Kuroda, “A 60-GHz 1.65mW 25.9 % locking range multi-order LC oscillator
based injection locked frequency divider in 65nm CMOS,” in IEEE Custom Integrated Circuits Conference (CICC), sept. 2010, pp. 1 –4.
[83] P. Mayr, C. Weyers, and U. Langmann, “A 90GHz 65nm CMOS InjectionLocked Frequency Divider,” in IEEE International Solid-State Circuits Conference
(ISSCC). Digest of Technical Papers., 11-15 2007, pp. 198 –596.
[84] I.-T. Lee, K.-H. Tsai, and S.-I. Liu, “A 104- to 112.8-GHz CMOS Injection-Locked
Frequency Divider,” IEEE Transactions on Circuits and Systems II: Express Briefs,,
vol. 56, no. 7, pp. 555 –559, july 2009.
[85] B.-Y. Lin, K.-H. Tsai, and S.-I. Liu, “A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC) - Digest of Technical Papers, 8-12 2009, pp. 282 –283,283a.
[86] B.-Y. Lin and S.-I. Liu, “A 132.7-to-143.5GHz injection-locked frequency divider in
65nm CMOS,” in Symposium on VLSI Circuits, 16-18 2009, pp. 230 –231.
[87] C.-Y. Wu and C.-Y. Yu, “Design and Analysis of a Millimeter-Wave Direct InjectionLocked Frequency Divider With Large Frequency Locking Range,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 8, pp. 1649 –1658, aug.
2007.
[88] C.-C. Chen, H.-W. Tsao, and H. Wang, “Design and Analysis of CMOS Frequency
Dividers With Wide Input Locking Ranges,” IEEE Transactions on Microwave
Theory and Techniques, vol. 57, no. 12, pp. 3060 –3069, dec. 2009.
[89] Q. Gu, H.-Y. Jian, Z. Xu, Y.-C. Wu, M.-C. Chang, Y. Baeyens, and Y.-K. Chen,
“200GHz CMOS prescalers with extended dividing range via time-interleaved dual
injection locking,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
may 2010, pp. 69 –72.
[90] S. Rong, A. Ng, and H. Luong, “0.9mW 7GHz and 1.6mW 60GHz frequency dividers
with locking-range enhancement in 0.13 µm CMOS,” in IEEE International SolidState Circuits Conference (ISSCC)- Digest of Technical Papers, feb. 2009, pp. 96
–97.
[91] H. Wang, L. Zhang, D. Yang, D. Zeng, L. Zhang, Y. Wang, and Z. Yu, “A 60GHz
wideband injection-locked frequency divider with adaptive-phase-enhancing technique,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), june 2011,
pp. 1 –4.
104
Frequency generation for mm-Wave and satellite applications
Bibliography
[92] J.-C. Chien and L.-H. Lu, “Analysis and Design of Wideband Injection-Locked Ring
Oscillators With Multiple-Input Injection,” IEEE Journal of Solid-State Circuits,
vol. 42, no. 9, pp. 1906 –1915, sept. 2007.
[93] C.-C. Hung, C. Lee, L.-C. Cho, and S.-I. Liu, “A 57.1-59GHz CMOS fractional-N
frequency synthesizer using quantization noise shifting technique,” in IEEE Asian
Solid-State Circuits Conference (ASSCC), 3-5 2008, pp. 413 –416.
[94] Z. Deng, J. Chen, J. Tsai, and A. Niknejad, “A CMOS Ku-band single-conversion
low-noise block front-end for satellite receivers,” in IEEE Radio Frequency Integrated
Circuits Symposium (RFIC), june 2009, pp. 135 –138.
[95] G. Girlando, S. Smerzi, T. Copani, and G. Palmisano, “A monolithic 12-GHz heterodyne receiver for DVB-S applications in silicon bipolar technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 3, pp. 952 – 959, march
2005.
Frequency generation for mm-Wave and satellite applications
105