Application Report
SLUA371 – September 2006
Closed-Loop Compensation Design of a Synchronous
Switching Charger Using bq2472x/3x
Lingyin Zhao........................................................................................................ PMP Portable Power
ABSTRACT
Design of the loop compensator is one of the key challenges in the circuit design of a
switching charger. This application report presents the internal control loop operation of
the bq2472x/3x as well as the external compensator design guideline. The modeling of
the nonlinear behavior of a switching charger is based on the state space average
model. A design example based on practical specifications is demonstrated.
1
2
3
4
Contents
Buck-Type Charger Power Stage Small-Signal Model ........................................ 2
bq2472x/3x Control-Loop Model and Compensation Design ................................. 6
Design Example .................................................................................... 9
Reference .......................................................................................... 19
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
The Power Stage of a Buck-Type Charger ..................................................... 2
Three-Terminal Model of a PWM Switch in CCM .............................................. 2
Control-to-Output Small-Signal Model in CCM ................................................. 3
Three-Terminal Model of a PWM Switch in DCM .............................................. 4
Control-to-Output Small-Signal Model in DCM ................................................. 5
PWM and Error Amplifiers Block of bq2472x/3x................................................ 6
Simplified Control-Loop Block Diagram.......................................................... 7
A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions ... 8
A Type III Compensator ........................................................................... 8
Bode Plot of a Typical Type III Compensator ................................................... 8
Control-to-Output-Voltage Transfer Function .................................................. 10
Control-to-Charge-Current Transfer Function ................................................. 11
Control-to-Input-Current Transfer Function .................................................... 12
Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain .......... 13
Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)................................. 14
Output-Voltage Loop Gain TV (CCM) ........................................................... 15
Charge-Current Loop Gain Tis (CCM) .......................................................... 16
Input-Current Loop Gain Tii (CCM) .............................................................. 17
Output-Voltage Loop Gain TV (DCM) ........................................................... 18
Input-Current Loop Gain Tii (DCM) ............................................................. 19
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Buck-Type Charger Power Stage Small-Signal Model
1
Buck-Type Charger Power Stage Small-Signal Model
A typical stage of a synchronous buck-type switching battery charger is shown in Figure 1.
Q1
RL
VIN
L
RSNS
IL
Q2
IS
VO
RC1
RC2
C1
C2
ZL
Figure 1. The Power Stage of a Buck-Type Charger
The small-signal model is obtained from the relationships among the perturbation in average terminal
quantities at a given dc operating point. The model is different under continuous conduction mode (CCM)
and discontinuous conduction mode (DCM).
1.1
Continuous Conduction Mode (CCM) Small-Signal Model
The average values of the switch network terminal waveforms can be determined in terms of the converter
state variables and the converter independent inputs. The basic assumption is made that the natural time
constants of the converter network are much longer than the switching period Ts. This assumption
coincides with the requirement for small switching ripple. The resulting averaged model predicts the
low-frequency behavior of the system, while neglecting the high-frequency switching harmonics [1]. The
three-terminal model for a PWM switch network in CCM is illustrated in Figure 2.
Vap
Q1
a
D
c
ˆ
d
c
a
Q2
^
ICd
D
1 1
p
(a) a PWM Switch
p
(b) Small-Signal Model
Figure 2. Three-Terminal Model of a PWM Switch in CCM
To perform the CCM small-signal analysis, the PWM switch in the buck converter is substituted with the
three-terminal model in CCM and Vin is shorted, as shown in Figure 3.
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Buck-Type Charger Power Stage Small-Signal Model
î i
Vin
d̂
D
1
RSNS
î L
L
RL
v̂ o
î s
RC1
RC2
C1
C2
D
ZL
Figure 3. Control-to-Output Small-Signal Model in CCM
The open-loop control-to-output-voltage transfer function is given as:
ǒws
ƞ
G
Vo
(s) +
vd
ƞ
d
+V
Z
in
z1
L
Ǔ ǒws
)1
Ǔ
)1
z2
l3s 3 ) l 2s2 ) l 1s ) l 0
(1)
Compared to a regular buck-type converter, this topology results in one more zero and one more pole,
both at high frequencies under normal conditions.
The open-loop control-to-charge-current transfer function is given as:
ǒws
ƞ
G
is
(s) +
isd
ƞ
d
+V
z1
in
Ǔ ǒws
)1
z3
Ǔ
)1
l 3s 3 ) l 2s2 ) l1s ) l 0
(2)
The open-loop control-to-input-current transfer function is given as:
ƞ
G
i
(s) + ƞi + I ) V
iid
L
in
d
a 2s2 ) a 1s ) 1
l3s 3 ) l 2s2 ) l 1s ) l 0
(3)
in which,
w z1 +
w z2 +
1
RC1
C1
(4)
C2
(5)
1
RC2
1
w z3 +
ǒRC1 ) ZLǓ
l 3 + ƪRC2
C2
Z L ) ǒRSNS ) R C1ǓǒRC2 ) Z LǓƫ
l 2 + ǒRL ) RC1ǓƪR C2
L
(6)
C1
Z L ) ǒRSNS ) RC1Ǔ ǒR C2 ) Z LǓƫ
C1 ) ǒRC2 ) Z LǓ ǒL * R 2C1
l 1 + ƪRC2
L
C 1Ǔ
C2
C1
(7)
C2 ) ǒZ L ) RSNS ) R C1Ǔ
C2
Z L ) ǒRSNS ) R LǓǒRC2 ) Z LǓƫ
(8)
C2 ) ǒZ L ) R SNS ) R LǓ ǒRL ) RC1Ǔ
C 1 ) L * R2L
C1
(9)
l 0 + Z L ) RSNS ) RL
a 2 + ƪRC2
(10)
Z L ) ǒRSNS ) R C1Ǔ ǒRC2 ) Z LǓƫ
a 1 + ǒZ L ) RSNS ) RC1Ǔ
C1 )
ǒR C2 ) Z LǓ
C1
C2
C2
(11)
(12)
Approximately, Gvd (s) and Gisd (s) can be presented as
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Buck-Type Charger Power Stage Small-Signal Model
ǒws
ZL
Z L ) RSNS ) R L
G vd(s) [ Vin
z1
Ǔ
ǒws ) w s Q ) 1Ǔǒws ) 1Ǔ
2
2
0
0
p1
z1
) 1 ws ) 1
z3
ǒws
1
G isd(s) [ Vin
Ǔǒ
) 1 ws ) 1
z2
Z L ) RSNS ) R L
Ǔǒ
(13)
Ǔ
ǒws ) w s Q ) 1Ǔǒws ) 1Ǔ
2
2
0
p1
0
(14)
in which,
w p1 +
w0 +
Q+
1.2
ǒZL ) R SNS ) R LǓ ǒC1 ) C2Ǔ
Z L ) ǒRSNS ) R C1Ǔ ǒRC2 ) Z LǓƫ
ƪRC2
C1
C2
(15)
1
ǸǒL
w0
C 1 ) C 2Ǔ
(16)
1
ǒR L ) R C1Ǔ ǒC1 ) C 2Ǔ
(17)
Discontinuous Conduction Mode (DCM) Small-Signal Model
Under DCM conditions, assume the dc voltage gain is
V
M+ o
V in
(18)
The duty cycle is given by
D+
2
(M*2)2
*1
M2
Ǹƪ
K
ƫ
(M * 2) 2
*1
M2
(19)
in which,
2L f s
K+
Vo
Io
(20)
The three-terminal model for a PWM switch network in CCM is illustrated in Figure 4.
v̂ ac
gi
Q1
a
c
c
a
ki d̂
Q2
gf v̂ac
p
(a) a PWM Switch
go
ko d̂
v̂cp
p
(b) Small-Signal Model
Figure 4. Three-Terminal Model of a PWM Switch in DCM
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Buck-Type Charger Power Stage Small-Signal Model
2I a
D
2I p
ko +
D
Ia
gi +
Vac
ki +
(21)
(22)
(23)
Ip
go +
Vcp
(24)
2I p
Vac
(25)
gf +
To perform the DCM small-signal analysis, the PWM switch in the buck converter is substituted with the
three-terminal model in DCM and Vin is shorted, as shown in Figure 5.
gi
k i d̂
gf
îi
îL
L
RL
go
kod̂
RSNS
v̂ o
îs
RC1
RC2
C1
C2
ZL
Figure 5. Control-to-Output Small-Signal Model in DCM
In a buck converter operating in DCM, the following equations can be obtained:
2
gi + D
2L f s
ki +
2I oM
D
(27)
2I o
D
k d + ki ) ko +
r+
(26)
(28)
V
1
+ o (I * M)
gi ) go ) gf
Io
(29)
The open-loop, control-to-output-voltage transfer function is given as:
ǒws
ƞ
G vd_DCM(s) +
vo
ƞ
d
+ kd
z1
ZL
Ǔ ǒws
)1
z2
Ǔ
)1
l3s 3 ) l 2s2 ) l 1s ) l 0
(30)
The open-loop, control-to-input-current transfer function is given as:
ƞ
i
G iid_DCM(s) + ƞi + k i * g i
d
in which,
L C1
g3 +
r
C2
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ƪR C2
kd
r ) gi
Kd
r
e 2s 2 ) e 1s ) 1
l3s 3 ) l2s 2 ) l 1s ) l 0
Z L ) ǒRSNS ) RC1ǓǒR C2 ) Z LǓƫ
Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x
(31)
(32)
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bq2472x/3x Control-Loop Model and Compensation Design
g2 +
C1
C2
r
ƪRC2
Z L ) ǒR SNS ) R C1ǓǒRC2 ) Z LǓƫ ) R C1
) Lr ƪǒR SNS ) R C1 ) Z LǓ
C
g 1 + r1
ƪǒRL ) rǓ
ǒR C2 ) Z LǓ ) R C2
ǒR C2 ) Z LNj
C2ƫ
C1 ) ǒRC2 ) Z LǓ
ǒR SNS ) R C1 ) ZLǓ ) RC1
ƪǒR L ) r ) RSNSǓ
R SNS
RSNS ) RC1
(33)
Z Lƫ
Z Lƫ ) Lr
(34)
R ) r ) R SNS ) Z L
g0 + L
r
e 2 + C1
C2
ƪRC2
e 1 + ǒRSNS ) RC1 ) Z LǓ
(35)
Z L ) ǒR SNS ) R C1ǓǒRC2 ) Z LǓƫ
C 1 ) ǒR C2 ) Z LǓ
(36)
C2
2
bq2472x/3x Control-Loop Model and Compensation Design
2.1
bq2472x/3x Control-Loop Model
(37)
The PWM and error amplifiers block of bq2472x/3x is illustrated in Figure 6. It consists of three feedback
loops: output-voltage loop, charge-current loop, and input-current loop (DPM loop). However, only one of
them dominates at one time. The simplified control-loop block diagram is depicted in Figure 7.
Figure 6. PWM and Error Amplifiers Block of bq2472x/3x
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bq2472x/3x Control-Loop Model and Compensation Design
v̂ i
Power Stage
d̂
G vd, G isd, G iid
v̂
iˆ iˆ
o s i
dˆ
FM
v̂ c
-A(s )
FG
Figure 7. Simplified Control-Loop Block Diagram
In Figure 7, FG is the feedback gain whose value depends on which loop is operating.
For the output-voltage loop,
1 6+1
(for 3 * cell)
6
FG + g rd g v + 1
6 + 0.75 (for 4 * cell)
8
ȡ
ȥ
Ȣ
in which grd and gv are the resistor divider gain and the voltage amplifier gain, respectively. For the
charge-current loop,
FG + R SNS g SR T damp1 + 40 R SNS T damp1
(38)
(39)
in which RSNS and gSR are the charge-current-sense resistor value and the charge-current amplifier gain,
respectively. Tdamp1 is the transfer function of the network added to damp the high-frequency harmonics
for this loop. It contains a pole at 60 kHz and another at 150 kHz.
1
T damp1(s) +
s
s
whfp1 ) 1 whfp2 ) 1
ǒ
Ǔǒ
For the DPM loop,
FG + R SNS g AC
Ǔ
T damp2 + 40
(40)
R SNS
T damp2
in which RSNA and gAC are the adapter input current-sense resistor value and the input current amplifier
gain, respectively. Tdamp2 is the transfer function of the network added to damp the high-frequency
harmonics for this loop. It contains a pole at 60 kHz and another at 150 kHz.
T damp2(s) + T damp1(s)
(41)
(42)
In Figure 7, A(s) is the compensator transfer function and FM is the control voltage to duty-cycle transfer
function. To generate a PWM drive signal, the control voltage Vc is compared with a ramp waveform, as
shown in Figure 6. The ramp peak voltage Vp = Vcc/10. Thus, the value of FM can be obtained as:
FM + 1
Vp
(43)
The three loop gains are given by
T v + G vd FG A(s) FM
(44)
T is + G isd
(45)
T ii + G iid
FG
FG
A(s)
A(s)
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FM
FM
Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x
(46)
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bq2472x/3x Control-Loop Model and Compensation Design
2.2
bq2472x/3x Compensator Design
Magnitude - dB
From Equation 13 and Equation 14, it can be seen that the power stage CCM open-loop transfer functions
are basically a three-pole-two-zero system. A typical Bode plot of the converter control to output gain
under CCM conditions is shown in Figure 8. However, it can be simplified as a double-pole system
because ωz1, ωz2, and ωp1 are normally located at high frequencies where the average model is not valid
any longer.
f - Frequency
Figure 8. A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions
A Type III compensator is a promising candidate for this application. The typical realization of a Type III
compensator is demonstrated in Figure 9. Its typical frequency response is depicted in Figure 10.
C1_com R 3_com
C 2_com R 2_com
C 3_com
EAO
EAI
FBO
R 1_com
Figure 9. A Type III Compensator
Magnitude - dB
Integrator
Pole 1 Pole 2
Zero 1 Zero 2
f - Frequency
Figure 10. Bode Plot of a Typical Type III Compensator
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Design Example
An integrator is needed for a high dc gain. Two zeroes need to be put below the loop gain crossover
frequency fc to compensate the excessive phase lag due to the integrator and the power stage complex
pole pair. In order to attenuate the high-frequency noise, two high frequency poles are added to ensure
the magnitude of the loop gain keeps decreasing after the 0-dB crossover. The two poles must be placed
below half of the switching frequency.
The transfer function of the compensator is given as:
s
s
wz1_com ) 1 wz2_com ) 1
A(s) + K
s w s )1 w s )1
ǒ
ǒ
Ǔǒ
Ǔǒ
p1_com
Ǔ
p2_com
Ǔ
(47)
where
K+
1
R 1_com
w z1_com +
w z2_com +
w p1_com +
ǒC1_com ) C3_comǓ
(48)
1
R3_com
C1_com
(49)
1
ǒR1_com ) R2_comǓ
C2_com
(50)
1
R2_com
C2_com
(51)
1
w p2_com +
R3_com
3
Design Example
3.1
Specifications
C1_com C3_com
C1_com)C3_com
(52)
Vin = 19 V, L = 10 µH, C1 = C2 = 20 µF, RSNS = RSNA = 10 mΩ, RC1 = RC2 = 10 mΩ, RL = 20mΩ,
Vbat = 9 V – 12.6 V (3s2p), Ichrg = 4 A, fs = 300 kHz
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Design Example
3.2
Power Stage Open-Loop Transfer Functions (CCM)
The transfer functions of the converter in CCM are illustrated in Figure 11, Figure 12, and Figure 13.
60
Magnitude - dB
ZL = 17.8 W
20
ZL = 2.25 W
0
-20
-60
1
10
10 k
100
1k
f - Frequency - Hz
(a) Gain
100 k
1M
Phase - Deg
180
ZL = 17.8 W
0
ZL = 2.25 W
-180
1
10
100
10 k
1k
f - Frequency - Hz
(b) Phase
100 k
1M
Figure 11. Control-to-Output-Voltage Transfer Function
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Design Example
Magnitude - dB
100
ZL = 2.25 W
0
ZL = 17.8 W
-100
1
10
100
1k
10 k
100 k
1M
f - Frequency - Hz
(a) Gain
100
Phase - deg
ZL = 17.8 W
ZL = 2.25 W
0
-180
1
10
100
1k
10 k
100 k
1M
f - Frequency - Hz
(b) Phase
Figure 12. Control-to-Charge-Current Transfer Function
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Design Example
Magnitude - dB
100
20
ZL = 2.25 W
0
ZL = 17.8 W
-20
-100
1
10
1k
100
10 k
100
1M
100
1M
f - Frequency - Hz
(a) Gain
180
Phase - deg
ZL = 17.8 W
ZL = 2.25 W
0
-180
1
10
100
1k
10 k
f - Frequency - Hz
(b) Phase
Figure 13. Control-to-Input-Current Transfer Function
3.3
Compensator Design Procedure
From the preceding calculation, the following parameters can be obtained:
1
w z1 +
+ 796 kHz
RC1 C1
w z2 +
w0 +
1
RC2
C2
+ 796 kHz
1
ǸǒL
(53)
C 1 ) C 2Ǔ
(54)
+ 8 kHz
(55)
Place the two compensator zeros before the resonant frequency of the converter (f0) to improve the DCM
stability.
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Design Example
Select
w z1_com + 2p
0.5
f 0 + 25 kHz
(56)
w p1_com + wp2_com + 1 2pf s + 943 kHz
2
(57)
Because ωz1, ωz2 are higher than half of the switching frequency, place the two high-frequency poles at
0.5fs:
w p1_com + wp2_com + 1 2pf s + 943 kHz
2
(58)
Set a crossover frequency fc (voltage loop) of 10 kHz – 20 kHz. Select K = 2500 to make fc≈ 15 kHz with
about 60° phase margin. Normally, a phase margin greater than 40° is desirable. The transfer function of
Gvd, the compensator and the entire voltage loop gain Tv are shown in Figure 14.
80
TV(S)
Magnitude - dB
Gvd(S)
0
A(S)
-80
1
10
100
100
10 k
1k
1M
f - Frequency - Hz
(a) Gain
180
Phase - deg
A(S)
0
TV(S)
Gvd(S)
-180
1
10
100
10 k
1k
f - Frequency - Hz
(b) Phase
100
1M
Figure 14. Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain
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Design Example
Assuming R1_com = 200k, based on equations (48)–(52), the preliminary compensator component values
can be determined as:
R1_com = 200kΩ, R2_com = 7.5kΩ, R3_com = 20kΩ, C1_com = 2000pF, C2_com = 130pF, C3_com = 51pF.
3.4
3.4.1
Check Loop Gains With Various Loads
Li-Ion Battery Equivalent Circuit Model
Figure 15 shows the typical Li-ion battery equivalent circuit model used for the small-signal analysis. lt is
approximately correct for charged state from 100% of SOC to 20% of SOC. Impedance varies from
manufacturer to manufacturer up to two times and from cell to cell up to ±15%. For a discharged state
below 20% of SOC, the impedance starts to increase rapidly. The particular value the impedance reaches
depends on manufacturer, but it can be roughly modeling by multiplying R1 and R2 by 3.
R hf
R SER
L
R1
R2
C1
C2
NOTE: R1 = 13.77 mW, C1 = 0.337672 F, R2 = 47.15 mW,
C2 = 1.79935 F, RSER = 65.18 mW, Rhf = 5.8 W, L = 0.637 mH
NOTE: R1=13.77 mΩ, C1=0.337672 F, R2=47.15 mΩ, C2=1.79935 F, RSER= 65.18 mΩ, Rhf=5.8 Ω, L=0.637 µH
Figure 15. Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)
3.4.2
CCM Loop Gains With Various Loads (Including Battery Load)
Plot the output-voltage loop gain, and check the stability and bandwidth with a 3s2p battery load, as
shown in Figure 16.
Plot the charge-current and input-current loop gains, and check the stability and bandwidth. The entire
charge-current and input-current loop gains Tis and Tii are shown in Figure 17 and Figure 18, respectively.
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Design Example
100
Magnitude - dB
ZL = 17.8 W
ZL =2.25 W
0
ZL = Zbat(s)
-100
1
10
100
10 k
1k
f - Frequency - Hz
(a) Gain
100 k
1M
Phase - deg
100
ZL = 17.8 W
0
ZL =2.25 W
ZL = Zbat(s)
-100
1
10
100
10 k
1k
f - Frequency - Hz
(b) Phase
100 k
1M
Figure 16. Output-Voltage Loop Gain TV (CCM)
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Design Example
Figure 17. Charge-Current Loop Gain Tis (CCM)
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Design Example
100
ZL = Zbat(s)
Magnitude - dB
ZL =2.25 W
0
ZL = 17.8 W
-100
1
10
100
10 k
1k
f - Frequency - Hz
(a) Gain
100 k
1M
100 k
1M
180
Phase - deg
ZL = 17.8 W
ZL =2.25 W
0
ZL = Zbat(s)
-180
1
10
100
10 k
1k
f - Frequency - Hz
(b) Phase
Figure 18. Input-Current Loop Gain Tii (CCM)
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Design Example
3.5
Check Loop Gains Under DCM Condition
Plot the output-voltage and input-current loop gains, and check the stability and bandwidth. The entire
output-voltage and input-current loop gains Tv and Tii are shown in Figure 19 and Figure 20, respectively.
100
IO = 40 mA
ZL =315 W
Magnitude - dB
IO = 700 mA
ZL = 17.8 W
0
IO = 40 mA
ZL = Zbat(s)
-100
1
10
100
10 k
1k
f - Frequency - Hz
(a) Gain
100 k
1M
180
Magnitude - dB
IO = 40 mA
ZL = Zbat(s)
IO = 700 mA
0
ZL = 17.8 W
IO = 40 mA
ZL =315 W
-180
1
10
100
10 k
1k
f - Frequency - Hz
(a) Gain
100 k
1M
Figure 19. Output-Voltage Loop Gain TV (DCM)
18
Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x
SLUA371 – September 2006
Submit Documentation Feedback
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Reference
50
IO = 40 mA
ZL =315 W
IO = 700 mA
ZL = 17.8 W
Magnitude - dB
0
IO = 40 mA
ZL = Zbat(s)
-100
1
10
100
10 k
1k
f - Frequency - Hz
(a) Gain
100 k
1M
100 k
1M
Magnitude - dB
180
IO = 700 mA
0
IO = 40 mA
ZL = 17.8 W
ZL =315 W
IO = 40 mA
ZL = Zbat(s)
-180
1
10
100
10 k
1k
f - Frequency - Hz
(b) Phase
Figure 20. Input-Current Loop Gain Tii (DCM)
From the transfer function Bode plots obtained, it is seen that this compensator design offers adequate
phase margins and bandwidths for all three loops. If not, the parameters (K, ωz1_com, ωz2_com) can be
adjusted to get a reasonable design.
4
Reference
1. R. W. Erickson, D. Maksimvić, Fundamentals of Power Electronics (Second Edition), Kluwer Academic
Publishers, Sixth Printing 2004.
2. Fred C. Lee, Modeling and Control Design of DC/DC Converters, CPES Lecture Notes, Virginia Tech,
2004.
SLUA371 – September 2006
Submit Documentation Feedback
Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x
19
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