WHITE PAPER: WP005
Paralleling eGan® FETs
Paralleling eGan® FETs
EFFICIENT POWER CONVERSION
Alex Lidow PhD, CEO and Michael de Rooij, PH.D., Director, Applications, Efficient Power Conversion Corporation
To parallel switching devices is a natural progression that enables increased power performance for switching converters
[1,2,5,6,7,8,9,10]. Paralleling gallium nitride transistors poses
many new challenges as these devices can be switched ten times
faster than commercial MOSFETs. These challenges are presented
in this paper and recommendations made to ensure the best performance from a paralleled switch converter.
Five basic designs, utilizing four EPC2001 (100 V, 25 A) paralleled
In this paper a “switch” is consistently defined as the paralleled group of FETs
acting as a single transistor. The discussion about paralleling of eGaN FETs will
furthermore be limited to a single gate driver per switch due to timing complexity issues present when using multiple gate drivers.
Paralleling of eGaN FETs shares many similarities with that of MOSFET paralleling, however some differences exist requiring special attention to achieve a
successful outcome. Some main areas that will be discussed include:
• The impact of device characteristics on the ability to parallel eGaN FETs.
devices per switch, in a half bridge configuration are presented.
• The main circuit characteristics that need to be considered and how they drive the device selection and design layout.
The merits and drawbacks of each of the parametric factors are
• How to manipulate the design layout to maximize converter performance.
discussed upon which the most optimal solution is presented.
Impact of Device Characteristics
Prior to paralleling any switching device one must first determine if they can inherently be paralleled or require special techniques to do so. Since eGaN FETs are based
on a relatively new technology, it is necessary to study every device characteristics for its effect on paralleling and hence determine its paralleling compatibility.
Most notably are (a) device selection (e.g. multiple small devices verses fewer large devices) or (b), Is there a positive or negative temperature coefficient of key characteristics such as RDS(ON) or VTH?
Device selection
eGaN FETs are available in a variety of current ratings, and choices for paralleling can range from four small devices to two large devices. In the discussion that follows,
it will become apparent that the choice to parallel eGaN FETs must not be taken lightly and furthermore it is more advantageous to keep the number of paralleled
devices to a minimum, in particular for high performance converters where timing and efficiency are important design parameters.
Temperature Effects
There are two important FET parameters to consider when analyzing temperature effects for paralleling compatibility and these are RDS(ON) and VTH. Large variations in these
parameters can have profound negative effects on the optimal operation of the converter employing paralleled FETs.
RDS(ON) temperature coefficient and variation effects
Variations in RDS(ON) can cause differences in drain current among the FETs of a switch. In extreme cases one FET may carry a significant burden of the total current while
another FET carries hardly any current. This may not be bad if the temperature rise among the FETs is uniform. If, however, the FET carrying the highest burden is operating near its operating limits it can cause more rapid degradation over time and ultimately lead to failure of the circuit. It is therefore preferable to ensure an even
distribution of current between all the FETs of the switch.
The RDS(ON) of a FET will vary with temperature. In the case of paralleling it is important that each of the FET’s RDS(ON) varies at the same rate of temperature change to ensure current balance at all operating temperatures. Deviations from this may be self-regulating if the FETs exhibit a positive increase in RDS(ON) as function of temperature
rise whereby higher temperature FETs, with higher RDS(ON), will begin to carry less current. This allows the device to cool until an equilibrium between all the paralleled
devices is reached. eGaN FETs exhibit a positive temperature coefficient for RDS(ON) which increases with temperature, thereby facilitating paralleling design.
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Paralleling eGan® FETs
VTH temperature coefficient and variation effects
Variations in VTH between FETs manifest as a time delay between the time when FETs turn ON and OFF with respect to each other. The consequences of these time
shifts are twofold: (1) they can induce inter-FET currents which can then induce voltages across common inductances and (2) they can cause a single device to carry
all the load current for a short period which, overtime, can lead to degradation or eventual failure. In extreme cases this can lead to false turn-on or turn-off triggering
with catastrophic consequences for the switch.
eGaN FETs exhibit a threshold voltage with a slightly positive temperature coefficient. If all the eGaN FETs in a switch have the same change in VTH as function of temperature, then the issue becomes part-to-part variation in the absolute value of VTH. An analysis of eGaN FETs timing variations resulting from variations VTH show that
they are extremely small when compared to the switching transient times. As an example: using a total gate rise time of 8 ns (from 0 V to 5 V) with two devices connected in parallel, one having a VTH = 1.4 V and the other VTH = 1.54 V, leads to a time shift of only 224 ps which translates into < 5% of the total drain-source switching
transition time. Despite these small timing variations, the designer must still determine the level of induced voltages across the various inter-device inductances to
determine if those voltages can cause unwanted switching behavior when induced into the gate path loop where it can exceed VTH.
Reference [5] discusses the VTH timing issue in more detail.
Paralleled eGaN® FET Circuit Considerations
There are many factors that play a role in the design and analysis of a parallel FET switch, and each will impact the optimum performance. In this section particular
attention will be given to the following design aspects:
• Layout induced circuit elements
• The impact of source inductance
• Defining switch transient immunity
• Comparing eGaN FETs and MOSFETs susceptibility to di/dt and dv/dt
• What are the relevant gate driver requirements for paralleled eGaN FETs
Layout Induced Parasitic Circuit Elements
As is the case for MOSFETs, eGaN FETs simply cannot have each of their respective terminals connected to each other to yield a good paralleled switch. To design a
paralleled eGaN FET switch that can function at near theoretical maximum performance, certain circuit changes are needed to ensure maximum performance from
each of the devices.
eGaN FETs have a lower threshold voltage (VTH) and a higher Miller capacitance
ratio than MOSFETs, making the details for parallel connection more important.
eGaN FETs also switch faster, forcing the designer to pay particular attention to
how the layout will create circuit characteristics that can affect the performance
of the switch.
A generic circuit for a half bridge converter, with details of the lower switch having two devices connected in parallel, is shown in figure 1. Two parameters need
to be controlled in the circuit that will ensure reliable operation of the switch:
(1) Source inductance, which can induce unwanted gate voltages into a device
and is dependent on the di/dt of the current flowing through the switch and, (2)
Miller capacitances which can induce a current into the gate path during switching events and is driven by the dv/dt experienced by the switch. Ironically, to design a switch that is immune to di/dt requires a high impedance gate loop, while
at the same time a low impedance in the gate loop will make the switch immune
to dv/dt induced gate currents. Figure 6 of reference [11] and the accompanying
paragraph discusses this issue in detail.
An understanding of the impact of each of these parasitic elements is needed
to overcome this design contradiction and determine, (a) the level that can be
tolerated and, (b) what can be done to mitigate the problems they may cause.
Ultimately the design comes down to how well the gate drive circuit can be isolated from the power circuit through design.
QUpperSW
Idv/dt_CDG1
LCDP2
LCDP1
Idv/dt
RG
CGD1
+
LG1
VGS1
+
+
VGate Drive
Vdi/dt
CGD2
Q1
CDS1
CGS1
LG2
Q2
CGS2
CDS2
LCSG2
LCSG1
-
LSG1
LCSP1
LSG2
LCSP2
IL_CS
Figure 1: Generic circuit of two paralleled FETs showing the location
of the parasitic inter-device inductances.
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Paralleling eGan® FETs
Detailed analysis and simulations reveal the following:
1. The source inductance, and inter-device source inductance are the most important elements in the circuit and must be kept as low as possible. Drain inductance
may be sacrificed to achieve this.
2. The gate inductance is inherently higher than the source inductance and is very difficult to keep below a ratio of 10:1. This is mainly due to the narrow width and
length of the gate drive transmission line. The point of coupling to the source inductance will play a major role in mitigating the source inductance impact on the
gate circuit.
3. The gate driver source and sink impedance can be pre-determined for full transient switching immunity by means of dv/dt reduction, however this comes at the
expense of efficiency.
4. A complete solution, including gate inductance results in a 3rd order system with both sinusoidal and exponential terms that require a numerical analysis for a
solution.
Source Inductance
Referencing figure 1, several layout-based parasitic inductances of note are shown.
These are:
1.LCSG1 and LCSG2: the common source inductance for each of the FETs respectively.
2.LSG1 and LSG2: the common source inductance in the gate circuit shared between the FETs.
3.LCSP1 and LCSP2: the inter-device common source inductance for each of the FETs respectively.
LCSGx Inductance
This inductance appears in both the power circuit and gate circuit and it is the most critical inductance in the layout circuit. For this reason every possible means must
be taken to keep this inductance as small as possible. Techniques to achieve this will be presented later in this paper.
LSGx Inductance
This inductance is common to all the FETs of the switch gate circuit. Since this inductance is isolated from the power path it is not as critical as LCSGx, however its value
should still be kept as low as possible by keeping the gate drive transmission path length as short as possible for reasons that will be presented later in this paper
LCSPx Inductance
This inductance appears in the switch power reference path (ground or switch-node in the case of a half bridge topology). This inductance can generate the highest
voltage between the FETs as the main current will flow through these inductors. It can be seen however that, with thoughtful planning of the layout, each of these
inductors can be made to the same value by careful selection of the point of coupling. Since the currents will always flow in the same direction through each of these
inductances, the induced voltage will be the same for each FET, thereby eliminating the effect of the power source (drain) on the gate circuit. There is one point of note
that must be considered for this system to work well; all the FETs must switch at the same time to maintain the balance in currents between these inductors. Variations
will induce a voltage in the gate circuit that can alter the behavior of the switch.
Switch Transient Immunity
The maximum possible switching rate for both dv/dt and di/dt, without negatively impacting the FET’s performance is defined as switch immunity. A negative impact to switch performance is loosely interpreted as any induced voltage
in the gate circuit that will cause the switch to function in the opposite mode
to the command signal. This definition applies to single FETs as well as paralleled FETs and, as such, the subsequent discussion will be simplified to that for
a single FET.
The simplified diagram for the gate circuits with the parasitic and circuit elements that can affect the dv/dt and di/dt immunity of the switch are shown in
figure 2. The dv/dt circuit simplifies to a current divider network. The di/dt circuit simplifies to a voltage divider network. The quantification of di/dt and dv/
dt immunity with resultant equations (1) and (2) for the switch can be derived
CGD
Idv/dt_DR
Idv/dt
dv/dt
ICGS
LG
RG
+
CGS
+
LG
VGS
RG
+
CGS
VGS
+
Ls
Ls
RDR
IGS
Vs = Idv/dt
RDR
Figure 2: Simplified schematics to determine dv/dt (left) and
di/dt (right) immunity.
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Paralleling eGan® FETs
by making certain simplifying assumptions. The key to successfully utilizing these equations is to identify the correct source and gate loop inductances. In the case of
figure 1 the common source inductance (Ls) will be LCSGx. However, a separate analysis may be required to determine the induced voltage resulting from the differential
current flowing between the FETs, in which case the source inductance for the equation will be the sum of LCSGx and the mutual inductance between the LCSPx’s. The gate
loop inductance (LG) for the equation will be the sum of LSGx and LGx from figure 1.
The di/dt immunity for the switch can then be determined using equation (1):
di
=
dt
Where:
VTH . 1 + RG + RDR +
LG . CGS
LG + CGS
(1)
LS
di/dt = Rate of Change in current through source inductor [A/s]
VTH = Threshold Voltage of switch [V]
RG = Gate Resistance [Ω]
RDR = Gate Driver output Resistance [Ω]
LG = Gate Inductance [H]
CGS = Gate-Source Capacitance [F]
LS = Source Inductance [H]
The dv/dt immunity for the switch can be determined using equation (2):
dv
=
dt
VTH
CGD . RG + RDR +
Where:
LG + LS
CGS
(2)
dv/dt = Rate of Change in voltage across drain-source [V/s]
CGD = Gate-Drain Capacitance [F]
Comparing eGaN® FETs and MOSFETs Susceptibility to di/dt’s and dv/dt’s
Device parameters, circuit elements and parasitic elements from layout become important when paralleling devices [3]. Considering a simplified switching circuit as
an example, and neglecting LG, the drain current will increase linearly during the entire commutation time and can be approximated by:
Where:
t ∆I =
RG + RDR . CGS + CGD
IDS
+ LS
VDR – VTH
gm
(3)
t∆I = Current commutation interval time [s]
gm = Transconductance [S]
VDR = Gate Driver voltage [V]
IDS = Drain Current [A]
eGaN FETs have lower drive voltage capability, gate resistance, and capacitances than an equivalent MOSFETs. Therefore the effect of the common source inductance
term in equation (3) becomes more pronounced. Figure 3 shows a plot of the current commutation time for varying values of common source inductance based on
the EPC2001 and an equivalent state-of-the-art MOSFET [Infineon BSC060N10N] for both turn-on and turn-off intervals (for turn-off, the term VDR – VTH is replaced by
VTH). The plot shows that the eGaN FET commutation time is significantly more affected by common source inductance than the MOSFET. For high enough values of
LS, the eGaN FET commutation time can actually exceed that of the MOSFET.
In a similar manner, the voltage commutation interval can be considered in two ways. First, determining the maximum switching time based on a given gate driver is
mathematically described by equation (4) and, second, determining the susceptibility to false turn-on resulting from a dv/dt event.
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QGD . RG + RDR–up
=
VDR – VPL
5
(4)
Where:
t∆V = Voltage commutation interval time [s]
QGD = Gate-Drain charge [C]
RDR-up = Gate Driver turn-on resistance [Ω]
VPL = Plateau voltage [V]
MOSFET turn-on
4
eGaN FET turn-off
3.5
MOSFET turn-off
3
2.5
2
1.5
1
Assume, as an example, a peak dv/dt during the voltage transition period is approximately 30% higher than the average dv/dt. The absolute minimum switching time without incurring a dv/dt induced (Miller) turn-on event, can then be
approximated by equation (5):
t ∆V immune =
eGaN FET turn-on
4.5
di/dt Commutation Time [ns]
t ∆V
Paralleling eGan® FETs
1.3VDC . RG + RDR– Down CGD
VTH
0.5
0
0
50
100
150
200
250
300
Common Source Inductance [pH]
(5)
Figure 3: Comparison of MOSFET and eGaN FET turn-on and turn-off
times as function of common source inductance.
Where:
t∆Vimmune = Voltage commutation interval time for immunity [s]
VDC = DC Bus voltage [V]
RDR-down = Gate Driver turn-off resistance [Ω]
Figure 4 shows a plot of the turn-on dv/dt commutation time as function of gate drive resistance (RG) together with the immunity limit (time before the VTH for the
FET is exceeded). This commutation time is defined as the immunity limit for the complimentary switch in a half bridge topology, and switching any faster can lead
to unwanted switching behavior. The commutation time is much higher than those predicted for immunity in the case of a MOSFET, thus providing higher inherent
dv/dt immunity. The commutation time for immunity is higher than what can be achieved in the case of the eGaN FET, hence lower values of RG for turn-off than for
turn-on are recommended.
Due to its smaller gate charge, the eGaN FET can switch faster than a MOSFET, as can be seen in the graph of figure 4. Consequently it is less sensitive to changes
in RG. Greater dv/dt immunity for the eGaN FETs is however not implied.
16
12
MOSFET turn-on
12
eGaN FET immunity
10
MOSFET immunity
8
6
4
eGaN FET immunity
MOSFET immunity
8
6
4
2
2
0
MOSFET turn-off
10
dv/dt Commutation Time [ns]
dv/dt Commutation Time [ns]
eGaN FET turn-off
eGaN FET turn-on
14
0
0.5
1
1.5
2
2.5
0
0
0.5
1
1.5
2
Gate Drive Resistance [Ω]
Gate Drive Resistance [Ω]
Figure 4: Comparison of MOSFET and eGaN FET turn-on commutation
times as function of gate resistance.
Figure 5 Comparison of MOSFET and eGaN FET turn-off commutation
times as function of gate resistance.
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Figure 5 shows a plot of the turn-off dv/dt commutation time as function of gate drive resistance (RG) together with the immunity limit (time before the VTH for the
FET is exceeded). In both the MOSFET and eGaN FET cases, the commutation time is higher (much higher for the MOSFET) than those predicted for immunity, thus
providing inherent turn-off dv/dt immunity.
The contribution of LG and RDR will increase as the gate loop gets longer and more devices are connected in parallel, having a negative impact on dv/dt immunity. This
leaves the only option to improve the immunity is to increase switching time.
Gate Driver Considerations
The gate driver is the single most important circuit connected to a FET. The gate driver functions to turn the FET on and off in a reliable manner and, as has already
been discussed, its ability to function at optimum is also at the mercy of layout. Adding paralleled FETs to this increases the complexity of the situation and requires
additional attention.
A designer has the option of providing a unique gate driver to each FET in the paralleled switch. This effectively eliminates the issue of inter-device source inductance
created by the layout. However, the disadvantages of this option are numerous and include:
• Increased cost of gate drivers for each FET. Due to the small size and relative low power rating of converters employing eGaN, this cost can become significant.
• The propagation delay and pulse width distortion between each gate driver are unique and as such the FETs of the switch will not turn-on or turn-off in unison
thereby creating the issue of temporary current unbalance between the FETs. This can be overcome by adding precise dead-timing to the circuit which, in most
cases, would require manual (and expensive) tuning. The added costs for this option also become apparent.
A single gate driver per switch is therefore the recommended as a cost effective
solution for driving paralleled FETs. The driver will need to have the output current
rating to drive the additional FETs.
The gate driver also needs to be located as close as possible to the switch to ensure
the lowest possible gate transmission line inductance, which has been shown to
be critical to optimum operation of the switch. Practical limitations include the
need to add the gate turn-on and turn-off resistors, which are of the same order of
size as the gate driver and eGaN FET. These resistors also contribute significantly to
the gate transmission line inductance and hence only one of each should be used
as shown in figure 6. It will be further demonstrated in the layout section that using unique gate resistors for each switch is not practical for layout as the total gate
inductance becomes intolerable for any reliable performance from the converter.
RGon
Driver
RGoff
Figure 6 Gate resistor sharing for each eGaN FET in the paralleled switch.
Layout Design Evaluation
Layout design is always required to be approached from two angles; (1) printed circuit board restrictions (including board populating) and (2) placement and routing
design. eGaN FETs are no exception to this requirement, but place additional requirements on the design due to their small size, compact connection structure needs,
and high demand on current and voltage ratings.
The eGaN FET Land Grid Array (LGA) package [4] is a dramatic and positive departure from traditional Power MOSFET packaging that helps drive new layout designs
with significant reduction in parasitic inductances between devices connected in parallel. These new options are critically important in achieving the best possible
solution to paralleling the devices, given that the eGaN FETs switch very rapidly and have a lower gate threshold voltage than MOSFETs. Designers still need to pay
careful attention to the layout of a converter design despite the advantages provided by the eGaN package and device.
To address the many questions on layout using eGaN FETs, EPC developed five half bridge topology layout designs with up to four FETs per switch connected in parallel
and which is shown in figure 7. Figure 8 shows a block diagram of the test setup that was used to evaluate the effectiveness of each of the design layouts.
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Paralleling eGan® FETs
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Gate Signal
Trace Path
Design B
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Qupper
+
Logic
Circuits
Physical Direction of
Switch Node Current
Design C
Single Component Side Designs
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Lower Switch
Devices (blue)
Design A
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De-Coupling
Capacitor
XXXX
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YYYY
Upper Switch
Devices (red)
Design D
Gate
Driver
DUT
Reconfigurable
Output Filter
Qlower
Design E
Double Component Side Designs
Figure 8: Block diagram of the parallel evaluation test
board for each of the layout designs.
Figure 7: Layout designs that were tested for effectiveness.
The key differences between each of the designs are summarized in table 1. The definitions of the gate structures used in table 1 are shown in figure 9.
Single/ Double Component Sided
Drain/ Source Inductance
Methodology
Output Current Exit
Gate Signal Feed in Structure
Design A
Design B
Design C
Design D
Design E
Single
Long/Narrow
(very low supply
inductance)
Device Lengthwise
Y-T
Single
Square
Double
Double
Double
Square
Short/Narrow
Short/Narrow
Device Lengthwise
I
Device Lengthwise
X
Device Widthwise
X
inductance)
Device Lengthwise
I
Table 1: Key attributes of each of the five designs evaluated in the layout analysis.
Gate Connection Structures
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I Structure
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x
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coupling
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Point of common
coupling
X Structure
Figure 9: Various gate connection structures used in the evaluation designs.
Figure 7: Various gate connection structures used in the evaluation designs
Analysis and measurements of the five designs yield gate and source inductance values that are given in the table 2.
Gate Inductance
[nH]
Source Inductance
[pH]
Design A
Design B
Design C
Design D
Design E
8.5*
4.2
4100†
610
4.4
4.9
3.1
3.6
410
430
690
690
* Larger value is inductance between device pairs, smaller value is total inductance as seen by the gate driver.
† Larger value is inductance between device pairs, smaller value is inductance between a pair set.
Table 2: Gate and source inductances of each of the five layout designs evaluated.
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Paralleling eGan® FETs
Paralleled FET Switch di/dt Immunity Evaluation
The di/dt limits of switch operation for each of the designs can now be used to determine the inductance values. These inductance results can then be used to determine which design yields the best possible configuration for paralleling eGaN FETs. The number of paralleled FETs for a design can subsequently be varied from one
through four to determine the impact of the number of devices on the effectiveness of each layout.
The inter-device common source inductance is shared by the gate loop and can cause voltages to be induced that can lead to undesired turn-on or turn-off of the
switch. Equation (1) can give the magnitude of induced voltage into the gate circuit by the common source inductance during a di/dt event. The di/dt limit for a particular design can be determined by setting the limit of induced voltage as the gate threshold voltage (VTH) (In the case of the EPC2001 device this limit is typically 1.4
V [4]).
Table 3 gives the calculated di/dt limits for each of the evaluated designs for four paralleled FETs using the inductance values from table 2 and the typical threshold
voltage (VTH).
di/dt limit [A/ns]
Design A
Design B
Design C
Design D
Design E
0.9
8.8
8.5
5.3
5.3
Table 3: Calculated di/dt limits for each of the five design examples.
Based on the results from table 3, it can be seen that the di/dt immunity of design A is far inferior to any of the other designs. This design was included in the discussion
to emphasize the incorrect method to parallel eGaN FETs and is a method that may otherwise seem attractive because it produces a very low supply loop decoupling
inductance.
Paralleled FET Switch dv/dt Immunity Evaluation
A current can be induced into the gate circuit, via the gate-drain Miller capacitance (CGD), during a rapid voltage transition (dv/dt event) across the drain source. This
typically occurs when the switch is turned OFF, and the opposite switch in a half bridge topology, is turned ON.
To ensure that the gates of the devices in the switch remain off during a dv/dt event, the gate circuit requires a low impedance that includes the gate driver. Referring
to figure 1 and figure 2 it can be seen that there are several elements in the gate circuit that include:
• Turn-off resistance (RGoff )
• Gate circuit inductance (LG)
• Common source inductance (LS)
• Gate-source capacitance (CGS)
• Gate-drain capacitance (CGD)
• Gate driver off-state resistance (RDR) (embedded in Vgatedrive)
The inductances and resistance are connected in series in the gate circuit and appear across the gate-source. The potentially corrupting current is introduced into the
gate circuit by the switch Miller capacitance, CGD, and the impedance of the inductor and resistor elements in the gate circuit will determine the voltage rise across the
gate. Analysis of the operation of this circuit is further complicated due to CGD being nonlinear with respect to drain voltage and as such a fixed value of 60 pF is used
for simplification. The following values of resistances were used for the evaluation boards: RDR = 100 mΩ and RGoff =1 Ω. The gate transmission line trace resistance is
considered negligible with respect to the gate driver and gate turn-off resistances because the trace will be kept very short.
The circuit reduces to the series combination of the resistances (RG + RDR) and inductances (LG + LS) across CGS. The induced current will divide between CGS
and the resistance-inductance circuit. The solution for dv/dt immunity circuit can be complex to solve as some solutions have oscillatory and exponential components. It is sufficient to say that the resistances (Rg + RDR) and inductances (LG + LS) should be kept as low as possible to ensure maximum possible
dv/dt immunity. The resistances (RG + RDR) for all the evaluated designs were kept the same and it can therefore be concluded that the level of immunity becomes
inversely proportional to the inductances (LG + LS).
Table 4.4 gives the calculated dv/dt limits of each of the evaluated designs for four paralleled FETs using the inductance values from table 4.2 and the typical threshold
voltage (VTH).
dv/dt limit [V/ns ]
Design A
Design B
Design C
Design D
Design E
2.2
2.6
2.5
2.7
2.7
Table 4: Calculated dv/dt limits for each of the five design examples.
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Parallel Impact Figure (PIF): A Quantitative Analysis of Paralleling Effectiveness
A converter’s performance when employing parallel FETs, can be quantitatively compared by creating a meaningful switching Parallel Impact Figure (PIF). By definition, the PIF will encompass switching capability. Omitted are the additional RDS(ON) and thermal benefits that come from distributing heat loads on the PCB. The dv/
dt and di/dt immunity have been shown as key performance contributors for predicting paralleled FET converter performance, and therefore it is logical to include
these quantities into the definition of PIF. Furthermore, the definition of PIF enables comparison between the paralleled FET converter performance with that of a
single switch equivalent. The PIF provides an indication of the limits within which the converter will function within the switch’s immunity limits when using paralleled
devices compared to a single FET equivalent.
The definition of PIF is given by the following equation:
dv 1 di1
+
dt
PIFn = dt
dvn di n
+
dt
dt
(6)
Where:
dvn/dt = dv/dt immunity for n number of devices connected in parallel [V/s]
din/dt = di/dt immunity for n number of devices connected in parallel [A/s]
dv1/dt = dv/dt immunity for a single device version of the converter [V/s]
di1/dt = di/dt immunity for a single device version of the converter [A/s]
n = Number of devices connected in parallel per switch
Parallel Board Layout Comparison
PIF
9.0
The PIF can be interpreted as a switching power loss multiplication factor of
a paralleled FET converter with respect to a single FET equivalent.
8.0
2 Devices in Parallel
Figure 10 shows a graph of normalized PIF for each of the evaluation designs using two and four paralleled FETs, calculated using equation (6) and
normalizing to a single FET equivalent design.
7.0
4 Devices in Parallel
From the PIF results shown in figure 10 it is clear that the two-FET design B
is the best, and that the four-FET design A is the worst. Design B can now be
studied in more detail to determine how the number of paralleled devices
will affect converter performance. Figure 11 shows the variations of layout
for design B with varying number of FETs connected in parallel.
4.0
6.0
5.0
3.0
2.0
1.0
0.0
Table 5 gives the inductance values and immunity limits for the designs
shown in figure 11. Figure 12 shows a graph of PIF for design B as function of
the number of FETs connected in parallel, normalized to a single FET equivalent design, including variations on the two paralleled FET layout.
A
B
D
C
E
Board Layout Design
Figure 10: Switching PIF comparison between the layout variations using two
and four FETs connected in parallel. A single device would have a PIF of 1.0.
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Board B Paralleling Comparison
B4
Figure 11: Layout options for Design B with varying number of FETs connected in parallel.
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Paralleling eGan® FETs
Single Device
2 Devices (tall)
2 Devices (long)
3 Devices
4 Devices
4.4
210
16.4
7.0
4.4
190
19.1
4.3
4.4
630
5.7
4.2
4.4
410
8.7
3.2
4.4
410
8.8
2.6
Gate Inductance [nH]
Source Inductance [pH]
di/dt limit [A/ns]
dv/dt limit [V/ns ]
Table 5: Calculated inductance and immunity limits for the variations shown in figure 11.
Board Layout Design B
PIF
2.5
2.0
1.5
1.0
0.5
0.0
B1
B2tall
B2long
B3
B4
Number of Devices in Parallel
Figure 12: PIF performance for design B with varying number of FETs connected in parallel.
Practical Layout Considerations
In the design of any layout for a circuit we need to consider what can practically be achieved. In the case of eGaN FETs, and due to their small size, we need to look at
the selection of component sizes and compare that against the critical aspects of the circuit to determine a solution that can be realized.
Separate or combined gate resistors?
When paralleling eGaN FETs for example, a designer might be tempted to select a separate gate resistor for each FET, as is traditional for MOSFETs. Doing
so, however, may increase the inductance (LG) in the gate loop so much as to
yield a solution with a very low immunity to dv/dt and di/dt transients. Figure
13 shows the size relationship of the EPC2001 against two 0603 size gate resistors in a parallel design. From the figure can be seen that adding additional
resistors to satisfy the individual resistors per gate is not practical given the size
constraints.
Turn-Off
Turn-On Resistor
Resistor
Gate
eGaN
FET
Gate
Return
eGaN
FET
Layer Assignment
As has already been discussed, the most important aspect for the layout design
of parallel connected eGaN FETs is to keep the various parasitic inductances to
a minimum that will ensure the most optimal solution. Single and double-layer
PCB designs are therefore effectively ruled out as options, and designers need
to focus on four or more PCB layers in their designs.
Signal and power layer assignment in design is a very important aspect of the layout, and is an effective way to provide E-field and H-field
shielding to the finished design. It is important to shield gate signals
from the very high dv/dt of the drain. There is also the practical side to design that can counter the best solution. As an example, consider a single
component sided (eGaN FET is mounted to one side of the board only).
In this case the ideal layer assignment is shown in figure 14. Although
Turn-Off
Resistor
eGaN
FET
Turn-On
Resistor
eGaN
FET
Figure 13 Example of gate resistance and eGaN FET size comparison.
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the gate is well shielded from the drain layers, the decoupling capacitor must be placed on the same side of the board as the eGaN FETs. The inductance of the connection to this decoupling capacitor may be larger than that of a more practical solution given in figure 15 where the decoupling capacitor is placed on the bottom side of the PCB. The gate signal of the bottom device, however, is now capacitively coupled to the drain. To reduce the
capacitance in the layout design between the gate signal and drain plane, the designer can separate them spatially in opposite directions as shown in figure 16.
Upper Switch on
top side
Layer 1
Supply Decoupling
Capacitor
Lower Switch on
top side
Supply Negative
(Source)
Supply Positive
(Drain)
Layer 2
Output/Gate Return
(Source)
Layer 3 Gate
Layer 4
Gate
Output
(Source)
Supply Negative/
Gate Return (Source)
Output
(Drain)
Figure 14: Ideal layer assignment for a 4-layer PCB having eGaN FETs mounted on the top side only.
Upper Switch on
top side
Layer 1
Lower Switch on
top side
Gate
Output
(Drain)
Gate
Output
(Source)
Supply Negative
(Source)
Output
(Source)
Layer 2
Layer 3
Supply Positive
(Drain)
Layer 4
Supply Positive
(Drain)
Output
(Drain)
Supply Negative
(Source)
Supply Decoupling
Capacitor
Figure 15: Practical layer assignment for a 4 layer PCB having eGaN FETs mounted on the top side only.
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Drain trace direction
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Figure
16: Gate
drain
decoupling on
layerlayer
by spatial
separation.
Figure 4.16
Gate
andand
drain
decoupling
ona single
a single
by spatial
separation
Double-Sided eGaN® FET Mounting Layout Considerations
There may be circumstances where a converter needs to use many FETs connected in parallel such that both sides of the PCB need to be populated to meet the design
requirements. One approach would be to simply double up the four-layer design assignment in the reverse order to form an eight-layer design. Furthermore, an upper
assigned switch should be located in the same area on both sides on the board. It may be tempting to place all the upper switches on the top side of the board and
all the lower switches on the bottom side. This will, however, create a layout that is difficult to route, and will require vias that create “Swiss cheese” of power planes
needed to carry high currents.
Figure 17 shows the suggested layout for a high-count parallel FET design. The decoupling capacitors need to be located next to the FET cluster. Despite having eight
FETs connected in parallel, the layout is still able to group all the gates very tightly for absolute minimum inter-FET inductance.
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Paralleling eGan® FETs
Via Considerations
°
°
°
°
°
°
Decoupling Capacitors
Figure 17: Suggested high FET count layout with FETs mounted on both
sides of the board.
Decoupling Output Current by Design
Staggered Vias
Another technique to further decouple induced voltage into the gate circuit
is to design the layout in such a manner that the output power circuit lies orthogonal to inter-device circuit. This effectively separates the common source
inductance from the inter-device source inductance. Figure 19 shows an example of this technique where the output current flows orthogonally to the
direction of the inductance circuit between the parallel connected FETs.
eGaN
FET
Vias on both
sides of the
FET. Current
exits pad in two
directions
Summary of Design Guidelines for Paralleling eGaN® FETs
Summarizing the design guidelines based on experimental results and lessons learned, a set of general design rules is given below:
1. Keep the source inductance between devices as low as possible in the
design. This can be achieved by short wide trace structures. This inductance should not be confused with the common source inductance for a
single device.
Direction of
Output
Current
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°
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°
Lower
Switch FETs
Point of common
coupling for gates
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To prevent unzipping the PCB, vias are recommended to be staggered as
shown in figure 18. Alternatively for an added cost, the PCB manufacturer can
be requested to rotate PCB such that the fiber grain will be at an angle of 45°
with respect to the edge of the board.
To ensure that the current can flow in two directions from the device into the
PCB, vias are placed on both sides of the device as shown in figure 18. This
helps reduce the inductance of the connection.
°
Upper
Switch FETs
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X structure for gate
connections
The location, type and size of vias used in a layout design are important for
achieving the best design solution. The choice of vias will ultimately dictate
the overall dimensions of the switch circuit layout, and following the via dimensions presented in reference 12 (page 38-39) for dual-sided terminations
is recommended. When using the low voltage LGA package of the EPC eGaN
devices, vias with a 6 mil (150 µm) hole and an 8 mil (200 µm) annular ring are
generally used. This size is the limit for most PCB manufacturers tolerances
when using 2-ounce thick copper.
eGaN
FET
Figure 18: Use of staggering of vias and on both sides of the FET.
2. Keep all the gate connections very tight with respect to each other. The
smaller the “open” distance between gate connections, the smaller the
common source inductance.
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Inter-device
Inductance
Current
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°
4. Drain inductance may be increased with respect to source inductance.
Drain inductance may aid in keeping the system stable over a wider
range of operating conditions. Too much inductance is also detrimental. Physically this means that a group of switches may be spread apart
slightly when designing the layout to make room for vias.
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3. Keep the gate-source impedance as low as possible and, in particular,
the inductance. This is difficult to achieve since the gate connections are
typically long narrow traces. Since trace width is generally constrained,
the design must keep the gate trace as short as possible from the exit
point of the gate driver.
Output
Current
Direction
5. Reduce the dv/dt of the switching event by increasing the gate driver
source resistance. This will help damp out oscillations that can occur in
the gate loop which otherwise can lead to exceeding the maximum allowed gate voltage.
6. Add gate turn-off resistance to help damp the gate circuit. As in the case
for the turn-on, the turn-off may oscillate during a switching event. In
the case for turn-off, the gate can ring negative or positive. A positive
ringing can lead to unwanted turn-on of the switch.
Figure 19: Example of applying the orthogonal principle to decouple the
common source inductance from the inter-device inductance.
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Paralleling eGan® FETs
Summary
Can eGaN FETs be connected in parallel? The simple answer is yes. However, due to the higher switching speed capability of eGaN FETs, source inductance and gate
inductance are more important than for MOSFETs. Paralleling eGaN FETs may require adjustment to the gate circuit to reduce the switching speed and ensure operation within the immunity limits of the device. Adjustment to the switching speed can be achieved by changing the values of the turn-on and turn-off resistances in
the gate driver.
With an increasing number of devices connected in parallel, the performance of the fast switching eGaN FETs become less relevant compared to the impact of layout.
In this paper a switching Parallel Impact Factor (PIF) was defined to quantify the predicted converter performance based on the number of FETs connected in parallel
with respect to a single FET equivalent. Most of the reduction in performance comes from the reduction in switching speed with increasing number of parallel FETs.
This reduction in switching speed tends to increase switching losses in the converter, thus reducing the benefits of paralleling the FETs. For the specific case of two
paralleled eGaN FETs, designs can avoid a performance penalty with respect to a single FET equivalent. With more than two devices in parallel, increased switching
losses are to be expected.
References:
[1] Jonathan Dodge, “Eliminating Parasitic Oscillation between Parallel MOSFETs”, Advanced Power Technology Application note APT-0402 Rev A, March 25, 2004
[2] James B. Forsythe , “Paralleling Of Power MOSFETs For Higher Power Output”
[3] Yuancheng Ren, Ming Xu, Jinghai Zhou and Fred C. Lee, IEEE , “Analytical Loss Model of Power MOSFET” , Transactions on Power Electronics Vol.21 No.2 March 2006
[4] “EPC2001 – Enhancement Mode Power Transistor”, Efficient Power Conversion datasheet for EPC2001
[5] Myzafere Limani, Qamil Kabashi, Nebi Caka, Milaim Zabeli, “Impact of rise time driving signal and mismatch threshold voltage MOSFET’s in parallel connection of Push-Pull Power Inverter”, International Journal of Circuits, Systems and Signal Processing, Issue 1, Volume 5, 2011
[6] Helge Granberg, “Get 600 Watts RF from Four Power FETs”, Motorola Semiconductor Engineering bulletin EB104/D
[7] Jingdong Chen, Scott Downer and Anthony Murray and David Divins, “Analysis of Avalanche Behaviour for Paralleled MOSFETs”, SAE World Congress 2004
[8] “Parallel Operation Of Semiconductor Switches”, Fairchild Semiconductor Application note AN-7513
[9] “Paralleling HEXFET® Power MOSFETs”, International Rectifier Application Note AN-941
[10] Janis M. Niedra, “Paralleling Power MOSFETs in Their Active Region: Extended Range of Passively Forced Current Sharing”, NASA Contractor Report 180902, July 1989
[11] Johan Strydom, The eGaN® FET-Silicon Power Shoot-Out: 2: Drivers, Layout”, Power Electronics Technology, January 2010, pp 14-19
[12] “GaN Transistors for Efficient Power Conversion”, Alex Lidow, Johan Strydom, Michael deRooij, and Yanping Ma, Power Conversion Publications, 2011
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