SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
D Low Output Skew for Clock-Distribution
D
D
D
D
D
D
D
D PACKAGE
(TOP VIEW)
and Clock-Generation Applications
TTL-Compatible Inputs and Outputs
Distributes One Clock Input to Six Clock
Outputs
Polarity Control Selects True or
Complementary Outputs
Distributed VCC and GND Pins Reduce
Switching Noise
High-Drive Outputs (−48-mA IOH,
48-mA IOL)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Packaged in Plastic Small-Outline Package
GND
1Y2
1Y3
GND
2Y1
2Y2
GND
3Y1
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1Y1
1T/C
VCC
2T/C
A
VCC
3T/C
OE
description
The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and
complementary outputs can be obtained. The output-enable (OE) input is provided to disable the outputs to a
high-impedance state.
The CDC391 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
INPUTS
OE
T/C
A
OUTPUT
Y
H
X
X
Z
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
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•
1
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
logic symbol†
9
OE
EN
1
12
A
15
1T/C
13
2T/C
10
3T/C
1
1
N1
N2
2
N3
2
3
16
1Y1
2
1Y2
3
1Y3
5
2Y1
6
2Y2
8
3Y1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
1T/C
9
15
16
1Y1
2
1Y2
3
A
1Y3
12
5
2Y1
13
2T/C
3T/C
2
6
10
8
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•
2Y2
3Y1
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.77 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
−48
Low-level output current
48
mA
∆t / ∆v
Input transition rise or fall rate
5
ns / V
fclock
TA
Input clock frequency
100
MHz
85
°C
High-level input voltage
2
V
0.8
Input voltage
0
Operating free-air temperature
−40
V
V
mA
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP‡
MAX
UNIT
−1.2
V
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = −18 mA
IOH = − 48 mA
VOL
II
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 48 mA
VI = VCC or GND
0.5
V
±1
µA
IOZ
IO§
VCC = 5.25 V,
VCC = 5.25 V,
VO = VCC or GND
VO = 2.5 V
± 50
µA
−100
mA
ICC
Ci
Co
VCC = 5.25 V,
VI = VCC or GND
IO = 0,
2
V
−15
Outputs high
10
Outputs low
40
Outputs disabled
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
mA
10
3
pF
5
pF
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
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3
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Any Y
tPLH
tPHL
T/C
Any Y
tPZH
tPZL
OE
Any Y
tPHZ
tPLZ
OE
Any Y
tsk(o)
A
tsk(p)
A
MAX
1.5
5
1.5
5
1.5
5
1.5
5
1.5
5
3
7
UNIT
ns
ns
ns
5
Any Y (same phase)
•
ns
0.5
ns
1
Any Y
1
ns
1.5
ns
1.5
ns
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•
5
Any Y (any phase)
tr
tf
4
MIN
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
GND
CL = 50 pF
(see Note A)
500 Ω
3V
Output
Control
(low-level
enabling)
LOAD CIRCUIT FOR OUTPUTS
1.5 V
3V
Input
1.5 V
1.5 V
tPLH
tPHL
2V
0.8 V
tr
1.5 V
VOH
2V
0.8 V
Output
Waveform 2
S1 at Open
(see Note B)
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
0V
1.5 V
0V
tPZL
Output
S1
Open
7V
Open
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH
VOH − 0.3 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
A
1T/C
1Y1
tPLH1
tPHL1
tPLH5
tPHL5
tPLH2
tPHL2
tPLH6
tPHL6
tPLH3
tPHL3
tPHL7
tPLH7
tPLH4
tPHL4
tPHL8
tPLH8
1Y2
2T/C
2Y1
2Y2
NOTES: A. Output skew, tsk(o), from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control
inputs (T/C) are at the same logic level. It is calculated as the greater of:
− The difference between the fastest and slowest of tPLH from A↑ to any Y (e.g., tPLHn, n = 1 to 4; or tPLHn, n = 5 to 6)
− The difference between the fastest and slowest of tPHL from A↓ to any Y (e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6)
− The difference between the fastest and slowest of tPLH from A↓ to any Y (e.g., tPLHn, n = 7 to 8)
− The difference between the fastest and slowest of tPHL from A↑ to any Y (e.g., tPHLn, n = 7 to 8)
B. Output skew, tsk(o), from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs
(T/C) are at the same or different logic levels. It is calculated as the greater of:
− The difference between the fastest and slowest of tPLH from A↑ to any Y or tPHL from A↑ to any Y (e.g., tPLHn, n = 1 to 4;
or tPLHn, n = 5 to 6, and tPHLn, n = 7 to 8)
− The difference between the fastest and slowest of tPHL from A↓ to any Y or tPLH from A↓ to any Y (e.g., tPHLn, n = 1 to 4;
or tPHLn, n = 5 to 6, and tPLHn, n = 7 to 8)
Figure 2. Waveforms for Calculation of tsk(o)
6
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