SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
D
D
D
D
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
Bidirectional Transceivers
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.11 and X.27
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
3-State Driver and Receiver Outputs
Individual Driver and Receiver Enables
Wide Positive and Negative Input/Output
Bus Voltage Ranges
Driver Output Capability . . . ± 60 mA Max
Thermal Shutdown Protection
Driver Positive and Negative Current
Limiting
Receiver Input Impedance . . . 12 kΩ Min
Receiver Input Sensitivity . . . ± 200 mV
Receiver Input Hysteresis . . . 50 mV Typ
Operate From Single 5-V Supply
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
description
The SN65176B and SN75176B differential bus transceivers are monolithic integrated circuits designed for
bidirectional data communication on multipoint bus transmission lines. They are designed for balanced
transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations
V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ,
an input sensitivity of ± 200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B is characterized for operation from – 40°C to 105°C and the SN75176B is characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
Function Tables
DRIVER
OUTPUTS
INPUT
D
ENABLE
DE
H
H
H
L
L
H
L
H
X
L
Z
Z
A
B
RECEIVER
DIFFERENTIAL INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
– 0.2 V < VID < 0.2 V
L
H
L
?
VID ≤ – 0.2 V
X
L
L
H
Z
Open
L
?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic symbol†
DE
RE
D
3
2
logic diagram (positive logic)
DE
EN1
D
EN2
1
4
1
R
1
6
7
RE
A
B
R
3
4
2
1
2
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
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6
7
A
B
Bus
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC
VCC
VCC
85 Ω
NOM
R(eq)
16.8 kΩ
NOM
Input
960 Ω
NOM
960 Ω
NOM
Output
GND
Driver input: R(eq) = 3 kΩ NOM
Enable inputs: R(eq )= 8 kΩ NOM
R(eq) = equivalent resistor
Input/Output
Port
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10 V to 15 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage, VCC
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
12
Voltage at any bus terminal (separately or common mode),
mode) VI or VIC
–7
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
2
Driver
High level output current,
High-level
current IOH
Receiver
Driver
Low level output current,
Low-level
current IOL
V
0.8
Differential input voltage, VID (see Note 3)
V
± 12
V
– 60
mA
– 400
µA
60
Receiver
free air temperature,
temperature TA
Operating free-air
V
8
SN65176B
– 40
105
SN75176B
0
70
mA
°C
NOTE 3: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
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3
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS†
PARAMETER
VIK
VO
Input clamp voltage
Output voltage
II = – 18 mA
IO = 0
|VOD1|
Differential output voltage
IO = 0
|VOD2|
g
Differential output voltage
VOD3
Differential output voltage
∆|VOD|
Change
g in magnitude
g
of differential output
voltage§
VOC
Common mode output voltage
Common-mode
∆|VOC|
Change
g in magnitude
g
of common-mode
output voltage§
IO
Output current
IIH
IIL
High-level input current
IOS
ICC
Low-level input current
Short circuit output current
Short-circuit
Supply current (total package)
MIN
TYP‡
MAX
UNIT
– 1.5
V
6
V
6
V
0
1.5
RL = 100 Ω,
See Figure 1
RL = 54 Ω,
See Figure 1
See Note 4
3.6
1/2 VOD1
or 2¶
1.5
V
2.5
1.5
RL = 54 Ω or 100 Ω
Ω,
Output disabled,,
See Note 5
See Figure 1
VO = 12 V
VO = – 7 V
5
V
5
V
± 0.2
02
V
+3
–1
V
± 0.2
02
V
1
– 0.8
VI = 2.4 V
VI = 0.4 V
mA
20
µA
– 400
µA
VO = – 7 V
VO = 0
– 250
VO = VCC
VO = 12 V
250
150
mA
250
No load
Outputs enabled
42
70
Outputs disabled
26
35
mA
† The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡ All typical values are at VCC = 5 V and TA = 25°C.
§ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
¶ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTES: 4. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
5. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.
switching characteristics, VCC = 5 V, RL = 110 kΩ, TA = 25°C (unless otherwise noted)
PARAMETER
TYP
MAX
15
22
ns
20
30
ns
See Figure 4
85
120
ns
See Figure 5
40
60
ns
Output disable time from high level
See Figure 4
150
250
ns
Output disable time from low level
See Figure 5
20
30
ns
td(OD)
tt(OD)
Differential-output delay time
tPZH
tPZL
Output enable time to high level
Output enable time to low level
tPHZ
tPLZ
4
Differential-output transition time
TEST CONDITIONS
RL = 54 Ω
Ω,
POST OFFICE BOX 655303
See Figure 3
• DALLAS, TEXAS 75265
MIN
UNIT
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER
TIA/EIA-422-B
TIA/EIA-485-A
VO
|VOD1|
Voa, Vob
Vo
Voa, Vob
Vo
|VOD2|
Vt (RL = 100 Ω)
Vt (RL = 54 Ω)
(
Vt (Test
Termination
Measurement 2)
|VOD3|
∆|VOD|
| |Vt| – |Vt| |
| |Vt – |Vt| |
VOC
∆|VOC|
|Vos|
|Vos – Vos|
|Vos|
|Vos – Vos|
IOS
IO
|Isa|, |Isb|
|Ixa|, |Ixb|
Iia, Iib
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT +
VIT –
Positive-going input threshold voltage
Vhys
VIK
Input hysteresis voltage (VIT + – VIT –)
Enable Input clamp voltage
II = – 18 mA
VOH
High level output voltage
High-level
VID = 200 mV,,
See Figure 2
IOH = – 400 µ
µA,,
VOL
Low level output voltage
Low-level
VID = – 200 mV,,
See Figure 2
IOL = 8 mA,,
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
II
Line input current
Other input = 0 V,,
See Note 6
IIH
IIL
High-level enable input current
Low-level enable input current
VIH = 2.7 V
VIL = 0.4 V
rI
Input resistance
VI = 12 V
IOS
Short-circuit output current
ICC
Negative-going input threshold voltage
Supply current (total package)
VO = 2.7 V,
VO = 0.5 V,
IO = – 0.4 mA
IO = 8 mA
MIN
TYP†
MAX
0.2
– 0.2‡
V
V
50
mV
– 1.5
27
2.7
V
V
VI = 12 V
VI = – 7 V
0 45
0.45
V
± 20
µA
1
– 0.8
mA
20
µA
– 100
12
µA
kΩ
– 15
No load
UNIT
– 85
Outputs enabled
42
55
Outputs disabled
26
35
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 6: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.
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5
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low- to high-level output
tPZH
tPZL
Output enable time to high level
tPHZ
tPLZ
Output disable time from high level
MIN
TYP
MAX
21
35
ns
23
35
ns
10
20
ns
12
20
ns
20
35
ns
17
25
ns
VID = 0 to 3 V
V, See Figure 6
Propagation delay time, high- to low-level output
See Figure 7
Output enable time to low level
See Figure 7
Output disable time from low level
UNIT
PARAMETER MEASUREMENT INFORMATION
VID
RL
VOD2
VOH
2
RL
2
VOL
VOC
+IOL
– IOH
Figure 2. Receiver VOH and VOL
Figure 1. Driver VOD and VOC
3V
Input
Generator
(see Note B)
RL = 54 Ω
50 Ω
0V
td(OD)
td(OD)
Output
Output
3V
1.5 V
1.5 V
CL = 50 pF
(see Note A)
50%
10%
tt(OD)
90%
≈ 2.5 V
50%
10%
≈ – 2.5 V
tt(OD)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 3. Driver Test Circuit and Voltage Waveforms
6
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SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
Output
3V
S1
Input
1.5 V
1.5 V
0 V or 3 V
Generator
(see Note B)
0V
RL = 110 Ω
CL = 50 pF
(see Note A)
50 Ω
0.5 V
tPZH
VOH
Output
2.3 V
tPHZ
TEST CIRCUIT
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 4. Driver Test Circuit and Voltage Waveforms
5V
3V
Input
RL = 110 Ω
S1
1.5 V
0V
Output
3 V or 0 V
Generator
(see Note B)
1.5 V
tPZL
tPLZ
CL = 50 pF
(see Note A)
50 Ω
5V
0.5 V
2.3 V
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 5. Driver Test Circuit and Voltage Waveforms
3V
Generator
(see Note B)
Output
51 Ω
Input
1.5 V
1.5 V
0V
1.5 V
CL = 15 pF
(see Note A)
0V
tPLH
tPHL
VOH
Output
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 6. Receiver Test Circuit and Voltage Waveforms
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7
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
2 kΩ
–1.5 V
S2
5V
CL = 15 pF
(see Note A)
Generator
(see Note B)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
3V
Input
3V
Input
1.5 V
0V
tPZH
1.5 V
S1 to 1.5 V
S2 Open
S3 Closed
0V
tPZL
S1 to –1.5 V
S2 Closed
S3 Open
VOH
≈ 4.5 V
1.5 V
Output
Output
0V
1.5 V
VOL
3V
Input
3V
S1 to 1.5 V
S2 Closed
S3 Closed
1.5 V
Input
S1 to – 1.5 V
S2 Closed
S3 Closed
1.5 V
0V
0V
tPHZ
tPLZ
0.5 V
≈ 1.3 V
VOH
Output
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 7. Receiver Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
VCC = 5 V
TA = 25°C
4
3.5
3
2.5
2
1.5
1
4
3.5
3
2.5
2
1.5
1
0.5
0.5
0
VCC = 5 V
TA = 25°C
4.5
VOL – Low-Level Output Voltage – V
4.5
0
– 20
– 40
– 60
– 80
– 100
IOH – High-Level Output Current – mA
0
– 120
0
20
40
60
80
100
IOL – Low-Level Output Current – mA
Figure 8
120
Figure 9
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
VOD – Differential Output Voltage – V
VOD
VOH – High-Level Output Voltage – V
VOH
5
VCC = 5 V
TA = 25°C
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30 40 50 60 70 80
IO – Output Current – mA
90 100
Figure 10
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SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE†
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
5
VOH – High-Level Output Voltage – V
VOH
VID = 0.2 V
TA = 25°C
4.5
VOH – High-Level Output Voltage – V
VOH
VCC = 5 V
VID = 200 mV
IOH = – 440 µA
4.5
4
3.5
3
2.5
VCC = 5.25 V
2
VCC = 5 V
1.5
VCC = 4.75 V
1
4
3.5
3
2.5
2
1.5
1
0.5
0.5
0
– 40
– 20
0
0
0
– 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40 – 45 – 50
Figure 11
100
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.5
0.4
0.3
0.2
0.1
5
120
0.6
VOL – Low-Level Output Voltage – V
VOL
VOL – Low-Level Output Voltage – V
VOL
80
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0
10
15
20
25
30
0.5
VCC = 5 V
VID = – 200 mV
IOL = 8 mA
0.4
0.3
0.2
0.1
0
– 40
– 20
0
20
40
Figure 13
Figure 14
POST OFFICE BOX 655303
60
80
TA – Free-Air Temperature – °C
IOL – Low-Level Output Current – mA
10
60
Figure 12
VCC = 5 V
TA = 25°C
0
40
† Only the 0°C to 70°C portion of the curve applies to the
SN75176B.
IOH – High-Level Output Current – mA
0.6
20
TA – Free-Air Temperature – °C
• DALLAS, TEXAS 75265
100
120
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
6
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5 V
3
5
VCC = 5.25 V
VO – Output Voltage – V
VO
VO – Output Voltage – V
VO
4
VID = – 0.2 V
Load = 1 kΩ to VCC
TA = 25°C
VCC = 5.25 V
VCC = 4.75 V
2
1
VCC = 4.75 V
VCC = 5 V
4
3
2
1
0
0
0
0.5
1
1.5
2
2.5
0
3
0.5
1
1.5
2
2.5
3
VI – Enable Voltage – V
VI – Enable Voltage – V
Figure 15
Figure 16
APPLICATION INFORMATION
SN65176B
SN75176B
SN65176B
SN75176B
RT
RT
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 17. Typical Application Circuit
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11
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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