Description:
The NTE3093 coupler uses a light emitting diode (LED) and an integrated high gain photon detector to provide 3000V DC electrical insulation, 500V/
µ s common mode transient immunity and extremely high current transfer ratio between inut and output. Separate pins for the photodiode and output stage result in TTL compatible saturation voltages and high speed operation. Where desired, the V
CC
and
V
O
terminals may be tied together to achieve conventional photodarlington operation. A base access terminal allows a gain bandwidth adjustment to be made.
Features:
D High Current Transfer Ratio
D
Low Input Current Requirement
D TTL Compatible Output
D 3000V DC Withstand Test Voltage
D High Common Mode Rejection
D Base Access Allows Gain Bandwidth Adjustment
D High Output Current
D DC to 1Mbit/s Operation
Absolute Maximum Ratings: (T
A
Input Diode
= +25
°
C unless otherwise specified)
Reverse Voltage, V
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Current (50% Duty Cycle,1ms Pulse Width), I
F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Transient Current (
≤
1
µ s Pulse Width, 300pps), I
F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V
40mA
20mA
Power Dissipation, P
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Linearly Above 50
°
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35mW
0.7mW/
°
C
Output Transistor
Current (Pin6), I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Linearly Above 25
°
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60mA
0.7mA/
°
C
Emitter–Base Reverse Voltage (Pin5–7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Supply Voltage (Pin8–5), V
Output Voltage (Pin6–5), V
Power Dissipation, P
D
CC
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 to 18V
–0.5 to 18V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Linearly Above 50
°
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35mW
0.7mW/
°
C
Total Device
Operating Temperature Range, T opr
Storage Temperature Range, T stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0
°
to +70
°
C
–55
°
to +125
°
C
Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), T
L
. . . . . . +260
°
C
Note 1. The small junction sizes inherent to the design of this bipolar component increases the component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degredation which may be induced by ESD.

Electrical Characteristics: (T
A
= 0
°
to +70
°
C, Note 2 unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Current Transfer Ratio
Logic Low Output Voltage
Logic High Output Current I
OH
Logic Low Supply Current I
CCL
Logic High Supply Current I
CCH
Input Forward Voltage
Input Reverse Breakdown
Voltage
V
F
V
(BR)R
Temperature Coefficient of Forward Voltage
Input Capacitance
Input–Output Insulation
Leakage Currnt
∆
V
F
∆
T
A
C
IN
I
IO
Resistance
Capacitance
CTR I
F
= 0.5mA, V
O
= 0.4V, V
CC
= 4.5V, Note 3, Note 4 400 800 –
V
OL
I
I
F
= 1.6mA, V
O
= 0.4V, V
CC
= 4.5V, Note 3, Note 4 500 900 –
F
= 1.6mA, I
O
= 6.4mA, V
CC
= 4.5V, Note 4 – 0.1
0.4
I
F
= 5mA, I
O
= 15mA, V
CC
= 4.5V, Note 4 – 0.1
0.4
I
F
= 12mA, I
O
= 24mA, V
CC
= 4.5V, Note 4
I
F
= 0, V
O
= V
CC
= 18V, Note 4
I
F
= 1.6mA, V
O
= Open, V
CC
= 5V, Note 4
I
F
= 0mA, V
O
= Open, V
CC
= 5V, Note 4
I
F
= 1.6mA, T
A
= +25
°
C
I
F
= 10
µ
A, T
A
= +25
°
C
– 0.2
0.4
V
– 0.05
100
µ
A
– 0.2
– mA
–
–
5
10
1.4
–
–
1.7
–
%
%
V
V nA
V
V
R
C
IO
IO
I
F
V
= 1.6mA
f = 1MHz, V
IO
F
= 0
45% Relative Humidity, T
= 3KVdc, Note 5
V
IO
= 500Vdc, Note 5 f = 1MHz, Note 5
A
= +25
°
C, t = 5s,
–
–
–
–
–
–1.8
60
–
10
11
0.6
–
–
1.0
–
– mV/ pF
µ
A
Ω pF
°
C
Note 2. All typicals at T
A
= +25
°
C, V
CC
= 5V unless otherwise specified.
Note 3. DC Current Transfer Ratio is defined as the ratio of output collector current (I
O
LED input current (I
F
) times 100%.
) to the forward
Note 4. Pin7 Open.
Note 5. Device considered a two–terminal device (Pins 1, 2, 3 and 4 shorted together and Pins 5,
6, 7 and 8 shorted together).
Switching Characteristics: (T
A
= +25
°
C unless otherwise specified)
Parameter
Propagation Delay Time
Symbol t
PHL t
PLH
Common Mode Transient Immunity CM
H
CM
L
Test Conditions
I
F
= 0.5mA, R
L
= 4.7k
Ω
, Note 3, Note 6
I
F
= 12mA, R
L
= 270
Ω
, Note 3, Note 6
I
F
= 0.5mA, R
L
= 4.7k
Ω
, Note 3, Note 6
I
F
= 12mA, R
L
= 270
Ω
, Note 3, Note 6
I
F
|V
= 0, R
L
CM
= 2.2k
Ω
, R
CC
| = 10V
P–P
= 0,
, Note 7, Note 8
I
F
|V
= 1.6mA, R
L
CM
| = 10V
P–P
= 2.2k
Ω
, R
CC
= 0,
, Note 7, Note 8
Min Typ Max Unit
–
–
–
–
–
5
0.2
5
1
500
25
1.0
60
7
–
µ s
µ s
µ s
µ s
V/
µ s
– –500 – V/
µ s
Note 3. DC Current Transfer Ratio is defined as the ratio of output collector current (I
O
LED input current (I
F
) times 100%.
) to the forward
Note 6. Use of a resistor between Pin5 and Pin7 will decrease gain abd delay time.
Note 7. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dv cm/dt on the leading edge of the common mode pulse (V
CM remain in a Logic High state (i.e. V
) to assure that the output will
O
2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode pulse signal (V
CM
) to assure that the output will remain in a Logic Low state (i.e. V
O
0.8V).
Note 8. In applications where dV/dt may exceed 50,000V/
µ s (such as static discharge) a series resistor (R
CC
) should be included to protect the detector IC from destructively high surge currents. The recommended value is:
1V
R
CC
=
0.15 I
F
(mA) k
Ω

N.C.
1
Pin Connection Diagram
Anode
Cathode
N.C.
2
3
4
8 V
CC
7 V
B
6 V
O
5 GND
8 5
.250 (6.35)
.020 (.508) Min
Seating
Plane
.100 (2.54)
1
.390 (9.9) Max
4
.185
(4.7)
Max
.115 (2.94) Min