Measuring Input Current of
a Buck or Flyback Converter
By John Bottrill,Senior
Senior Applications Engineer
Engineer,
Texas Instruments, Manchester, N.H.
Input currents for non-boost converter topologies
can be derived from current measurements in
the primary switch.
W
hen designing converters, it is often
desirable to measure the dc current
coming into the converter. This is
particularly true when batteries are
being used and the amount of discharge
current out of the batteries needs to be monitored and/or
limited for the health and long life of the batteries.
In most converters, there is a circuit that monitors the
V
IN
J1
C BULK
IIN
V
J5
CC
C3
VCC
V
Gate
CT
I SENSE
REF
Q1
R FILTER
FIL
GND
R SENSE
C FILTER
FIL
RINJ
Q2
CT
R
BIAS
U1
J4
R1
+
current through the main switch. This circuit is necessary to
prevent damage to the switch under transient conditions for
voltage-mode control and is an input to the control loop for
current-mode control. In addition, this circuit can be used
to measure the dc current into the converter.
In the topologies described here, the current through
the primary switch is either measured directly with a
resistor or indirectly with a current-sense transformer. This
measured signal then gives
the instantaneous current
D1
through the power switch.
J2
With buck topologies, Sepic
C4
or Flyback configurations,
J3
the only path for the
input current is through
the power switch. This
means that the current’s
integral through the switch
is equal to the integral of the
current into the converter
over the same time frame.
However, this method will
not work for boost topologies
because the total current
into the converter is greater
than the current through
the switch and additional
circuitry would be required
to measure the input current
(IIN).
–
C2
A Flyback
Topology Circuit
C1
R2
R3
Fig. 1. In this flyback circuit, input dc current is derived from voltage across the sense resistor.
Power Electronics Technology November 2005
34
Fig. 1 illustrates a flyback
topology circuit that uses
the existing current-sense
resistor (RSENSE) to measure,
amplify and present the
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INPUT CURRENT
information in the form of
D1
a voltage that tracks the dc
J2
VIN
level of the input current.
C BULK
C4
D3
The circuit’s function can
J3
be examined by referring to
T2:A
Fig. 1. Let’s take a specific
case that allows for a simple
J5
V
CC
Q1
explanation and shows how
C3
the input current informaVCC
tion can be derived. Suppose
V
Gate
REF
that the input voltage is conI SENSE
CT
stant, that the pulse width
RFILTER
R5
R6
FIL
of the switching converter
C FILTER
is at a 50% duty cycle, and
FIL
further that each cycle starts
RINJ
Q2
from zero. This is a realistic
CT
configuration for a disconR BIAS
tinuous flyback circuit.
Let’s assume that the
line input current from the
R1
R7
D4
+
source is constant at 1 A.
+
J4
–
–
C7
R4
When the switch Q1 is off,
C8
C1
R2
all the current from the line
R9
R10
goes into the bulk capacitor.
C4
C2
R3
But when the switch is on,
the current is drawn from
the bulk capacitor and the Fig. 2. This forward converter uses a current transformer and includes overcurrent protection (red).
line. Because the voltage and
current are fixed, the total charge into the supply through A Forward Topology Circuit
input terminal J1 over one cycle must equal the total charge
Fig. 2 shows a circuit configuration using a current
through the switch during the on time.
transformer for measurement. The difference is in the
Since the switch is on half the time and the current into the current-sense transformer’s turns ratio. Here it demonstrates
inductor is linearly increasing, the peak current through the a forward instead of a flyback topology.
switch is 4 A. Therefore, if you integrate the voltage developed
It should be noted in Fig. 2 that if a ramp is added into the
across the current-sensing
resistor over a single cycle
and divide by the resistance,
the average value of the input
current can be determined.
In the Fig. 1 circuit, this is
accomplished by resistors R1
and C1, where:
current signal ISENSE via Q2 to provide slope compensation
1
Ê
ˆ Ê fS ˆ
ÁË (2 ¥ C1R1) ˜¯ < ÁË 100 ˜¯ and fS is the switching frequency. for control/stability reasons, it will be small (much less than
1%) compared to the desired switch-current voltage when
But since RSENSE is small, that information is a small voltage measured across the current-sense resistor R6. As such, the
and the signal would be easier to use if it was amplified. The ramp will have little effect on the input current monitor.
operational amplifier U1 with resistors R2 and R3 provide this
Both Figs. 1 and 2 show the addition of the stabilizing
function. Resistors R2 and R3 set the operational amplifier’s signal for the power converter’s current-mode control.
gains to:
Current mode is a method of controlling the output voltage
by using the current signal in the primary of the transformer
Ê R 2+R 3 ˆ
as one of the inputs in the feedback loop.
ÁË
˜¯
R3
.
Sometimes it is desirable to shut the converter down in
C2 provides additional filtering if needed. By selecting the event of a sustained overcurrent but also allow for shortthe values of R2 and R3, it is possible to achieve any scaling duration transients above the maximum steady-state levels.
factor desired.
The components shown in red in Fig. 2 form a circuit that
Current mode is a method of controlling the output
voltage by using the current signal in the primary of the
transformer as one of the inputs in the feedback loop.
www.powerelectronics.com
35
Power Electronics Technology November 2005
INPUT CURRENT
J1
C3
2.2 µF
100 V
R5
9.9 k�
TP33
TP
J2
TP66
TP
Q1
U5:A
J5
+
Q3
R33
-
R8
0.080
R6
1.0
C31
R34
D3
R35
BAS16
C2
47 µF
16 V
C4
1 µF
R4
5.1 k�
�
TP11
TP
TP22
TP
R2
R1
26 k�
�
1.0 k�
1
2
3
4
6
8
7
5
U2
TPS2812D
VCC
REG_IN
REG_OUT GND
1OUT
OUT A
2OUT
1IN
R15
1.0
TP77
TP
C13
1 µF
1
2
3
4
C5
0.1 µF
Ê IIN ˆ
ÁË ˜¯ R 6,
N
UCC38083D
or
UCC38085D
8
CTRL VDD
ISET GND 7
CS
1IN 6
RT
2IN 5
R3
84.5 k�
�
TP44
TP
where N is the number of secondary
turns (T2:B) on the current transformer. The
primary (T2:A) is one turn. The resistors R9
and R10 are chosen so that the voltage at the
R9-R10 junction is equal to the voltage on the
comparator’s noninverting input when IIN is
at the maximum allowed level. R4 is chosen
so that the voltage on the ISENSE pin of the
converter is greater than the voltage necessary
to shut down the converter if the output of
the comparator becomes high.
TP55
TP
C8
0.1 µF
C1
500F
Fig. 3. The current-monitoring circuit was tested on this push-pull converter.
is designed to shut down the converter in the event of an
overcurrent being drawn from the battery. The input current
is measured by the current transformer T2 and a currentsense resistor R6.
The information from the current monitor is passed
through a low-pass filter R7 and C8, which integrates it over
several cycles and generates a dc voltage that is a function
Tek Run: 1.00 MS/s Sample
of the input current. The measured current
level is then compared to a dc level set
by the reference and R9 and R10. If this
signal exceeds the reference level, a signal is
generated that will shut down the converter.
C7 is used to prevent noise from causing false
tripping. An additional capacitor from the
output of the comparator to the positive
input (not shown) may be desirable to
provide hysteresis and reset time. This
connection would form a capacitive
voltage divider, so the additional capacitor
should generally be larger than C8.
After being filtered by R7 and C8, the
dc voltage at the noninverting input of the
comparator is equal to:
Testing the Theory
Tests were performed to prepare documented results of the
theory. A reference design using a UCC38083 was modified
to verify this operation. The circuit consisted of the reference
push-pull converter plus an operational amplifier and three
resistors and a capacitor.
Fig. 3 shows the essential elements of the modified circuit.
The input current was measured using a Tektronix current
Tek Run: 50.0 MS/s Sample
T
T
�: 2.94 V
@: 40 mV
�: 2.94 V
@: 40 mV
T
T
4
4
T
T
1
1
Ch1 1.00 V BW Ch4 1.00 V � BW M 50.0 �s Ch1
Ch1 1.00 V BW Ch4 1.00 V � BW M 1.00 �s Ch1
2.60 V
2.60 V
Fig. 4. Input currents for 24-V input and output set to 3 A (left) and 10 A (right).
Power Electronics Technology November 2005
36
www.powerelectronics.com
INPUT CURRENT
Tek Run: 50.0 MS/s Sample
Tek Run: 50.0 MS/s Sample
T
T
�: 2.94 V
@: 40 mV
�: 2.94 V
@: 40 mV
T
T
4
4
T
T
1
1
Ch1 1.00 V BW Ch4 1.00 V � BW M 1.00 �s Ch1
2.60 V
Ch1 1.00 V BW Ch4 1.00 V � BW M 1.00 �s Ch1
2.60 V
Fig. 5. Supply current sensor (blue) and current monitor (red) outputs vary inversely with VIN (19 V at left and 36 V at right) when load is constant.
Tek Run: 5.00 kS/s Sample
T
resonance with the power source. This is not sensed by the
current-monitoring circuit. However, there is some noise
on the error amplifier output. This can be taken care of by
additional filtering or a good layout. The circuit used here
was connected together by lengthy leads and was intended
for demonstration only.
The next test was to see the effects of a dynamically
changing load condition and its effect on the input current
as well as the monitored current. For this measurement, the
error amplifier output was sensed using a tip-and-barrel
connection to eliminate the noise previously seen.
The circuit was set at 10 Adc, and an additional 10-A
pulse was applied at 30 Hz with a 50% duty cycle. Fig. 6
shows the effect on the input current and the error amplifier
monitored output.
The signal’s ripple from the current probe is the result
of resonant currents between the input capacitor and the
power source. The low frequency seen is an aliasing effect.
As seen in the lower waveform in Fig. 6, the error amplifier
does not respond as quickly as the current probe. However,
it would be easy to increase the monitor circuit’s frequency
response by changing the R/C values of the low-pass filter.
In most cases, this low-frequency response is desirable.
That’s because the unit’s transients are not shut off unless
they would damage the unit. Indeed, the shutoff is taken
care of by the pulse-by-pulse current limiting of the
converter itself.
�: 30.2 ms
@: 36.0 mV
T
4
T
1
Ch1 1.00 V
Ch4 1.00 V � BW
M 10.0 ms Ch1
1.72 V
Fig. 6. Current-monitor filtering reduces noise but also slows step
response.
probe. The results were compared with the output of the
operational amplifier at J5. Extremely good results were
obtained at high- and low-current levels and in tracking
dynamic changes.
Fig. 4 was taken with the current on the output set at 3
A and 10 A. All of these figures were taken with a dc input
voltage of 24 V. The upper trace is the current probe and
the lower trace is the output of the error amplifier. In these
figures, the lower waveforms (showing voltages on J5) reflect
the increase in load and track with the upper waveforms
(showing the current probe signals).
Fig. 5 shows the effect of a constant load for different
input voltages. Since the load is the same, the input current
varies inversely with the input voltage variations. These
two figures also show the effects of an input voltage change
from 19 V to 36 V. Also of note in these figures is that the
current sensed by the current probe and the sensed voltage
at the operational amplifier output change by the same
percentage.
In the input current waveform, there is a ripple due to
the switching of the power switch that is causing a harmonic
Power Electronics Technology November 2005
Positive Results
It is possible to monitor the input current with minimal
additional circuitry using this method while getting an
accurate reproduction of the current levels into a power
converter. By adjusting the filter cutoff frequency, it would
be possible to increase the signal’s frequency content.
With the correct scaling, this circuit would be suitable
for monitoring and limiting the current from a battery into
a converter. It could also determine such things as power
consumption, total-charge consumption and remaining
battery life.
PETech
38
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