ICT - Information and Communication Technologies
Collaborative Project
Grant Agreement Number: 318240
Report on generic assembly and packaging concepts
applicable to PhoxTroT
D8.1
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D8.1
31.07.13 (M10)
01.10.2012
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Fraunhofer IZM
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WP8
30.08.13 (M11)
48 months
CO
Hermann Oppermann
Fraunhofer IZM, Gustav-Meyer-Allee 25, 13355 Berlin, Germany
+49 30 46403 163
hermann.oppermann@izm.fraunhofer.de
Kobi Hasharoni, Jochen Kraft, Hermann Oppermann
CEOS, AMS, Fraunhofer IZM
Abstract:
The packaging concept describes five different packaging levels. The first level is the interposer
technology including optical and electrical TSVs, optical waveguides and integrated switches. The
chip-to-interposer interconnects focus on the assembly of the components. The assembly of the
OptoChips to the optical board dealing with single mode is described as well as the assembly of
the CEOS router chip multimode operation. Finally multimode interconnects will be depicted for
multimode applications.
Keywords: 3D system integration, single mode and multimode transmission, silicon interposer,
optical transceiver chip
Security Notice
This document contains confidential proprietary information.
None of the information shall be divulged to persons other than partners of the FP7 PhoxTroT
project, authorized by the nature of their duties to receive such information, or individuals of
organizations authorized by the PhoxTroT Coordinator, in accordance with PhoxTroT Consortium
Agreement.
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(including the Commission Services) ; CO = Confidential, only for members of the consortium (including the Commission Services)
© PhoxTroT (FP7-318240)
PhoxTroT
D13.4 PhoxTroT Newsletter
PROJECT
Photonics for High-Performance, Low-Cost & Low-Energy
Data Centers, High Performance Computing Systems:
Terabit/s Optical Interconnect Technologies for On-Board,
Board-to-Board, Rack-to-Rack data links
PhoxTroT
01.10.2012
48 months
318240
Dr. Tolga Tekin - Fraunhofer
Large-scale integrating project - CP-IP
ICT-8-3.5 - Core and disruptive photonic technologies
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Report on generic assembly and packaging concepts
applicable to PhoxTroT
Report
D8.1
31.07.13 (M10)
30.08.13 (M11)
Tolga Tekin
Kobi Hasharoni, Jochen Kraft, Hermann Oppermann
Fraunhofer IZM
CEOS, AMS, Fraunhofer IZM
CO
WP8
Integration and Packaging
10.07.2013
30.08.2013
V5
30
final, consortium version
PU = Public; PP = Restricted to other program participants (including the Commission Services); RE = Restricted to a group specified by
the consortium (including the Commission Services) ; CO = Confidential, only for members of the consortium (including the Commission
Services)
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Table of Contents
1 2 2.1 2.2 3 4 4.1 4.2 4.3 4.4 4.5 5 Executive Summary .............................................................................................. 4 Purpose of this document ..................................................................................... 4 Document structure .......................................................................................... 4 Audience ............................................................................................................ 4 Introduction ....................................................................................................... 5 Packaging Concept ............................................................................................ 6 Interposer Technology ...................................................................................... 6 Chip to Interposer Interconnect ..................................................................... 12 On Board Interconnect Single Mode .............................................................. 18 On Board Interconnect Multimode ................................................................ 24 Board to Board Interconnect MM................................................................... 28 Summary .......................................................................................................... 30 30.08.2013
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1 Executive Summary
The packaging concept will be described in five different packaging levels 3.1 to 3.5. The
overall concept can be evaluated by combining the performance at each individual level
which simplifies the judgment of the whole concept. The first level is the interposer
technology (3.1) including optical and electrical TSVs, optical waveguides and integrated
switches. The chip-to-interposer interconnects (3.2) will focus on the assembly of the
components (laser diodes, PDs, drivers and TIAs). The active component itself will be
described in the work package 4 and in the related reports. On-board interconnects Single
Mode (3.3) will describe the assembly of the OptoChips to the optical board, whereas Onboard interconnects multimode (3.4) the assembly of the CEOS router chip. Finally
multimode interconnects will be depicted for multimode applications (3.5).
2 Purpose of this document
The objective of this deliverable D8.1 is to report on generic assembly and the packaging
concepts applicable to PhoxTroT. It will serve as a guideline for all partners towards the
development of components and the hybrid integration technologies. It will also be an
input for the planning of the final demonstrators.
2.1
Document structure
The present deliverable D8.1 is split into four major chapters:
 Executive summary
 Introduction
 Packaging Concept
 Summary
The main chapter with the packaging concept is further divided into five sub chapters
dealing with the different integration levels.
2.2
Audience
This document is Public. We will write an internal one and extract a public version. Please
mark those paragraphs which should be consortium confidential
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3 Introduction
Detailed assembly and packaging flow are reported for different optical interconnect
technology layers. It will provide a description of the process flow for the packaging across
all interconnect hierarchy layers: interposer level, chip-to-interposer, on-board and boardto-board.
The process conditions and the tolerances at each integration level are collected and
analyzed in order to consider different requirements as overall system performance
including coupling efficiency and bandwidth, optoelectrical signal integrity, CMOS
compatibility, thermal management including low power and control of heat transfer,
thermo/mechanical stability (CTE mismatch) and reliability aspects. As a result an overall
process flow will be described. Further on it will provide input for the design of the
components with respect to interfaces and features for a common alignment strategy.
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4 Packaging Concept
4.1 Interposer Technology
The core interposer technology is shared between the PhoxTroT project and the MIRAGE
project (Grant Agreement No. 318228). This is the production of an interposer with
metallization layers on front- and backside of the Silicon substrate and the processing of
through silicon vias (TSVs) that provide an electrical connection between the two interposer
sides. In addition in PhoxTroT optical vias will be investigated according to the special
needs of the objected prototypes. These optical vias will allow transmitting light through
the substrate. E.g. a VCSEL mounted on the backside of the interposer could emit light,
which passes through the optical via to a photodiode on the front side of the interposer.
A concern about the transmission of high frequency electrical signals through an (electrical)
via is cross talk. As the interposer has low doping levels in the deeper regions of the
interposer substrate, small potential variations in the TSV can cause long range charge
shifts in the substrate that could reach a neighbor TSV. A (by ams AG) patented solution to
battle the cross talk is the contacting of the substrate close to the substrate or even more
promising realizing a co-axial TSV. This so-called co-axial TSV has a second metallization
layer build in which serves as shielding layer. Thus the potential spread can be suppressed.
The bulk TSV and the co-axial TSV could also be a solution for cross talk problems in
Mirage, but will be reported in the frame work of PhoxTroT.
The need for higher speed of signal transmission resulted in the idea of using a Si
interposer instead of a PCB. On an interposer design rules like in standard Si wafer
processing technology are valid thus enabling more compact and denser metal lines.
Shorter connecting lines are a prerequisite for less parasitic inductances and capacitances,
which is needed for high speed signal transmittance. The main properties an interposer
needs in comparison to a mere Si chip is the capability of providing pads for bonding of
further chips on both sides. I.e. structured metal layers and isolation layers are needed on
both sides. Furthermore electrical connections through the interposer so-called Through
Silicon Vias (TSVs) are needed.
From these properties the main additional (pure interposer) processing steps can be
deduced:
1. Thinning of the wafer
2. Backside processing of a metal redistribution layer
3. TSV processing
In order to fulfill these processing steps an auxiliary mean is needed. Further processing of
thinned wafers is only possible with the aid of a temporarily bonded wafer. This wafer
gives the whole system of device wafer plus temporary handling wafer (THW) mechanical
stability and enables the processing of layers on the backside of the bonded wafer pair. In
this case the THW takes over the functionality of the wafer substrate.
As the interposer serves as basis for an optical chip, a wave guide structure needs to be
integrated. Furthermore a special post processing of windows in the oxide above the inplane coupler is required.
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Two kinds of platforms for the optical chips will be needed.
1. C2B active photonic chip (optical transceiver chip)
PCB-WG -> PD -> TIA -> driver -> VCSEL -> WG -> PCB-WG
The signal is coming from the wave guide which is embedded in the PCB, the
photonic chip receives the light by the photo diode array and transforms the signal
from an optical to an electrical signal. The TIA is processing the signal, the output is
going to the driver chip, which drives the VCSELs. The VCSELs feed the signal into
the wave guide of the optical chip via a grating coupler and a grating coupler will
also serve as link to the PCB wave guide.
2. 3D photonic router (optical router chip)
PCB-WG -> PD -> TIA -> driver -> VCSEL -> WG -> Router -> PCB-WG
The signal path for the 3D photonic router will be like in the C2B active photonic
chip, but additionally after the signal was fed into the chip wave guide, it ill be
optically processed by a router before a grating coupler makes the optical signal
leave the wave guide and makes it pass to the PCB wave guide.
Among several versions the process flow was chosen under the criterions of minimum
process effort and maximum process stability. The final version has the advantage of a
reduced number of bonding steps, the need of a TSV processing only from one side and
the advantage that there is no bonding interface in the final interposer chip which
increases the robustness of the whole device.
The processing flow is as follows
 Structuring of the wave guide: in-plane couplers, wave guides, routing structures
(done by the wave guide supplier)
 Oxide fillings, planarization and metallization
 Opening of passivation pads
 Temporary bonding of the first temporary handling wafer (covering the wave guide
side)
 Oxide deposition
 TSV processing:
o TSV etch
o Isolation oxide deposition and opening of the bottom oxide layer
o TSV metallization deposition and structuring
o Passivation layer deposition and structuring
 Temporary bonding of the second handling wafer (covering the TSV side)
 Removal of the first temporary handling wafer
 Processing of pad openings for bonding of drivers and TIAs
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Figure 1: TSV processing with the aid of the first temporary handling wafer
Figure 2: Removal of the first temporary handling wafer and pad opening on the wave
guide side of the interposer.
The TSVs shown in Figure 3 reveal the functionality of a TSV. A metallization layer is
embedded between two Si oxide layers. The layer between the metallization and the
substrate serves as isolation layer. Breakdown Voltages above 100 V can be achieved
through the thickness of the isolation layer decreases with TSV depth. The metallization
layer is deposited by a CVD process which enables constant thickness throughout the
whole TSV sidewall and thus enables a low TSV resistance. Finally the oxide layer seals the
TSV against environmental influence.
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Isolation layer
TSV
metallization
Passivation layer
Figure 3: cross section of top TSV sidewall (left hand side); bottom TSV (right hand side
Optical via
The optical via is an option which enables the placement of the VCSELs on the backside of
the interposer (see also chapter 3.2). Ideally the VCSEL which feeds the light into the PCB
wave guide should be placed as close as possible to the PCB. But unfortunately the VCSELs
used for the extremely fast application in this process have the light output on the same
side as the bumping pads. I.e. the light goes into the direction of the interposer to which
the VCSELS are mounted.
The optical via should not impose additionally processing complexity to the interposer flow.
Therefore it is planned (and already realized on the first test chip) to process a TSV in the
same manner as a normal electrical via, but leave out the metal landing pad. I.e. there will
be no stop layer for the TSV oxide etch and as a consequence of this fact, the TSV will be
slightly deeper, but it can be expected, that the oxide membrane is still thick enough to
withstand the successive processing procedures.
Suppression of cross talk in-between TSVs
1. Enough spacing between the TSVs
The design rule for the spacing of TSVs demands a distance between TSVs of
180μm. It is not yet known, if this is enough in order to avoid cross talk, but a test
structure with varying the TSV spacing is placed on the first test chip.
2. Bulk TSV
The easiest way of suppressing cross talk is the electrical contacting and grounding
of the bulk surrounding the TSVs. Similar to the optical TSVs a concept for a TSV
serving as a bulk contact was worked out that can be processed in parallel to the
normal TSVs. Only layout changes can trigger the different functionality of this socalled bulk TSV. It is known, that the etch rate in deep reactive ion etch depends
on the diameter of the TSV. Thus if a TSV is layouted with a smaller diameter, e.g.
60% of the standard diameter, the etch depth will not reach the total thickness of
the substrate. The TSV etching will stop within the substrate and the successing
metallization will create an electrical contact to the substrate bulk
3. Co-axial TSV
From an electrical point of view the ideal kind of TSV for suppression of cross talk
is a so-called co-axial TSV with a second sidewall metallization which can shield the
electromagnetic disturbances from the inner TSV metallization which carries the
electrical signal. In this case additional processing steps are needed as another
isolation layer, another metal deposition and another structuring step for the metal
layer is needed. The process flow is shown in Figure 4.
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Figure 4: process flow of a co-axial TSV
(a) Standard TSV processing with one metal layer
(b) Metal “spacer” etch – the TSV bottom metal layer is removed by a anisotropic etch,
while the metal layer on the wafer surface is protected by a resist mask
(c) Deposition of the second isolation layer and spacer etch in order to release the
second landing pad (metal 2)
(d) Deposition and structuring of the second TSV metal layer
(e) Passivation deposition
(f) Pad opening in the passivation layer
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The design rules for the interposer were already reported in deliverable D1.2 on page 85.
They are the combination of the CMOS design rules and design rules specifically defined
according to the needs of TSV. Main parameters are the diameter of the TSV and the metal
enclosure. But also parameters like spacing between TSVs or the spacing from TSV to metal
and poly/wave guide structures are important.
Figure 5: TSV design rules
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4.2 Chip to Interposer Interconnect
Module Concepts
The module concept is mainly driven by the optical interconnect scheme and the coupling
efficiency. The original concept was based on VCSEL with backside emission, PDs with
backside illumination and therefore their assembly was planned on the bottom side of the
interposer for optical interconnect to the optical PCB (Figure 6). It turned out, that backside
emitting VCSEL will not be available and therefore only concepts with front side emitting
lasers were further investigated.
Figure 6: Original module concept based on backside emitting VCSEL.
Preparation of interposer wafers
The interposer wafers which are completely processed at AMS will be further processed at
IZM in order to electroplate a tall bump socket. The large socket will be needed to mount
components as VCSEL, PD or silica lenses on the bottom side of the interposer. Flip chip
assembly is selected to meet the sever RF requirements up to 40 Gbps. The bump socket
will end with a gold metallization for mechanical gold stud bumping to increase the bond
height.
FUI (Flipped Under Interposer)
The FUI concept is based on the coupling of VCSEL into an optical layer in the interposer
and from there to the optical waveguide in the PCB (Figure 7). The optical layer will be
integrated in the interposer anyway for the optical router module. Optical interconnects to
the interposer waveguides is formed by grating couplers. As the grating couplers have the
highest coupling efficiency with 10° inclination the VCSEL array will be assembled with
such a tilt.
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Figure 7: VCSEL coupled first to optical waveguide at interposer and coupling waveguide
to waveguide into PCB
FOI (Flipped On Interposer)
In the FOI concept the VCSEL array is assembled on the interposer. The light passes
through the interposer and couples into the optical PCB. As silicon is transparent the beam
could propagate through the silicon. But optical simulations have shown that losses from
reflections at the silicon interface are very high. Therefore optical vias of 80 μm in diameter
will be etched into the interposer (Figure 8). The interposer thickness should be as thin as
possible. 100 μm or even 50 μm thickness should be targeted. Beside wafer processing
also thermocompression bonding will show the limitation in thickness reduction.
In order to collimate the beam silica lenses are mounted at the bottom of the interposer.
Figure 8: VCSEL at top side of interposer and transmission through optical via
In both module concepts the PD array is mounted in a similar way as the VCSEL array to
the silicon interposer. The driver components and the TIAs are always mounted on top of
the interposer.
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Assembly of VCSEL and PD Arrays, Drivers and TIA
The VCSEL array of four lasers will be flip chip bonded by thermocompression. Gold stud
bumping is performed on the interposer in order to avoid clamping of small VCSEL or PD
arrays. Final metallization on silicon interposer pads can be any CMOS-typical aluminum
(0.5 to 1 μm thickness) or gold (minimum thickness 1 μm) with minimum pad opening in
the passivation of 60 μm. Driver and TIA circuits should have similar pad metallization as
the interposer for stud bumping.
Figure 9: Single VCSEL construction
Figure 10: Backside illuminated PD array for 25 GHz application
For the VCSEL design shown in Figure 9 three interconnects are planned per channel. A
first order rough calculation of the thermal resistance for die bonding using Ag filled
adhesive showed a thermal resistance of 0.4 K/W. Using 3 Au stud bumps with 30 μm
diameter and 30 μm height the thermal resistance is decreased by a factor of 9 (see Table
1).
x
y
t
A

R_th
die bond
0,25 mm
0,25 mm
0,025 mm
0,0625 mm²
1 W/mK
0,4 K/W
d
n
t
A

R_th
flip chip
0,03 mm
3
0,03 mm
0,0021 mm²
318 W/mK
0,0445 K/W
Table 1: Thermal resistance
For the PD array show in Figure 10 each source and ground pad will be connected with a
flip chip bump. In addition the two pads in the upper corner will have bumps as well.
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Footprint
The driver and the TIA will need a footprint of 1.5 mm² per channel, which means with 4
transceiver channels 6 mm² for the TIA and 6 mm² for the driver. The footprint of the
VCSEL array will be 0.25 mm² whereas the PD array has a slightly larger footprint of 0.5
mm². The number of TSVs depends on the location of the VCSEL and PD arrays whether
they are on top or bottom of the interposer. Between 10 and 32 TSVs are expected for the
interposer. TSV diameter is 80 μm, TSV pitch should be in the range of 160 μm, which
allows for 36 TSVs per mm². All together this sums up to 14 mm² and adding the same
area for space between the components 28 mm² are required. An interposer size of 10
mm x 10 mm is therefore fully sufficient.
Process Flow FOI
The process flows for the assembly of the flip chip on interposer (FOI) is shown in Figure
11. It starts with stud bumping and mounting of VCSEL, PD, TIA and driver on the upper
site of the silicon interposer. The VCSEL will be aligned to the center of the optical via.
Correction data from Vertilas are used for the VCSEL alignment. A silica lens with a
maximum thickness of 100 μm will be glued using fiducials on the lens and the same
alignment procedure for the optical via. The alignment tolerances for VCSEL / PD and
lenses are assumed to be within ±1 μm. The adhesive used for gluing must withstand
follow-up process temperatures of 260°C. The fiducial on the lens will be used for the
alignment to the optical board.
Figure 11: Process flow for FOI
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Process Flow FUI
For the assembly of the flip chip under interposer (FUI) the process flows is shown in Figure
12Figure 11. Again, it starts with stud bumping and mounting of VCSEL and PD to the
bottom side of Si interposer. They are aligned to the fiducials from grating coupler
definition. On the top side of the interposer the TIA and the driver will be bonded by
thermocompression. The alignment tolerances for VCSEL and PD are assumed to be within
±1 μm. The fiducial defined by the grating coupler process will later be used for the
alignment to the optical board.
Figure 12: Process flow for FUI
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4.3 On Board Interconnect Single Mode
The optical waveguides are either formed in glass on a glass sheet or in polymer on silicon
wafers. The concept will be valid for both approaches. The glass sheet used in ion
exchange process to form the waveguides will be cut down to 8” wafer size with a laser.
Electroplating
For the assembly of the interposer a high stand-off is required. Therefore Cu bumps with
50 μm height and 80 μm in diameter are electroplated (Figure 13). Signal tracks, probe
pads and Via pads for the PCB contact are plated using 5 μm Cu. On top of the probe pads
and the bumps approximately 1 to 3 μm Ni and 2 μm Au will be deposited.
Figure 13: Processing of optical inlay (glass or Si)
PCB Lamination and Cut-Out
The glass wafer is singulated and a laser is used to achieve the cut-out of approximately
25 mm x 5 mm (Figure 14). With silicon wafers the cut-out is formed by DRIE etching. The
parts are laminated into a PCB. The PCB has a cut-out area of about 30 mm x 30 mm. Vias
are drilled into the PCB towards the via pads on glass and connect the signal traces on the
inlay with the signal routes on the PCB. For the glass inlay the facet of the waveguide is
finally prepared by a cleavage.
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Figure 14: Glass / silicon carrier after PCB processing with cut out
Assembly of Coupling Element
The coupling element (CE) is attached under a support frame, which is well aligned and
glued on the inlay (Figure 15). One coupling element will typically consist of at least 8
single mirrors / lenses (4 + 4 for PD and VCSEL) fabricated with a single mask process and
will be aligned together as a whole. Extra channels and mirrors / lenses could be designed
in to support the alignment procedure. The PCB cut-out area has to be larger than the
support frame. No electrical signal routes on the inlay should cross the area under the
support frame to provide a flat surface.
Figure 15: Mounting of support frame and coupling element
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Assembly of Optochip
The pre-assembled Optochip is aligned and bonded by thermocompression at 260°C. The
method is similar for the FOI (Figure 16) and the FUI (Figure 17) concept, mainly the
coupling element and the alignment concept differ from each other. For the FOI fiducials
on the silica lens and those on the coupling element will be used. In the case of FUI the
fiducials processed with the grating couplers are aligned to those from the coupling
element.
Figure 16: Mounting of pre-assembled interposer (FOI concept)
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Figure 17: Mounting of pre-assembled interposer (FUI concept)
Process Flow
The process flow is already quite obvious from the pages before. In more detailed they can
be seen with cross-sections in the following pictures.
In the FOI concept (Figure 18) Stud bumping is performed on the inlay which is already
laminated into the PCB (as shown in Figure 14). The coupling elements are aligned and
fixed by gluing. During assembly of the Optochip to the PCB the fiducials on the CE are
aligned to those on silica lens. Thermocompression bonding at 260°C with ±1 μm accuracy
is achievable.
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Figure 18: Process flow for FOI concept
A modified process flow could become attractive: The Optochip is mounted on the optical
PCB without any VCSEL or PD arrays (Figure 19). With additional optical waveguides,
lenses, mirrors and optical TSVs an optical reference could be designed in to measure any
deviation from the optical axis. The data’s could be used for recalculating the position of
VCSEL and PD. The thermocompression bonding of VCSEL and PD can then be performed
with corrected placements with respect to the optical TSV.
Figure 19: Process flow for FOI concept with final assembly of VCSEL and PD
For the FUI concept the assembly flow will be similar and starts with Au stud bumping at
250°C (Figure 20). The coupling element is attached with the support frame by gluing. The
pre-assembled Optochip is aligned using fiducials on the coupling element and on the
silicon interposer fabricated with the grating coupler. Thermocompression bonding at
260°C is used to fix the position.
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Figure 20: Process flow for FUI concept
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4.4 On Board Interconnect Multimode
The multimode assembly task is based on a chip to chip interconnect using polymeric
waveguide arrays; the router chip design is described in deliverable D6.2 and the MM
waveguides D5.1. Optical coupling between the VCSEL and PD arrays on the router chip is
achieved using a lens relay and a folding mirror/prism as described in deliverables D7.1 and
D7.2.
Chip Alignment on Board
The router chip is 52×52mm in size with a 4000 element BGA matrix at 0.8mm pitch; a
4×10 cutout hole in the package allows for optical coupling. Both, VCSEL and PD matrices
are assembled directly on the CMOS chip, and this structure is further assembled using
onto an organic package with the BGA matrix on its top. A schematic layout of the router
chip on a PCB with waveguides is given in Figure 21; obviously, there are several
accumulating alignment errors which must be considered for assembly and coupling into
an embedded waveguide array:
 VCSEL/PD on CMOS:
±7μm
 CMOS to package:
±15μm
 Package to PCB:
±100μm
 Overall error (RSS):
±101μm
These alignment uncertainties result from ball collapse during reflow and self-alignment
and are a function of the ball diameter (525μm in the BGA case). Given the 50×50μm
profile of each waveguide, a passive alignment scheme becomes very challenging at this
phase as it would require fabrication of micromechanical structures that would have to
align a very large chip to within ±15-20μm. Thus, for the first phase of PhoxTrot, an active
alignment method is selected in which the chip is assembled onto the PCB using ordinary
BGA placement techniques and the optical coupling elements are actively aligned.
Figure 21: Schematic layout of the CEOS router chip on a PCB with embedded WG arrays.
Board Design for Chip to Chip Interconnection
The PCB is designed to accommodate 2 router chips 15cm apart; the router chips are
placed rotated to each other such that the Tx matrix of chip #0 is linked via a waveguide
array to the Rx matrix of chip #1 and vice versa. Thus, there are 2 cut-out holes for both
chips sized 11.5×5.1mm above-which the router chip is assembled using its BGA matrix. In
addition, there are also 2 MTP fiber connectors which are described in a following section;
the board layout is shown in Figure 22. The multimode waveguide arrays connecting the
two chips are polymeric with a 50μm profile. The VCSEL and PD matrices have a 12×14
layout; however, at this phase only a subset of these 168 channels can be utilized in a
single WG layer. Thus, there are 28 WG channels connecting the two chips (14 Tx0 to Rx1
and 14 for the opposite route). The PCB electrical layout was carried out such that the area
above and around the optical waveguides is free of vias and components (Figure 22C).
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Thermal control of the system is done using a heat sink above each router chip and with
forced air flow through the fins. A thermal interface material is used to ensure good
thermal coupling. The power dissipation of each chip is about 25-30W and the laser
junction temperature is maintained at 60-70ºC.
Figure 22: Board layout showing the WG arrays, 2 router chips and MTP fiber connectors
(A); board layout with the heatsink assembled on the router chips (B); location of the WG
arrays with respect to the router chip (C).
Optical Alignment Method
Optical coupling is based on a 3-lens relay with one microlens array (MLA) assembled on
the VCSEL or PD matrix and two MLA arrays assembled on the folding matrix. The first lens
is a high index (GaP) one which is pre-aligned on the optoelectronic chips using flipchip
with accuracy better than 3μm and 1º; the other two lenses are from Silica. The optical
system is designed to maintain coupling over a long optical path of 2.5-3.5mm and to
couple the light into the WG or PD 50μm aperture with an illuminated area of < 20μm in
diameter. Following PCB assembly, the VCSEL and PD matrices on the router chip are
offset from the WG array by an unknown lateral and angular shift which results from the
uncontrolled self-alignment of the BGA solder balls on their pads. An optical coupling
element which includes a right angled prism with 2 MLA attached is used to correct for the
assembly errors. This optical coupling element is built from a glass cube with a triangle-like
cutout area such that the structure is made from two right angled prisms attached to each
other (Figure 23A). The two lens arrays are aligned on the normal surfaces of the coupling
element using flipchip and alignment marks evaporated on glass. The double prism is
mounted and glued onto a metal holder shown in Figure 23A using a mechanical
alignment jig. The entire assembly is connected to a vacuum chuck and inserted into the
cut-out hole in the PCB. The final location and angular position of the element is
determined from an active coupling scheme using a 6-axis mechanical stage. Final
placement is determined by maximizing the optical power going into the WG arrays (Tx
coupling) or the optical signal on the PD (Rx coupling). Final fixation of the coupling
element is carried out using metal blocks glued onto the PCB surface. This procedure is
carried out for both VCSEL and PD coupling.
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Figure 23: coupling element with the MLA assembled on top (A) assembly of the coupling
element on the PCB using metal blocks (B) assembly of two coupling elements above both
VCSEL and PD matrices (C).
The feedback required for active alignment of the first chip is obtained from a second
coupling element inserted into the second cut-out hole. This element is based on a dove
prism which is also attached to a vacuum jig for manipulation inside the hole. A power
meter or laser source located at the lower face of the prism will be used as an optical
feedback to the alignment. The active alignment scheme is shown in Figure 24.
Figure 24: Active alignment scheme of a router chips. The aligned coupling element is
shown here on the right side and the alignment tool is shown in the cut-out hole on the
left side. An optical power meter or laser source can be attached to the lower arm of the
alignment tool dove prism.
Once a satisfactory optical coupling to and from the WG array has been obtained, the
coupling element is glued onto the PCB using a mixture of low-shrinkage epoxy glues as
shown in Figure 23B. The procedure is than repeated again for the second Rx or Tx matrix
(Figure 23C). With one router chip aligned, the optical coupling element of the second chip
is actively aligned in a similar way. However, the alignment feedback is obtained directly
from the photo-response of the first router chip.
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Optical Loss Budget
An estimate to the overall loss budget for a 15cm optical link as described above between
two router chips is given in the following table for two cases. In the worst case, we assume
a WG loss of 0.3dB/cm which will be optimized to 0.1dB/cm in the target case. Similarly,
scattering from the WG surface has been shown to be a dominant factor when estimating
the propagation loss. However, polishing of the PCB edges and/or applying a thin layer of
UV curable glue has been shown to significantly reduce the scattering from the WG
surface.
VCSEL power
(dBm)
VCSEL to WG
coupling
Front surface
scattering
WG
propagation,
15cm
Back surface
scattering
WG to PD
coupling
PD signal level
(dBm)
Worst
case
3.0
Target
case
3.0
-3.0
-2.0
-2.0
-0.5
-4.5
-1.5
-2.0
-0.5
-4.0
-3.0
-12.5
-4.5
The typical VCSEL power is 3dBm and the receiver sensitivity at BER < 10-12 was found to
be -8 to -10dBm; the dynamic ratio is about 12dB. Obviously, the worst-case scenario is
problematic while the target case can be handled by the router chip while maintaining BER
at an acceptable level.
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4.5 Board to Board Interconnect MM
The board to board interconnect using MM waveguides is a two phase project with the
first phase being based on a fiber to WG interconnect and the second will be based on
board to board interconnect. We describe here the alignment method for the fiber to WG
phase which is also based on the PCB described in section 3.3 above.
Fiber to Waveguide Coupling Method
Coupling between a MPO connector and the router chip is carried out as described in
Figure 25. One fiber connector is routed into the VCSEL matrix on the router chip and the
other is interconnected with the PD matrix. A 90º folding mirror is built into the PCB and
fabricated with the WG arrays in a single process. In order to facilitate butt-coupling (w/o
microlenses), a trench is cut above the WG termination area such that the ferrule can be
brought into close contact with the mirror.
Figure 25: WG arrays connecting 2 MPO fiber connectors and the router chip (left); blowup of the fiber connector on board showing the trench in the PCB and the coupling mirror
(right).
Alignment and fixation of the MPO connector is required in order to facilitate a pluggable
operation of the device. However, the positional and diameter accuracy required from the
guide pin holes is in the <5μm range which is practically impossible to achieve using PCB
drill technologies. Similarly, the usage of fiducials is also not practical because of
technology limitation. Thus, an active alignment step is required based on attachment of a
second MT ferrule to the bottom side of the PCB, Figure 26. Two large diameter guide
holes are drilled on both sides of the WG array through-which the MT guide pins will be
routed through the board. The accuracy needed for these guide pins is provided by the
external MT ferrule. Prior to gluing of the ferrule to the board, it is manipulated in space
until good coupling has been achieved.
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Figure 26: Fiber to WG alignment method
Fiber to Waveguide Coupling Method 2
An alternative method is based on the US Conec ‘PRISM’ connector which has a built-in
90º folding element based on TIR lenses. In this case, the bottom side ferrule is replaced
with the housing of the Prism connector which will be actively aligned before final
attachment to the board. This method is probably superior to the previous one as it is
simpler to perform with all the needed guide-pin accuracy contained within the connector
housing.
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5 Summary
The packaging concept applicable for FoxTrot is split in five different integration levels with
common defined interfaces for electrical and optical interconnects.
The interposer manufacturing concept includes the electrical routing of TIA and drivers on
the top, the integration of photodetectors and VCSEL on the bottom side and a version
with VCSEL on the top. Through silicon vias (TSV) connect top and bottom layer and an
optical via is formed to couple the light from the VCSEL on top of the interposer directly to
the PCB. The process flow takes care of an optical layer and includes concepts for bonding
and de-bonding of handling wafers.
The TIA and drivers are flip chip attached to the top side of the interposer. The assembly of
VCSEL and PD are planned in one version on the bottom layer of the interposer by flip chip
assembly. The VCSEL is slightly tilted during flip chip bonding to increase the optical
coupling efficiency. In another version all components are placed on top of the interposer
over an optical TSV and collimating lenses are attached to the bottom side. The
components are bumped using mechanical Au stud bumps and thermocompression
bonding.
In the next integration level the interposer is thermocompression bonded on a PCB where
an optical layer has been laminated in. For optical coupling the PCB is opened to give
access to the optical layer and a coupling element with mirrors is fixed in front of the
optical waveguides in a cavity.
The multimode assembly task is based on a chip to chip interconnect using polymeric
waveguide arrays. Optical coupling between the VCSEL and PD arrays on the router chip is
achieved using a lens relay and a folding mirror/prism.
The board to board interconnect using MM waveguides is a two phase project with the
first phase being based on a fiber to WG interconnect and the second will be based on
board to board interconnect. The alignment method for the fiber to WG phase is
described.
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