A 400MHz
Direct Digital Synthesizer
with the AD9912
Daniel Da Costa
danieljdacosta@gmail.com
Brendan Mulholland
firemulholland@gmail.com
Project Sponser:
Dr. Kirk W. Madison
Project 1160
Engineering Physics 479
The University of British Columbia
January 9, 2012
Part I
Design and Fabrication of the
Device
i
Executive Summary
Part I of this report discusses the design and and fabrication stage of this project. At time of writing,
testing is on hold while a complete prototype device has been assembled. Part II will follow and will
include documentation the testing procedures, the results and all recommendations.
This project aimed to design, build and test a complete and functional Direct Digital Synthesizer
(DDS) device with output frequencies of up to 400MHz. A DDS is a device capable of digitally
generating sinusoidal waves with programmable frequency and phase. The Analog Devices 9912
(AD9912) was chosen as a suitable DDS Integrated Circuit (IC) and this was used in the project
design. An enclosure also had to be built to house the DDS device.
The device had to be compatible with an existing parallel control interface used in the lab,
requiring a parallel-to-serial converter, as the AD9912 requires a serial interface. This parallel-toserial converter was designed and prototyped on a breadboard to verify correct operation.
It was also necessary for the device to minimize noise. This was accomplished with a passive
analog filter circuit that was simulated in SPICE and confirmed to meet design specifications.
Complete designs and fabrication files for the circuit and enclosure had to be provided. The
schematics for the board were completed and a PCB layout was designed from this schematic. The
PCB layout generated all files required for manufacturing. The enclosure was modified from an
existing design to better accommodate the PCB layout and to improve heat dissipation.
Twenty PCBs had to be manufactured and parts had to be ordered for 15 boards. These have
all arrived and a prototype device is currently being assembled. Enclosures for 15 boards also had
to be ordered and these are all currently being manufactured.
ii
Contents
Executive Summary
ii
Contents
iv
List of Figures
vi
List of Tables
vii
Glossary
viii
Acronyms
ix
Acknowledgements
x
1 Introduction
1
2 Discussion
2.1 Theory of Operation . . . . . . . . . . . . . . . . .
2.1.1 Device Overview . . . . . . . . . . . . . . .
2.1.2 The AD9912 Direct Digital Synthesizer . .
2.1.2.1 DAC Peak Output Current . . . .
2.1.3 RF Output and the Reconstruction Filter .
2.1.3.1 SPICE Verification . . . . . . . . .
2.1.4 Clock Drivers . . . . . . . . . . . . . . . . .
2.1.5 Clock Inputs . . . . . . . . . . . . . . . . .
2.1.5.1 SCLK . . . . . . . . . . . . . . . .
2.1.5.2 SYSCLK . . . . . . . . . . . . . .
2.1.5.3 PLL . . . . . . . . . . . . . . . . .
2.1.6 Digital Control . . . . . . . . . . . . . . . .
2.1.6.1 The UTBus . . . . . . . . . . . . .
2.1.6.2 The AD9912’s Serial Control Port
2.1.6.3 Parallel-to-Serial Converter . . . .
2.1.6.4 Programming . . . . . . . . . . . .
2.1.7 Power Management . . . . . . . . . . . . .
2.2 PCB Layout Considerations . . . . . . . . . . . . .
2.2.1 Components . . . . . . . . . . . . . . . . .
2.2.2 Power Plane . . . . . . . . . . . . . . . . .
2.2.3 Heat Dissipation . . . . . . . . . . . . . . .
2.2.4 Characteristic Impedance and Trace Width
2.3 Design and Fabrication Methods . . . . . . . . . .
2.3.1 Schematic Design . . . . . . . . . . . . . . .
2.3.2 PCB Design . . . . . . . . . . . . . . . . . .
2.3.3 PCB Fabrication . . . . . . . . . . . . . . .
iii
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4
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20
CONTENTS
2.4
2.5
2.3.4
Board
2.4.1
2.4.2
2.4.3
Enclosures . . . . . . . . . . .
Features . . . . . . . . . . . .
Inputs and Outputs . . . . .
DIP Switch . . . . . . . . . .
Configuration Options . . . .
2.4.3.1 SYSCLK . . . . . .
2.4.3.2 SCLK . . . . . . . .
2.4.3.3 SCLK Enable Pin .
2.4.3.4 CMOS Clock Driver
2.4.3.5 PLL . . . . . . . . .
2.4.3.6 RF Path . . . . . .
Breadboard Testing . . . . . . . . .
iv
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Voltage
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21
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3 Conclusions
29
4 Project Deliverables
4.1 List of Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Financial Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
31
References
32
A Schematic Diagrams
33
B PCB Fabrication Drawings
43
C 3D PCB Renderings
48
D PCB Parts List
51
List of Figures
1.1
Photo of the 150MHz AD9852-based DDS . . . . . . . . . . . . . . . . . . . . . . . .
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
Block diagram of the full DDS device, showing input and outputs. . . . .
Block diagram showing internal functionality of the AD9912. . . . . . . .
Reconstruction filter schematic used for SPICE simulation. . . . . . . . .
Reconstruction filter transfer function generated from SPICE simulation.
Diagram of the 50-Pin UTBus Connector . . . . . . . . . . . . . . . . . .
Timing diagram for the UTBus. . . . . . . . . . . . . . . . . . . . . . . . .
The PCB power plane design. . . . . . . . . . . . . . . . . . . . . . . . . .
Diagram of microstrip trace geometry. . . . . . . . . . . . . . . . . . . . .
Diagram of stripline trace geometry. . . . . . . . . . . . . . . . . . . . . .
PCB layout, top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB layout, bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Assembly diagram, top side. . . . . . . . . . . . . . . . . . . . . . .
Device Assembly diagram, bottom side. . . . . . . . . . . . . . . . . . . .
Photo of the PCB, top side. Some components have been installed. . . . .
Photo of the PCB, bottom side, no components. . . . . . . . . . . . . . .
Labelled diagram of the enclosure body. . . . . . . . . . . . . . . . . . . .
Diagram of the enclosure lid. . . . . . . . . . . . . . . . . . . . . . . . . .
3D rendering of the enclosure. . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel-to-serial converter breadboard test results. . . . . . . . . . . . . .
A.1 Schematic
A.2 Schematic
A.3 Schematic
A.4 Schematic
A.5 Schematic
A.6 Schematic
A.7 Schematic
A.8 Schematic
A.9 Schematic
A.10 Schematic
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
B.9
diagram,
diagram,
diagram,
diagram,
diagram,
diagram,
diagram,
diagram,
diagram,
diagram,
Fabrication
Fabrication
Fabrication
Fabrication
Fabrication
Fabrication
Fabrication
Fabrication
Fabrication
top level. Top Level.SchDoc . . . . . . . . . .
clocks. CLK.SchDoc . . . . . . . . . . . . . . .
digital. . . . . . . . . . . . . . . . . . . . . . .
flip-flops and board select comparator. . . . .
parallel-to-serial converter. . . . . . . . . . . .
AD9912. . . . . . . . . . . . . . . . . . . . . .
power 1 (voltage regulators). . . . . . . . . . .
power 2 (bypass capacitors and ferrite beads).
analog. . . . . . . . . . . . . . . . . . . . . . .
reconstruction filter. . . . . . . . . . . . . . . .
Drawings,
Drawings,
Drawings,
Drawings,
Drawings,
Drawings,
Drawings,
Drawings,
Drawings,
top copper layer. . . . .
ground plane (negative).
power plane (negative). .
bottom copper layer. . .
top silkscreen. . . . . . .
bottom silkscreen. . . . .
top soldermask. . . . . .
bottom soldermask. . . .
drill drawing. . . . . . .
v
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43
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47
LIST OF FIGURES
C.1 3D Rendering of the DDS, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2 3D Rendering of the DDS, bottom view. . . . . . . . . . . . . . . . . . . . . . . . . .
C.3 3D Rendering of the DDS, angled view. . . . . . . . . . . . . . . . . . . . . . . . . .
vi
48
49
50
List of Tables
2.1
2.2
2.3
2.4
2.7
Serial control port instruction word bit functionality. . . . . . . . . . . . . . . . . . .
AD9912 byte transfer count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample DDS Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of connection pads available on the Printed Circuit Board (PCB) designed for
BNC Connector mounting. Note that only J3, J5 and J6 are intended for mass
production, and the enclosure design reflects this. . . . . . . . . . . . . . . . . . . . .
Options for Power-Up Default Frequencies on the AD9912 . . . . . . . . . . . . . . .
Recommended Loop Filter Values for a Nominal 1.5 MHz SYSCLK PLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
4.2
Financial Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDS Enclosure Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
2.6
D.1 Bill of Materials
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vii
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26
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31
51
Glossary
AD9852 is a DDS IC produced by Analog Devices, with a maximum system clock of 300MHz.
AD9912 is Analog Devices’ highest-performance DDS IC, with a maximum system clock of 1GHz.
DDS is a device capable of digitally generating sinusoidal waves with programmable frequency and
phase.
ferrite bead is a passive component which is primarily resistive at high frequencies. Therefore,
they act to block high-frequency noise and are useful as an inexpensive means of isolating
noisy power supply groups.
FSC is a digitally programmable 10-bit scale factor that sets the peak output current of the AD9912
Digital-to-Analog Converter (DAC)[3].
prepreg is a shorthand term for pre-impregnated material. In this report, it is a name for the
dielectric material placed between copper layers on a PCB.
via is a connection between one or more copper layers on a PCB.
viii
Acronyms
CSB Chip Select Bit.
DAC Digital-to-Analog Converter.
DAQ Data Acquisition System.
DIP Dual In-line Package.
EMI Electromagnetic Interference.
FTW Frequency Tuning Word.
IC Integrated Circuit.
LDO Low-Dropout.
NI National Instruments.
PCB Printed Circuit Board.
PHAS Department of Physics and Astronomy.
PLL Phase-Locked Loop.
QDG Quantum Degenerate Gasses.
SMD Surface-Mount Devices.
UTBus University of Texas Bus.
VCO Voltage-Controlled Oscillator.
ix
Acknowledgements
We’d like to thank Kirk Madison and Jon Nakane for taking their time to review our in-progress
designs. Extra thanks to Kirk having enough confidence in us amateur PCB designers to fund the
project. Thanks to Will Gunton for being our reliable contact at the QDG lab and for administrating
the purchasing for the project. Thanks to Pavel Trochtchanovitch, Richard, Gar and Dave at the
PHAS electronics shop for assembling our boards and having patience when our instructions didn’t
make sense. Extra thanks to Richard for spending time on several occasions to review out PCB
layout.
x
1
Introduction
The Quantum Degenerate Gasses (QDG) Laboratory at the University of British Columbia investigates the applications of ultra-cold gases to the physics of many-body quantum systems [8]. One
such investigation attempts to trap, isolate and precisely control the movement of ultra-cold atoms.
Naturally, this experiment requires precise control of experimental conditions. To achieve this,
they employ a complex computer-controlled electronic system. Contained within this control system
are several devices called Direct Digital Synthesizer (DDS)s. The current generation of these devices
are designed by Todd Meyrath and are capable of producing radio frequency signals between DC
and 135MHz [9]. Todd Meyrath’s device is shown in Figure 1.1. The DDSs are based around the
Analog Devices 9852 (AD9852), a highly integrated 300MBPS CMOS digital synthesizer. This IC
provides a highly stable frequency-, phase-, and amplitude-programmable cosine output[2].
Other key features of the AD9852 are the ability to internally multiply an external clock up to
a maximum of 300MHz (20 × 15MHz) and an output update of speed up to 108 Hz. The AD9852
supports Phase-Shift Keying (PSK) and Frequency-Shift Keying (FSK), which allow switching between two pre-programmed phases or frequencies based upon the level of a digital signal. Further,
a high-speed integrated analog comparator allows the AD9852 to be used as a programmable clock
source.
The QDG lab requires eight devices capable of analog sinusoidal outputs with programmable
frequencies of up to 400MHz. These devices will be used to control acousto-optic modulators, which
can be used to precisely control the frequency of the laser beams. The QDG lab uses these lasers to
control ultra-cold atoms in experiments that are beyond the scope of this document.
To fit the lab requirements, this project aims to redesign, implement and test a new DDS device,
the AD9912, which replaces the AD9852 microchip with a similar chip, the AD9912. This IC is a
newer and faster edition of the AD9852 - a 1GBPS digital synthesizer capable of producing radio
frequency signals at frequencies of up to 400MHz and an output update speed of up to 2MHz. To
simplify usage in the lab, the AD9912-based DDS device must support the existing AD9852 DDS
device control interface.
As the AD9912 is a faster IC than the AD9852, it has several requirements that make a designing
an AD9912-based DDS device more challenging. For example, the higher speed signals involved
require much more careful impedance control of the signal lines than the AD9852 DDS devices.
There are feature differences as well: the AD9912 does not support PSK or FSK, though the AD9852
does, and supports serial programming in place of a parallel control bus. The AD9912 also requires
voltage supplies at 1.8V on top of the 3.3V the AD9852 required. Like the AD9852, the AD9912’s
output must be filtered to remove noise resulting from the digital synthesis process; this filter must
be designed and characterized.
Due to these differences, the design for DDS device built for this project did not begin with the
AD9852 DDS device. Instead, the design began with the AD9912 evaluation board. This is evident
in the analog portion of the AD9912 DDS device, which uses similar structure and components
choice as the evaluation board. However, the AD9912 DDS device did draw inspirations from the
AD9852 device[9]. In particular, the digital control and power circuitry design is heavily based upon
1
1. INTRODUCTION
2
the AD9852 device and the overall PCB layout is very similar.
To house the DDS device, an enclosure must be designed. This should securely fasten the AD9912
DDS device, provide noise isolation and be compatible with the rack mount solution used for the
AD9852. Both the enclosures and the front panel mounting mechanism should be ordered.
This project is sponsored by Dr. Kirk Madison, Assistant Professor with the department of
Physics and Astronomy at The University of British Columbia and head of the QDG Laboratory.
This report is organized into several chapters: Discussion, Conclusions and Project Deliverables.
A chapter on recommendations will be included with Part II of this report. The Discussion is
broken into Theory of Operation, PCB Layout Considerations, Design and Fabrication Methods,
Board Features and Breadboard Testing. The Discussion aims to provide a quantitative description
of the expected operation of the device and give insight into the methodology of the design process.
The Conclusions provide closure to the report, summarise the important results and findings. The
Project Deliverables describe the physical and electronic results of this project which are to be handed
over to the QDG Laboratory. Finally, the Appendices present the design schematics, fabrication
drawings, 3D renderings of the PCB and a full parts list.
1. INTRODUCTION
Figure 1.1: Photo of the 150MHz AD9852-based DDS designed by Todd Meyrath[9].
3
2
Discussion
2.1
Theory of Operation
This section will begin by giving an overview of the functionality of the device. Next, the internal
workings of the AD9912 IC itself will be discussed, providing an understanding what to expect from
the IC’s RF and clock outputs. Afterwards the supporting circuitry will be described block by block,
returning as needed to the AD9912 IC to explain related concepts.
2.1.1
Device Overview
The device is designed to generate a sinusoidal or square output signal with a frequency of up to
400MHz. The frequency and phase of both output signals can be rapidly digitally programmed (but
not independently). The output signal is generated by the AD9912, a high-performance, low-noise
14-bit DDS[3].
The sinusoidal output is filtered through a 400MHz low-pass filter to remove unwanted highfrequency noise. Depending on board configuration, the filtered RF signal can then be taken as
the primary device output or it can be brought back to the AD9912 to become the input signal for
either of the AD9912’s two clock drivers - the CMOS output driver and the HSTL output driver
(see Section 2.1.4).
Figure 2.1 is a high-level block diagram of the newly designed AD9912-based DDS device. The
block diagram shows all existing BNC connection pads. Only three of these are intended for use in
the finished devices. These are SYSCLK, the system clock input, RF, the sinusoidal signal output
and CMOS, the CMOS clock driver output. The remaining connections are intended primarily for
testing.
Significant omissions from the block diagram are the Phase-Locked Loop (PLL) loop filter (see
Section 2.1.5.3) and the voltage regulation circuitry (see Section 2.2.2).
2.1.2
The AD9912 Direct Digital Synthesizer
Figure 2.2 is a block diagram showing the core internal functionality of the AD9912, reproduced
from the datasheet[3]. This diagram consists of three main blocks: the 48-bit accumulator, angle to
amplitude conversion and the DAC. fs is the DAC sample rate[3].
Each cycle of fs , the accumulator increments its running total by the 48-bit value of the Frequency
Tuning Word (FTW)[3]. The accumulator will periodically reach its maximum value (248 ) and roll
over. The rate of roll over is equal to the frequency of the sinusoidal output, fDDS , and is given by
fDDS =
FTW
fs [3].
248
(2.1)
Equation 2.1 can be solved to give
F T W = round(248 (
4
fDDS
))[3].
fs
(2.2)
2. DISCUSSION
Parallel Data
Input
16
6
Address
Data
Strobe
SZ
5
10-Pos DIP Switch
6
4
DAC_OUT
Board
Address
Board
Address
Comparator
Parallel-toSerial
Converter
Reconstruction Filter
(400 MHz Low-Pass)
RF
DAC_OUT/
DAC_OUTB
Startup
Config
SDIO
CSB
FDBK_IN/
FDBK_INB
SCLK
FDBK_IN
AD9912
OUT_CMOS
CMOS
SCLK
Clock
Oscillator
(~25MHz)
OUT/OUTB
SYSCLK/
SYSCLKB
OUT_N
OUT_P
SYSCLK
Figure 2.1: Block diagram of the full DDS device, showing input and outputs. Switches are implemented as 0Ω resistors. The crystal oscillator shown is optional and replaces the external SYSCLK
input.
The output of the accumulator is offset by the 14-bit value Phase Offset. This results in a phase
offset to fDDS of ∆Φ given by
∆phase
∆Φ = 2π(
)[3].
(2.3)
214
Both the FTW and the Phase Offset can be digitally controlled by the user (see Section 2.1.6),
allowing the frequency and phase of the output sinusoid to be controlled with 48 and 14 bits of
precision, respectively. This corresponds to increments of approximately 3.6µHz (at fs = 1GHz)
and 3.8 × 10−4 rads.
After the phase offset, the accumulator output (which is a digital representation of the phase of
the output sinusoid) is converted to a 14-bit digital value representing the amplitude of the output
sinusoid. The DAC then converts this value to an analog differential signal pair (DAC OUT/
DAC OUTB). The frequency, phase and peak output current (see Section 2.1.2.1) of this signal are
digitally controllable. It will be transformed into a single-ended signal and low-pass filtered (see
Section 2.1.3) before becoming the output RF signal of the DDS device.
2. DISCUSSION
2.1.2.1
6
DAC Peak Output Current
The peak output current of the DAC is determined by two factors: a reference current on the
DAC RSET pin (IDAC RESET ) and a digitally programmable 10-bit scale factor referred to as the
FSC[3]. The DAC RSET pin is internally connected to a reference voltage of 1.2V and externally
connected to ground through the resistor RDAC REF (R26 on the PCB), and therefore
IDAC
REF
=
1.2V
[3].
RDAC REF
The AD9912 datasheet recommends IDAC REF = 120µA which implies taking RDAC
10kΩ.
The DAC full-scale output current (IDAC F S ) is given by
IDAC
FS
= IDAC
REF (72
+
192F SC
)[3].
1024
(2.4)
REF
=
(2.5)
Digital control of the FSC allows the DAC output current to be digitally controlled in increments
of 0.1875µA from a minimum of 8.64µA to a maximum of 31.68µA1 .
Figure 2.2: Block diagram showing internal functionality of the AD9912, reproduced from the
datasheet[3].
2.1.3
RF Output and the Reconstruction Filter
The AD9912’s DAC produces a sampled reconstruction of the desired sinusoidal signal. A basic
result in Fourier Analysis says that this reconstructed signal contains both the desired baseband
signal, extending from DC to the Nyquist frequency (fs /2), as well as images of this baseband signal
which appear periodically at intervals of fs /2 and theoretically extend to infinity[3].
Note that the first unwanted image is that of the baseband signal, mirrored about fs /2. This
means that as the DDS output frequency is increased, the frequency of the fundamental spur in
the first image decreases. For example, if the DDS output frequency is 400MHz, the first spur will
appear at 600MHz. At an output frequency of 490MHz, the first spur will appear at 510MHz. So
as the output frequency increases, the requirements on the filter become more stringent. The result
is a practical limitation on the DDS output frequency which is less than the Nyquist frequency of
fs /2. The actual limit will depend upon the properties of the filter used and the requirements of
the application.
Our application desires only the baseband signal, and therefore the DAC output must be low-pass
filtered to remove higher frequency noise. This filter is referred to as the reconstruction filter. It is
desired that this filter have a cut-off frequency of 400MHz, as steep a roll-off as possible (rejection
at 500MHz is desired) and very good rejection in the stop-band (60dB attenuation at a minimum).
1 This follows from Equation 2.4. Comparably, the datasheet’s AC specifications table gives the DAC’s typical and
maximum full-scale output current as 20µA and 31µA, respectively.
2. DISCUSSION
7
Following from the AD9912 evaluation board design, a 50Ω surface mount RF transformer
(ADT2-1T-1P+, Mini-Circuits) is used to transform the differential signal pair of Figure 2.2 (DAC OUT/
DAC OUTB) into a single-ended signal prior to filtering[4]. A single-ended filter design is less susceptible to component variations than its differential counterpart[4]. A differential filter design might
be more appealing to users who were only interested in the clock generation feature of the AD9912
(see Section 2.1.4), not the RF output, since no transformers would be required. However, our
application requires a single-ended RF output, and so one the transformer would still be required.
Note that the RF transformers have a (7 × 8)mm2 footprint and cost approximately $4.25.
Note that since transformers do not function at low frequencies, the RF output will be attenuated
at very low frequencies and will not function near DC2 . The ADT2-1T-1P+ RF transformers are
rated for frequencies in the range of 8 to 600 MHz.
The reconstruction filter design is based on that of the AD9912 evaluation board, Rev. B3 . It is
a 7th-order passive elliptic low-pass filter, shown in Figure 2.3.
2.1.3.1
SPICE Verification
The reconstruction filter design was verified through a SPICE simulation (AC Analysis in NI MultiSim v11.0). Figure 2.3 shows the schematic used for SPICE simulation and Figure 2.4 shows the
resulting transfer function.
As we can see from the transfer function, the cut-off frequency is 400MHz, the roll-off occurs in
100MHz and the stop-band attenuation is about 60dB. The data used to generate the plot shows
that the pass-band ripple is a maximum of about 1.5dB.
Figure 2.3: Reconstruction filter schematic used for SPICE simulation. This is a 7th order elliptic
low-pass filter with a 400MHz cut-off frequency. Designators were taken to match the PCB.
2.1.4
Clock Drivers
The AD9912 has two on-board clock drivers, the CMOS output driver and the HSTL output driver.
These clock drivers share the differential FDBK IN/FDBK INB inputs and effectively serve to transform the filtered sinusoidal DAC output into a square clock signal. A second ADT2-1T-1P+ RF
2 This is not a concern for the QDG lab, as the existing AD9852-based devices function at frequencies from DC to
135MHz[9].
3 Rev. A uses a 240 MHz low-pass filter with very similar design.
2. DISCUSSION
8
Magnitude (dB)
Magnitude Plot
0
−20
−40
−60
−80
−100
−120
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
Frequency (MHz)
Phase (deg)
Phase Plot
180
135
90
45
0
−45
−90
−135
−180
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
Frequency (MHz)
Figure 2.4: Reconstruction filter frequency-domain transfer function generated from a SPICE simulation of the circuit shown in Figure 2.3
transformer is used to transform the single-ended filter output into a differential signal suitable for
the FDBK IN/FDBK INB inputs.
The CMOS output driver provides a CMOS-level clock signal and is suitable for frequencies
in the range 8kHz to 150MHz[3]. The device can be configured at component population to have
a CMOS voltage of either 3.3V or 1.8V (see Section 2.4). The CMOS output driver includes an
integer divider which can be enabled or bypassed. When bypassed, the CMOS output frequency is
the same as the signal on the FDBK IN/FDBK INB inputs. When enabled, this frequency can be
reduced. At frequencies below 30MHz, noise on the CMOS output can be reduced by enabling the
CMOS divider and running the DAC at a higher frequency[3]. See the AD9912 datasheet for more
information.
The HSTL output driver provides a 1.8V differential clock signal and is suitable for frequencies
in the range 20MHz to 725MHz[3]. Frequencies above the Nyquist rate fo the AD9912 are achieved
with a 2× frequency multiplier. The datasheet claims a duty cycle between 48% and 52%, while the
CMOS driver’s duty cycle is given as being between 45% and 55%. Note that unlike the AD9852,
the AD9912 does not support digital control of the duty cycle of the output clock.
2.1.5
Clock Inputs
The DDS device has two clocks on-board. These are referred to as SYSCLK and SCLK. SYSCLK
drives fs , the internal DAC sample rate of the AD9912. The frequency of fs is directly proportional
to the output frequency of the DDS. If PLL is enabled on the AD9912, fs can be made to have
a frequency up to 66 times greater than that of SYSCLK. SCLK is the digital control clock and
controls the frequency of the AD9912’s serial control interface.
2. DISCUSSION
2.1.5.1
9
SCLK
SCLK controls the frequency of the AD9912’s serial control input. This clock is also used to convert
the incoming digital programming parallel signal into the serial signal used by the AD9912. Our
implementation allows for two possible sources for SCLK: an external connection and an on-board
clock oscillator (TXC 7C Series). The external connection is intended for testing purposes, particularly to determine the maximum frequency at which the serial input can reliably operate (see next
paragraph). Once this frequency has been determined, an appropriately selected TXC 7C IC will
be placed on board and used as SCLK.
An important note is that the TXC 7C datasheet does not specify whether the enable pin is
active high or active low. The board includes jumpers to allow for both possibilities; see Section 2.4
for information on switching between these two options.
According to the AD9912 datasheet SCLK is limited to a maximum of 50MHz[3]. However, the
maximum value of SCLK will likely be limited by the digital control logic and not the AD9912.
Timing analysis based upon information in all relevant components’ datasheets suggests that the
maximum SCLK frequency should be around 25MHz; see Section 2.1.6 for details.
2.1.5.2
SYSCLK
SYSCLK is the main system clock. The DAC sample rate, fs , is controlled by SYSCLK. As discussed
below, the AD9912 has PLL multiplier circuitry which allows fs to be up to 66 times greater than
the frequency of SYSCLK. From the AD9912 datasheet, fs is limited to a maximum of 1GHz, so
the SYSCLK and PLL multiplier must be carefully chosen to be less than this speed[3].
The AD9912 supports the use of either a crystal oscillator or a clock oscillator; the DDS device
supports both an on-board crystal oscillator and an external clock source (recommended). Depending
on which is to be used, the jumpers necessary to connect the clock source or crystal oscillator to the
AD9912 must be installed; see Table 2.7.
2.1.5.3
PLL
The AD9912’s PLL circuitry allows the frequency of SYSCLK to be increased by any even multiple
between 4 and 66. This circuitry generates an internal clock using a Voltage-Controlled Oscillator
(VCO). The voltage that controls the VCO is generated by a current pump and an external loop
filter consisting of components defined in Table 2.6 and is related to the phase difference between
the internal clock, divided by a number set by the PLL register, and the SYSCLK. The voltage then
raises and lowers to converge the internal clock on a set multiple of the SYSCLK[3].
The AD9912 PLL also includes a frequency doubler before the PLL circuitry itself. This functionality creates a clock pulse on both the rising and falling edge of SYSCLK, doubling the frequency.
Using the frequency doubler creates a clock output that has an improved phase noise performance
over simply using double the PLL multiplier instead. Unfortunately, the frequency doubler does not
produce a clean rectangular pulse with constant duty cycle. That is, subharmonics are introduced at
multiples of the SYSCLK input frequency. The PLL multiplier should be chosen to suppress these
subharmonics[3].
Using the PLL allows for a slower clock to be used as the input to the DDS device. Slower clock
sources are much cheaper and easier to acquire. However, the PLL will introduce additional noise
and inaccuracy into the system, especially as the PLL multiplier approaches the maximum of 66×.
The ideal configuration of the PLL loop filter depends on the multiplier to be used. If PLL is to
bypassed, then the loop filter can also be bypassed. See Section 2.4 for details.
2.1.6
Digital Control
The devices are controlled through an existing parallel interface called the University of Texas Bus
(UTBus). Custom circuitry on board our devices has been designed to interface the parallel UTBus
with the AD9912’s serial control port. This section will describe the UTBus, the serial control port
and the custom interface between the two.
2. DISCUSSION
2.1.6.1
10
The UTBus
The UTBus is an existing parallel programming interface used by the QDG lab and based upon
Todd Meyrath’s work[9]. As the UTBus is already in use in the lab4 , supporting this interface was
a design requirement.
The interface uses ribbon cable and a 50-pin Molex connector with pin functionality as defined
in Figure 2.5. As shown, these 50 pins are divided into 25 grounded pins, 8 address bits, 16 data bits
and one additional bit, called the strobe. The 8 address bits are used to specify which device should
receive the 16 bit command. The strobe bit is effectively a clock with a 1/3 duty cycle; when the
strobe bit is high, the address and command are guaranteed to be stable. The UTBus address and
data pins are asserted for three distinct periods with equal length: once, while the strobe remains
low, a second time while the strobe is high, and a third time while the strobe is low[7]. These three
periods together comprise one UTBus command. This timing is illustrated in Figure 2.6.
Figure 2.5: Diagram of the 50-Pin UTBus Connector, reproduced from [9].
Figure 2.6: Timing diagram for the UTBus, showing the strobe, address, data and NI-DAQ clock.
Each command sent to a device requires three periods of the NI-DAQ clock to complete. Reproduced
from Keith Ladouceur’s Master’s Thesis[7].
The QDG lab currently uses an NI-DAQ, controlled by a desktop computer running a custom
python script, to drive the UTBus. Current uses of the UTBus send one command at a time, with
an NI-DAQ clock frequency of up to 5MHz.
4 The UTBus is used to control various devices in the QDG lab, including analog output devices and the existing
AD9852-based DDSs[7].
2. DISCUSSION
2.1.6.2
11
The AD9912’s Serial Control Port
In contrast with the parallel programming interface of the AD9852, which was used on the previous
generation of DDS devices, operation of the AD9912 is controlled through a serial interface. This is
inconvenient from a design standpoint because the UTBus provides 16 bits of data in parallel and
no suitable clock. Section 2.1.6.3 describes the hardware solution which interfaces the UTBus with
the serial control port.
A detailed discussion of the serial control port is given in the AD9912’s datasheet, including
multiple timing diagrams. Here we summarize the essential elements.
The serial control port of the AD9912 consists of four pins: a clock (SCLK), an I/O pin (SDIO),
an active-low control pin which gates the I/O cycles (Chip Select Bit (CSB)) and an output pin
(SDO). SDO is unnecessary for our application and has been left unconnected on the board5 .
Control of the AD9912 is established through the writing of binary data to various registers. Each
register has a unique 13-bit address and some functionality which is documented in the datasheet.
For example, the DDS output frequency can be controlled by writing to the 48-bit register containing
the FTW. Note that all registers are not equal in size.
Each communication cycle consists of two parts: the writing of a 16-bit instruction word and the
reading of or writing to a register. Table 2.1 shows the 16-bits of the instructions words mapped
to their corresponding bits in the UTBus. The instruction word contains a 13-bit register address
(A12,. . . ,A0), two bits indicating the length of the coming data transfer (W1 and W0, see Table
2.2) and a single bit indicating whether the transfer is to be a read or a write (R/W ). Note that
our device supports only only one- and two-byte transfers and does not support reads. Writing to
registers larger than two bytes will require multiple communication cycles.
Table 2.1: Serial control port instruction word bit functionality. D0,. . . ,D15 correspond to
DAT0,. . . ,DAT15 in our design and schematics (see Figures A.3 and A.5). The last row corresponds
to the 16 bits of the instruction word. Adapted from the AD9912 datasheet[3].
MSB
LSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Table 2.2: Decoding of the W1 and W2 bits in an instruction sent the AD9912’s serial control port.
These two bits control the number of bytes to be transferred in the current communication cycle and
describe the number of bytes transferred in this command cycle, excluding the 2-byte instruction.
W1 and W0 correspond to the DAT14 and DAT13 data bits on the UTBus, respectively. Note
that the AD9912 DDS device does not support all byte lengths. Reproduced from the AD9912
datasheet[3].
W1 W0 Bytes to Transfer Supported?
0
0
1
Yes
0
1
2
Yes
1
0
3
No
1
1
Streaming mode
No
The CSB must be held low in order for the AD9912 to recognize data on the SDIO. Accordingly,
the CSB should be held low during writing of the instruction word. Afterwards, the CSB can remain
low and data transfer can begin immediately. Alternatively, the CSB can be brought high to disable
the serial control port until the user is ready to transfer data. Data transfer is similar: the CSB must
be held low during the writing of each byte of data. Between each byte, the CSB can be brought
high to pause the transfer if desired6 .
5 Actually, the pin itself is connected to a trace leading away from the AD9912 IC and to a via. This is to facilitate
testing.
6 Streaming mode is an exception to this; during streaming mode, a rising edge on the CSB indicates the end of
the communication cycle.
2. DISCUSSION
12
Some registers on the AD9912 are buffered so that writing to these registers does not affect
the device output until an I/O update operation is performed to transfer the data from the buffer
registers to the control registers. This can be accomplished by toggling the IO UPDATE pin or by
writing a 1 to the register update bit. To simplify the design of the interface between the UTBus
and the serial control port, the IO UPDATE pin is disabled on our devices, and so the latter method
will be used in practice. In practice, the CSB will be brought high between commands sent on the
UTBus in order to stall the communication cycle and allow time for the UTBus to send the next
command.
2.1.6.3
Parallel-to-Serial Converter
Schematics for the parallel-to-serial converter are shown in Figures A.3, A.4 and A.5.
An 8-bit comparator is used to compare bits A7 to A2 of the UTBus address bits (the lower
2 bits are not used as addresses) against the board address. The board address, which can be set
using a Dual In-line Package (DIP) switch, is a 6-bit address which should be unique for each device
connected to the UTBus. If the address bits match the address set on the DIP switch, a custom
arrangement of flip flops listens for a rising edge on the strobe bit. When this happens, a pulse is
generated that latches the 16 bit command into two SN74HC166 8-bit shift registers. These 8-bit
shift registers are daisy-chained together to form a 16-bit shift register.
Once the data is loaded in, the shift registers output the UTBus data into the AD9912’s serial
port one bit at a time beginning with DAT0. The number of data bits clocked into the AD9912 is
an option set by the UTBus address bus bit 1 (A1), renamed to SZ in our schematics. The SZ bit
switches between using all 16 bits of the data bus (SZ=0) or only the lower 8 bits of the data bus
(SZ=1). The SZ bit will be critical when programming the AD9912; see Section 2.1.6.4.
To implement the switch between 8 and 16 bits, the DDS device design takes advantage of the
CSB pin on the AD9912. Since the AD9912 can only be programmed when the CSB is held low,
the DDS device ensures that the CSB is only held low for either 8 or 16 bits. This is accomplished
by using a mirrored set of SN74HC166 8 bit shift registers. These second set of shift registers are
loaded with either all logic low, or 8 bits of logic low followed by 8 bits of logic high. The output
from these shift registers is directly connected to the CSB and is clocked out at the same time as
the shift registers containing the command. This ensures that the AD9912 is only able to receive
data on the serial port for exactly the time it takes to clock in one of 8 or 16 bits.
Parts of this circuit have been prototyped and tested; see Section 2.5. A timing diagram is
presented in this section using the data collected; see Figure 2.19.
2.1.6.4
Programming
Programming the DDS device consists of sending a series of commands on the UTBus. On each
command, 8 or 16 bits of data on the UTBus are clocked into the DDS one bit at a time beginning
with DAT0. The UTBus address bit A1 (renamed to SZ in our schematics) controls the length of
the data transfer (low for a 16-bit transfer). Thus (see Section 2.1.6.2), each communication cycle
with the AD9912 requires two commands to be sent on the UTBus. The first command sent will
always be 16-bits and tells the AD9912 which register is to be written to as well as how much data
is to be written (8 or 16 bits; see Table 2.2). The second command can be either 8-bits or 16-bits
and is the actual data to be written to the register addressed previously.
If the register being written is a buffered register (see Section 2.1.6.2), an additional register must
be written to update the DDS output. This can be done immediately or after multiple registers
have been written to.
If the register to be written to is larger than 16-bits, multiple communication cycles are required,
as illustrated in the example below.
The following is an example of a series of commands to set the FTW to 68DB8BAC716 7 (FTW
controls the output frequency; see Section 2.1.2). With fs =1GHz, this sets the AD9912 output to
100MHz. The FTW is 48 bits, and so requires 3 communication cycles to completely overwrite. The
7 68DB8BAC7
16
= 0000 0000 0000 0110 1000 1101 1011 1000 1011 1010 1100 01112
2. DISCUSSION
13
fourth communication cycle shown below is a write to the I/O Update register, which causes the
output frequency to be updated. The address and strobe bits are not shown.
Table 2.3: Sample DDS Device Commands to set the output frequency to 100MHz and subsequently
update the output. The first 6 commands set the FTW to the value required for at output frequency
of 100MHz, while the last two commands tell the AD9912 to update the output.
Data
SZ 0-3
4-7 8-11 12-15 Description
0
0010 0001 1010
1011
Send (0) the next two bytes (01) of data to register 01AB16
(0001101010112 ), the register containing the top 8 bits of
the FTW
0
0000 0000 0000
0110
Write 000000002 to register 01AB16 and 000001102 to register 01AA16
0
0010 0001 1010
1001
Send (0) the next two bytes (01) of data to register 01A916
(0001101010012 )
0
1000 1101 1011
1000
Write 100011012 to register 01A916 and 101110002 to register 01A816
0
0010 0001 1010
0111
Send (0) the next two bytes (01) of data to register 01A716
(0001101001112 )
0
1011 1010 1100
0111
Write 101110102 to register 01A716 and 110001112 to register 01A616 , bits 15:8 of the FTW
0
0000 0000 0000
0101
Send (0) the next byte (00) of data to register 000516
(00000000001012 ), the IO UPDATE register that tells the
AD9912 to update the output
1
1000 0000 0000
0000
Write 1 to the 1 bit IO UPDATE register
2.1.7
Power Management
The AD9912 has stringent power requirements to ensure the highest-performance operation. Both
3.3V and 1.8V power supplies are needed. While it would be possible to implement an AD9912based device using only two power rails, the datasheet highly recommends isolation between each
group of power supplies on the AD9912. The extent to which isolation is required depends on the
requirements of the application. See Power Supply Partitioning in the AD9912 datasheet for a
detailed description of which pins can be grouped together and which should be isolated.
The isolation between power supply groups can be achieved by using separate regulators for each
group or by placing a ferrite bead between a common regulator and each rail. Separate voltage
regulators provide better isolation but require more PCB area, increase the cost of the device8 and
increase the power consumption of the device9 . Our design uses four regulators, two at each of 1.8V
and 3.3V, each separated into the broad groups analog and digital. Five ferrite beads are then used
to isolate five power supply groups, each sourcing from the 1.8V analog regulator. See the schematics
shown in Figures A.7 and A.8.
The CMOS clock driver power supply (VDD CMOS) can either be connected to the analog 3.3V
regulator through a ferrite bead (F4) or to the analog 1.8V regulator through a 0Ω jumper (W14)10 ,
depending on the desired CMOS output voltage level.
All power pins on the AD9912 and digital logic ICs have a 0.1µF bypass capacitor connected as
close as possible to the supply connection. Bypass capacitors serve as power reservoirs, providing
instantaneous power to the IC. They prevent that power from needing to travel over a long connection
to the voltage regulator, introducing delays due to parasitic inductance of the traces involved. Instead
8 The
cost of each high-performance Low-Dropout (LDO) voltage regulator used was about $4.50.
is not a significant concern for this application.
10 See the datasheet for more information on the CMOS power supply recommendations. W14 uses the same 0805
package as the ferrite beads, allowing a ferrite bead to be used instead of a jumper if desired.
9 This
2. DISCUSSION
14
the power comes directly from the capacitor, which is placed as close as possible to the IC in order to
minimize parasitic inductance. This capacitor is then recharged by power from the voltage regulator
at a speed much closer to DC.
2.2
PCB Layout Considerations
Major sources of inspiration were the AD9912 evaluation board and Todd Meyrath’s AD9852
design[9] (shown in Figure 1.1). Here we discuss the components chosen for the DDS device, the
considerations needed for power management, techniques for managing heat and how trace widths
were chosen to ensure signal integrity.
2.2.1
Components
All parts and components used on the DDS device were selected and sourced, beginning by considering the components used on either the AD9912 evaluation board or Todd Meyrath’s AD9852
design[9]. Many of these parts were re-used, as reflected in the complete Bill of Materials, which is
given in Appendix D.
For this application, Surface-Mount Devicess (SMDs) were preferred to through-hole components
due to reduced inductances and the possibility of higher component density, which is ideal for high
frequency design[10]. For these reasons (and following the example of the AD9912 evaluation board
and the old AD9852 DDS), most components on our board are surface-mount. There are only
three through-hole components: the 50-pin Molex UTBus connector, the 3-pin Molex power connector (5V) and the 10-Pos switch (sets the board address and the AD9912 start-up configuration).
Component choice for the UTBus and power connectors is compatible with those used in previous
generation devices.
Most common passive components use either 1206 (3.2mm×1.6mm) or 0402 (1.0mm×0.51mm)
surface-mount packages. The 1206 packages is preferred for its larger footprint11 , but 0402 is preferred near the AD9912 IC in order to shorten the trace lengths between the AD9912 IC and its
bypass capacitors12 .
Most components are placed on the top side of the board. Bottom-side components are limited
to resistors, capacitors and ferrite beads.
The BNC connectors are mounted to the enclosure and solder directly to 2.54×6.35mm pads on
the PCB. This design is identical to that used in Todd Meyrath’s AD9852 design[9].
The linear regulators used for this board (Texas Instruments TPS78633 and TPS78618) were
selected due to their proven use in Todd Meyrath’s AD9852 design[9]. These are fixed-voltage 1.5A
LDO voltage regulators suitable for use with a 5V supply. Four regulators are used. See Section
2.1.7 for more information.
2.2.2
Power Plane
The third layer of the 4-layer PCB is a dedicated power plane, shown in Figure 2.7. This power plane
was split into five regions. Around the outside perimeter of board is a 5V plane which is supplied
by the 3-pin external power connector. A 470µF tantalum capacitor near the connector stabilizes
this supply and ensures constant voltage levels. The 5V supply is used by the four on-board linear
power regulators which power the remaining four regions.
The left side of the power plane (labelled Digital 3.3V) is used to supply a 3.3V signal to the
digital components which provide the digital interface between the UTBus and the AD9912. The
Digital 3.3V power plane also provides power for the AD9912’s serial control port.
The three other power planes (Digital 1.8V, Analog 1.8V and Analog 3.3V) provide power to
the appropriate sections of the AD9912 IC. These are all required to be independently supplied and
11 The
small 0402 footprint requires a steady hand and some skill in order to install manually.
reduce Electromagnetic Interference (EMI), a Texas Instruments white paper recommends that the length-towidth ratio of traces between an IC and its voltage source should not exceed 3:1[10].
12 To
2. DISCUSSION
15
there are stringent requirements on bypass capacitors and ferrite beads, as listed by the AD9912
datasheet. These recommendations have been followed wherever practical.
5V
Digital 1.8V
Analog 3.3V
Digital 3.3V
5V
Analog 1.8V
5V
Figure 2.7: The PCB power plane design. This is a negative fabrication image; black areas indicate
removal of copper. The plane is split into five region, labelled in the figure. There are analog and
digital 1.8V and 3.3V power planes as well as a 5V plane which serves to supply the four on-board
LDO voltage regulators. The PCB areas taken up by each voltage regulator and bypass capacitors
are shown outlined in dashed green lines.
2.2.3
Heat Dissipation
Power dissipation is an important consideration for the voltage regulators and the AD9912. Both
ICs have grounded thermal contacts which are to be soldered directly to copper fills on the top side
of the PCB. As recommended by both ICs’ datasheets, an array of thermal vias is located under each
of these pads and serves to conduct heat away from the ICs. All empty areas on the bottom side of
the PCB are ground-filled and this serves to increase the heat capacity. Areas on the bottom layer
which are to be in contact with the aluminium enclosure have the insulating soldermask removed,
increasing heat transfer to the enclosure (as well as grounding the enclosure). Figures 2.10 and 2.11
show the full PCB layout from the top and bottom sides.
2.2.4
Characteristic Impedance and Trace Width
Characteristic impedance is the instantaneous impedance of a PCB trace. It is the impedance that
a high-speed signal will encounter as it propagates along a trance, charging up the metal of the trace
as it goes. This charging is essentially charging a capacitor where the signal trace is the top of the
capacitor, the PCB prepreg is the dielectric and the ground plane is the bottom of the capacitor[1].
As the signal’s edge travels along the trace, it charges the trace itself before encountering any other
electrical components.
If the trace impedance is different from the source or destination impedance, it is possible that the
signal’s energy will not be completely transferred, with some of the energy returning back through
the trace. This can cause constructive or destructive interference, resulting in a less accurate signal.
2. DISCUSSION
16
To avoid this, our design ensured that high-frequency signal traces were 50Ω. 50Ω is a common
standard and matches the input impedance of the amplifier that the RF output is intended to drive.
All other components along these signal paths should be 50Ω as well, including the RF transformers,
BNC connectors and coaxial cables.
Equation 2.6 gives a formula for calculating the characteristic impedance of a rectangular trace[5],
where W, T and H are in common units. r is the dielectric constant of the PCB prepreg. This
equation is an approximation and it most accurate for Z0 between 50 and 100 Ω[5]. It is the same
equation that Altium Designer uses by default for calculating the characteristic impedance of traces.
Z0 (Ω) = √
5.98H
87
ln
r + 1.41 0.8W + T
(2.6)
Figure 2.8 shows the trace geometry assumed by Equation 2.6. This trace geometry is referred
to as a microstrip.
Figure 2.8: Diagram of microstrip trace geometry. Use this figure for characteristic impedance
calculations following Equation 2.6. Reproduced from [5].
The situation is slightly more complicated for differential signals. Equation 2.7 can be used for
differential signals [6]. S is the spacing between the two traces carrying the differential signal.
S
Zdif f = 2Z0 (Ω)[1 − 0.48e−0.96 H ]
(2.7)
An alternative trace geometry is referred to as the stripline, and is shown in Figure 2.9. Striplines
have the advantage of having lower impedance than the equivalent microstrip and of providing
natural shielding for high-frequency signals, thus reducing emissions and reducing interference from
incoming signals[5]. Emissions and external interference is not a significant concern for us, as the
boards are to be enclosed in a solid aluminium enclosure. Also, striplines are not accessible from
the exterior of the board, making testing more difficult. We do not use striplines on our board.
Figure 2.9: Diagram of stripline trace geometry. This figure is shown for comparison only; striplines
do not appear on our device. Reproduced from [5].
2. DISCUSSION
17
Using Equations 2.6 and 2.7 and the following parameters,
r = 4.350 (FR-406 dielectric material)
T = 2.8 mils (0.071 mm or the thickness of 2 oz/f t2 copper)
H = 9.6 mils (0.244 mm)
S = 9.0 mils (0.229 mm)
trace widths giving 50Ω were calculated as 14.75mils (0.375mm) for single-ended signals and 26.5mils
(0.673mm) for differential signals. Wherever practical13 , these widths were used in the design.
2.3
Design and Fabrication Methods
This section describes the methods used in designing and fabricating the PCB and enclosure.
2.3.1
Schematic Design
Altium Designer was the software tool used to design the new device, both for a connectivity-level
schematics to the generation of layer-by-layer PCB fabrication files.
Due to similarities, the design was largely based upon the AD9912 reference board schematic.
This included the schematic for the DDS output, including the Reconstruction Filter, but did not
include digital input or power designs. These additional designs were based upon Todd Meyrath’s
AD9852 design[9] but were extensively modified due to the differences between the AD9912 and the
AD9852.
All schematic diagrams are shown in Appendix A.
2.3.2
PCB Design
As mentioned, Altium Designer was the software tool used design the PCB layout. Once the design
was complete, Altium was used to generate layer-by-layer PCB fabrication files (Gerber files) and
drill files. Printouts of these Gerber files are shown in Appendix B. The drill files instruct the PCB
manufacturer on the size and location of all holes to be drilled.
Section 2.2 discusses several considerations which influenced the PCB design.
Figures 2.10 and 2.11 show the full PCB layout from the top and bottom sides. Figures 2.13
and 2.12 show assembly diagrams for the PCB. The top and bottom pastemasks and silkscreens are
shown above the enclosure and IC mechanical drawings.
13 Very
IC.
close to the AD9912 it is nessessary to reduce the width of the traces, due to the small pin spacing of the
2. DISCUSSION
18
Figure 2.10: Top Side PCB layout. The top copper layout is shown in red. The top pastemask is
shown in purple (shown on top of the copper layer).
Figure 2.11: Bottom Side PCB layout. The bottom copper layout is shown in blue. The bottom
pastemask is shown in pink (shown on top of the copper layer). Notice the bottom of the PCB
is ground-filled and that large areas of this ground fill have been exposed (see pink areas). These
regions are located along the edges of the PCB and below the AD9912 IC and the voltage regulators.
They allow the PCB to be grounded to the enclosure and improve heat dissipation.
2. DISCUSSION
19
Figure 2.12: Assembly diagram showing the top pastemask and silkscreen above the enclosure and
IC mechanical drawings.
Figure 2.13: Assembly diagram showing the bottom pastemask and silkscreen above the enclosure
drawings.
2. DISCUSSION
2.3.3
20
PCB Fabrication
The PCB layout design was used to generate fabrication files. There is a drill file, eleven Gerber
files and a README file with basic fabrication instructions. The eleven Gerber files are shown in
Appendix B.
The boards are 5.300 × 300 , which is the same size as the previous generation DDS devices. They
are four-layer boards (top signal, ground, power, bottom signal), which is again the same as the
previous generation DDS devices. They were fabricated using FR-406 dielectric material (4.350
dielectric constant, 9.6 mils (0.244 mm) thick). Each side of the board is protected and insulated
with a green solder-mask and is annotated with a white silkscreen. The PCBs were fabricated by
Advanced Circuits. An electrical test was also performed by Advanced Circuits.
Most components were sourced by our team and ordered from Newark. At time of writing, the
Department of Physics and Astronomy (PHAS) electronics shop was in the process of assembling
a single prototype device. The device is expected to be complete within two or three days of the
submission of this report. We provided them with all necessary parts (except ferrite beads) and
assembly instructions.
Figures 2.14 and 2.15 are photos of the top and bottom of the PCBs. These photos were taken
after the assembly process had begun. Several components are installed, including the AD9912 IC
itself.
Figure 2.14: Photo of the PCB, top side. Some components have been installed.
2. DISCUSSION
21
Figure 2.15: Photo of the PCB, bottom side, no components.
2.3.4
Enclosures
The enclosure is made of aluminium and has two pieces: a body and a lid. The enclosure design was
based upon Todd Meyrath’s work[9]. Due to the increased complexity of our design, it was found that
the original enclosures would short many of the PCB vias. Avoiding these shorts through changing
the PCB was found to be impractical due to space constraints. For this reason, the original enclosure
was modified to minimize the metal surface in contact with the PCB while maintaining structural
integrity. The decreased contact area provided adequate area for the vias.
The enclosure was grounded in a number of ways. The primary method of grounding is through
the screws attaching the PCB to the enclosure, which ensures both a tight fit and adequate return
paths. However, the areas of the bottom of the PCB in direct contact with the enclosure were also
ground filled and exposed to allow for further contact. This grounding is particular important, as
the BNC connectors used obtain their ground only from the enclosure itself.
The New Jersey-based on-line machine shop company eMachineShop was chosen as the supplier (www.emachineshop.com). eMachineShop was the supplier for the enclosures used for the
AD9852-based DDSs (upon which the new design is based). The enclosures were designed using
eMachineShop’s proprietary software, also called eMachineShop. Fifteen enclosures have been ordered from eMachineShop and are expected to arrive within two to three weeks of the submission
of this report.
Figure 2.16 is a labelled diagram of the enclosure body, shown from the top. Green dotted lines
indicate the approximate outlines on the PCB of the four LDO voltage regulators and the AD9912
IC. Shown are ten 4-40 threaded holes and fourteen 8-32 threaded holes, used for mounting the
enclosure lid and the PCB, respectively. Gray dotted lines indicate sixteen 4-40 threaded mounting
holes, twelve of which are for mounting three BNC receptacles and four of which are for mounting
the enclosure to a rack.
The lid is unchanged from the previous design and is shown in Figure 2.17. Shown are twelve
4-40 clearance holes, used to mount the enclosure lid onto the body (two of these holes will be unused
as they have no matching hole in the body). Two spaces are cut into the lid to allow for the 50-pin
data and 3-pin power connectors.
Designs for rack mounting brackets also exist. Each bracket allows up to eight DDS devices to
be mounted to the electronics racks in the QDG lab. The design was modified slightly from an
existing design; the spacing of mounting holes were changed to be compatible with the intended
2. DISCUSSION
22
racks. Five14 brackets have been ordered. At time of writing, the rack mounting brackets have
already been fabricated and are in transit.
Figure 2.18 shows a 3D rendering of the enclosure, created using eMachineShop software.
50-pin
UTBus
Conn.
Digital
1.8V
Analog
3.3V
RF OUT
BNC
DDS
SYSCLK
IN
BNC
5V Conn.
Digital
3.3V
Analog
1.8V
CMOS
OUT
BNC
Figure 2.16: Labelled diagram of the enclosure body (top view). Green dotted lines indicate the
approximate outlines on the PCB of the four LDO voltage regulators and the AD9912 IC.
14 Not
all of these brackets are intended for this project. Extra backets were ordered at the request of the QDG lab.
2. DISCUSSION
23
Figure 2.17: Diagram of the enclosure lid (top view). This design is unchanged from the design used
for the previous generation DDS devices at the QDG lab.
Figure 2.18: 3D rendering of the enclosure, created using eMachineShop software.
2. DISCUSSION
2.4
24
Board Features
This section will begin by discussing the device’s available inputs and outputs, the 10-position switch
used to specify the board address and AD9912 start-up configuration, and the possible configurations
which are possible when the device is assembled.
2.4.1
Inputs and Outputs
Table 2.4 lists the connection pads available on the PCB for BNC Connector mounting. Note that
only J3, J5 and J6 are intended for mass production, and the enclosure design reflects this (see
Section 2.3.4).
Table 2.4: List of connection pads available on the PCB designed for BNC Connector mounting.
Note that only J3, J5 and J6 are intended for mass production, and the enclosure design reflects
this.
Name
Mass Production? Description
Designator
J1
SCLK
No
digital control clock input
DAC OUT
No
unfiltered RF signal, or input to reconstruction
J2
filter for debugging
J3
RF
Yes
filtered RF output signal
FDBK IN
No
input to the AD9912’s on-chip comparator
J4
J5
SYSCLK
Yes
main clock input
J6
CMOS
Yes
programmable clock output (CMOS-level)
J7
OUT N
No
differential programmable clock output (negative)
J8
OUT P
No
differential programmable clock output (positive)
2.4.2
DIP Switch
A 10-position DIP-package single-pole single-throw switch is shared between the six board address
bits and the four AD9912 start-up configuration bits (S1,S2,S3 and S4). Each switch is labeled on
the silkscreen on the top side of the PCB. With the switches closed, the connections are grounded.
With the switches open, the connections are pulled to the 3.3V digital rail through 10kΩ resistors.
The AD9912 start-up configuration bits on the AD9912 allow control of the default start-up
output frequency and the system clock input mode (PLL enabled or bypassed). A decoding of the
configuration bits is reproduced from the AD9912 datasheet in Table 2.5[3].
2.4.3
Configuration Options
The DDS device has various functionality and options that may be enabled, disabled or switched
between by placing or not placing various components. Here we summarise all options of the board
and provide details on how to use them. Table 2.7 summarizes the key options and gives details on
specific components which need to be omitted for each option.
2.4.3.1
SYSCLK
The DDS device is intended to be clocked with an external clock source on BNC connector J5.
However, the option is provided to use an onboard crystal oscillator.
In the QDG lab, the off-board SCLK will originate from a 10MHz rubidium clock with another
DDS being used to increase the frequency as needed (the CMOS clock driver of the AD9912 or
AD9852 equivalent are possible). For more information, see Section 2.1.5.2.
2. DISCUSSION
25
Table 2.5: Options for Power-Up Default Frequencies on the AD9912, for 1GHz System Clock.
Adapted from the AD9912 datasheet[3]. These options can be changed on the device by toggling
four PCB-mounted switches.
S4 S3 S2 S1 SYSCLK Input Mode Output Frequency (MHz)
0
0
0
0
Xtal/PLL
0
0
0
0
1
Xtal/PLL
38.87939
0
1
0
Xtal/PLL
51.83411
0
0
0
1
1
Xtal/PLL
61.43188
0
1
0
0
Xtal/PLL
77.75879
1
0
1
Xtal/PLL
92.14783
0
0
1
1
0
Xtal/PLL
122.87903
0
1
1
1
Xtal/PLL
155.51758
1
0
0
0
Direct
0
0
0
1
Direct
38.87939
1
1
0
1
0
Direct
51.83411
0
1
1
Direct
61.43188
1
1
1
0
0
Direct
77.75879
1
1
0
1
Direct
92.14783
1
1
1
0
Direct
122.87903
1
1
1
Direct
155.51758
1
2.4.3.2
SCLK
It is possible to use either a clock oscillator or an external clock source to drive SCLK. The intention
is to use an on-board clock oscillator (nominally 25MHz, but this will be determined after testing).
For more information, see Section 2.1.5.1.
2.4.3.3
SCLK Enable Pin
If the on-board clock oscillator is to be used, one of W4, W5 and W6 must be installed in order to
enable the clock oscillator.
The board provides jumpers allowing the SCLK enable pin to be connected to ground (W4), 3.3V
(W5) or the address comparator output15 (W6). The address comparator output is LOW when the
address matches.
2.4.3.4
CMOS Clock Driver Voltage
The CMOS clock driver output voltage can be configured to be either 1.8V or 3.3V, depending on
the supply voltage present on the VDD SCLK pin. The board provides two 0805 footprints (F4
and W14) allowing a jumper or ferrite bead to connect the pin to either voltage rail. For more
information, see Section 2.1.1.
2.4.3.5
PLL
When the PLL is enabled, follow Table 2.6 when choosing values for the loop filter components.
See the circuit schematic shown in Figure A.6 for context. The PLL can be enabled or bypassed
on the AD9912 by writing a 0 or 1 to Register 0x0010, Bit 4[3]. The default can be controlled
through startup pin S4. The N-divider should also be set (Register 0x0020, bits 4:0); see the
AD9912 datasheet for more information. This N divider will be half of the PLL multiplier; since N
is restricted to 2 < N < 33, 4 <PLL multiplier< 66. For more information, see Section 2.1.5.3.
15 We aren’t really sure if this is useful, but we thought it might be, so we included it. The idea is that the clock
oscillator will turn off if the board isn’t being talked to by the UTBus. This would reduce power usage and possibly
noise, but may introduce new complication during programming.
2. DISCUSSION
26
Table 2.6: Recommended Loop Filter Values for a Nominal 1.5MHz SYSCLK PLL Loop Bandwidth.
Adapted from the AD9912 datasheet[3]. Designators have been taken to match actual designators
in PCB design. See the circuit schematic shown in Figure A.6.
Multiplier
R4
Series C46 Shunt C45
8
390Ω
1nF
82pF
470Ω
820pF
56pF
10
20
1kΩ
390pF
27pF
10pF
40 (default) 2.2kΩ 180pF
60
2.7kΩ 120pF
5pF
2.4.3.6
RF Path
It is desirable to be able to characterise the reconstruction filter. To do so, the board provides an
option to connect BNC connector J2 directly to the input of the reconstruction filter. To use this
option, place jumper W3 and do not place jumpers W2 or W7. To monitor the pre-filter single-ended
AD9912 DAC output on BNC connector J2 instead, place W2. For normal operation, place only
W7.
The jumper W8 can be used to connect the filtered DAC output to the AD9912 FDBK IN inputs
(these drive the clock drivers). If either clock driver is to be used, install W8. If the clock drivers
are not used, W8 should be omitted, and T2 and R5 are unnecessary.
Table 2.7: List of all device configuration options. In general, all components should be installed
except those listed beside the desired options.
Option
SYSCLK
(1) XTal
(2) External
SCLK
(1) Clock Oscillator2
(2) External
CMOS Voltage
(1) 1.8V
(2) 3.3V3
PLL
(1) Disabled
(2) Enabled4
RF Signal Path5
(1) Clock Drivers Disabled
(2) Clock Drivers Enabled
1
2
3
4
5
Components to omit
C53 C54 R7 R8 R9 R14 T3 W151
W11 W12 X1 C48 C51 W161
W1
U2 W4 W5 W6
F41
W141
C45 C46 R4 W10
R3 W9
C55 C60 C61 C63 R5 R6 R10 R11 R12 R13 T2 W2 W3 W8 W13
W2 W3
These components are located on the bottom side of the PCB.
The clock oscillator used has an enable pin that could be either active high or active low; see
Section 2.1.5.1.
W14 uses the same (0805) package as the ferrite beads, allowing a ferrite bead to be used instead
of a jumper if desired. See Section 2.1.7
If PLL is enabled, the loop filter components must be chosen according to Table 2.6
These are the conventional options are for normal operation. There are several other possible
configurations available; see Section 2.4.3.6.
2. DISCUSSION
2.5
27
Breadboard Testing
In order to verify functionality of the parallel to serial converter, the circuit was constructed and
tested on a breadboard. The PHAS electronics shop provided 8-bit shift registers (CD74HCT165E)
and flip-flops (74HCT74N) in DIP packages for testing. The components used are functionally similar
to the SN74HC166 shift registers and SN74HC74 flip-flops, which are the intended components.
However, the HCT165E shift registers have an asynchronous load while the SN74HC166 have a
synchronous load. The slight difference in shift register functionality does not fully compromise the
test, however it does lead to some undesirable output as discussed below.
Switches were used to statically simulate the address comparator output, the strobe and 16bit data input (arbitrarily set to 1010 1010 1001 01012 ). The outputs were monitored with an
oscilloscope. Results are shown in Figure 2.19. Note that, as expected, the CSB was held low while
the data was clocked out on SDIO.
The undesirable output is indicated graphically on the SIO and CSB subplots of Figure 2.19.
Both signals responded too soon to the SH/LD signal due to the asynchronous load of the HCT165E
shift registers.
The DDS device is designed to use the SN74HC74 shift registers, which have a synchronous load.
The result will be that the output will not respond to a change in the SH/LD signal until a rising
edge of the clock. The red lines shown in Figure 2.19 indicate the desired output.
2. DISCUSSION
28
Voltage (V)
SCLK (Clock)
4
2
0
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
2.5
3
3.5
4
2.5
3
3.5
4
3
3.5
4
Time (µs)
Voltage (V)
SH/LD (Shift/Load)
6
4
2
0
−2
−0.5
0
0.5
1
1.5
2
Time (µs)
Voltage (V)
SIO (Serial Data)
6
4
2
0
−2
−0.5
0
0.5
1
1.5
2
Time (µs)
Voltage (V)
CSB (Chip Select Bit)
6
4
2
0
−2
−0.5
0
0.5
1
1.5
2
2.5
Time (µs)
Figure 2.19: Parallel-to-serial converter breadboard test results. This test simulates the writing
of the (arbitrarily chosen) 16-bit number 1010 1010 1001 01012 to the AD9912 serial control port.
The top graph shows the clock, which was operating at 5.642MHz. A function generator was used.
Below this, the SH/LD graph illustrates the functioning of the load pin. When this signal is low,
the 16-bits of data on the UTBus are latched into two 8-bit shift registers on the DDS device. When
high, shift register contents are clocked into the AD9912. Second from the bottom, the SIO data
plot illustrates the data output from the shift registers. The results are not as desired, but this is
expected due to using parts not from the design (CD74HCT165E shift registers were used in place
of SN74HC74). The red lines illustrate the desired behaviour. The bottom graph shows that the
CSB, which is implemented identically to the SIO and demonstrates the same issue.
3
Conclusions
This report studied the operation of the AD9912 and described in detail the elements of its operation
which are relevant to the project.
A conceptual design satisfying the project requirements has been created and presented. As
required, the design is compatible with the existing UTBus control interface and is designed to
provide a sinusoidal output signal at frequencies from 8 to 400MHz.
The reconstruction filter design was borrowed from the design given for the AD9912 evaluation board, Rev. B. This design has been verified through a SPICE simulation and the resulting
theoretical transfer function has been presented. This transfer function meets the desired performance specifications: 400MHz cut-off frequency, a roll-off within 100MHz and a minimum of 60dB
of attenuation in the stop-band.
Altium Designer was used as the software tool in creating connectivity-level schematics and PCB
fabrication files. The new PCB design uses the same board dimensions, I/O connectors and layer
stack-up as Todd Meyrath’s AD9852 design.
The functionality of the parallel to serial converter design has been verified through a physical
breadboard test. Unfortunately, the exact components specified by the design were not available
at the time and so substitutes of similar functionally were used instead. This did lead to some
undesirable output, however it did not fully compromise the test. The difference between the desired
output and actual output was minor and easily predictable given the functionality of the devices as
described in their datasheets.
Twenty PCBs have been fabricated by Advanced Circuits and are now in the possession of the
QDG lab.
Enclosures for the devices were designed using eMachineShop’s proprietary software. The design
is a modification of the previous generation AD9852 enclosure design. It is not conveniently compatible with the previous generation devices. Fifteen enclosures have been ordered from eMachineShop
and are expected to arrive within two to three weeks of the submission of this report. Five rack
mounting brackets have been ordered, each supporting up to eight DDS devices. The rack mounting
brackets have already been fabricated and at time of writing are in transit.
At time of writing, the PHAS electronics shop was in the process of assembling a single prototype
device. The device is expected to be complete within two or three days of the submission of this
report. Our team provided them with all necessary parts1 and assembly instructions.
Since the prototype device was not complete at time of writing, no testing has been done.
As such, no claims are made regarding the actual functionality and performance of the device.
Our team intends to test the prototype device and either verify correct basic operation or identify
any serious issues. Part II to this report will document testing procedures, testing results and all
recommendations. It will be submitted January 9, 2012.
1 With
the exception of ferrite beads.
29
4
Project Deliverables
At time of writing, a single PCB is in the PHAS electronics shop being assembled. The board is
expected to be complete during the week of January 9, 2012. Our team will test the device in order
to verify correct basic operation of the device or detect any serious issues. No extensive performance
characterization will be performed. A Part II to this report will be submitted on January 20, 2012,
documenting the testing procedures, the results and all recommendations.
4.1
List of Deliverables
The following is a list of the deliverables given in the original proposal for this project, Proposal to
Construct a Direct Digital Synthesizer. The description of each deliverable is copied verbatim. For
each deliverable the current state is described.
• The results of the SPICE simulation of the low-pass filter. In particular, a plot showing the
transfer function of the circuit will be provided.
– The simulation is complete and shows that the filter should work as desired.
– The design was borrowed from the design given for the AD9912 evaluation board, Rev.
B.
– Electronic copies of the files used for testing and the results will be provided.
• Schematic diagram of the DDS device and a full parts list.
– The schematics are complete and all parts have been chosen and sourced.
– Electronic copies of the schematics, parts list and a working Bill of Materials will be
provided electronically.
• PCB layout of the DDS device.
– The PCB layout is complete and has been used to build a PCB with no issues during
manufacturing.
– The PCBs will be left in the drawer the QDG lab has provided for DDS parts.
• Detailed description of testing procedures and results. Performance of the device will be
quantified wherever possible.
– The testing has not yet been completed due to time constraints.
– An assembled board should be received on January 9, 2012 and testing will begin then.
– Details of testing procedures and results will follow this report in a Part II.
• The functioning prototype device.
30
4. PROJECT DELIVERABLES
31
– The prototype device is expected to be received the week of January 9, 2012.
– Once testing is complete, the prototype device will be left in the DDS board drawer in
the QDG lab.
• Modified enclosure design, if required.
– Enclosures for the devices were designed.
– The design is a modification of the previous generation AD9852 enclosure design and is
not conveniently compatible with the previous generation design.
– Fifteen enclosures as well as rack mounting brackets have been ordered from eMachineShop and are expected to arrive within two to three weeks of the submission of this
report.
• Eight or more finished DDS devices, ready for integration into the QDG labs electronic experiment control system.
– Due to time constraints, this milestone was not and will not be accomplished as part of
this ENPH 479 project.
• Engineering recommendation report.
– This document, submitted January 9, 2012, is the Engineering recommendation report.
4.2
Financial Summary
See Table 4.2 for a brief financial summary of the project. See Table 4.2 for a breakdown of the
enclosure costs.
Table 4.1: Summary of costs associated with this project. Enclosure costs do not include front
panels. Extra PCBs were ordered since the marginal cost is very low. The evaluation board was
ordered because it should be a useful benchmark during performance characterization.
Quantity Vendor
Unit Cost Total Cost
Description
PCBs
20
Advanced Circuits
$44.92
$898.30
Enclosures
15
eMachineShop
$60.59
$908.85
AD9912
15
Analog Devices
$50
$750
Other Components 15 sets
Newark, Mousser, Digikey $43.35
$650.26
Evaluation Board
1
Analog Devices
$500
$500
Table 4.2: DDS Enclosure Costs. All parts were ordered from eMachineShop. Note that only 2 of 5
front panels are intended for the AD9912 DDS devices.
Description
Quantity Unit Cost Total Cost
Lid
15
$10.87
$163.05
Enclosures
15
$49.72
$745.73
Front Panels 5
$67.29
$336.47
References
[1] Advanced Layout Solutions, Ltd., Control Impedance. 2009.
[2] Analog Devices CMOS 300 MSPS Complete DDS, Analog Devices 9852. 2007.
[3] Analog Devices, Analog Devices 9912 1 GSPS Direct Digital Synthesizer with 14 Bit DAC. 2010.
[4] Analog Devices, AD9912 Evaluation Board, Rev.0. 2008.
[5] Analog Devices, Microstrip and Stripline Design. 2009.
[6] Douglas Brooks, Differential Impedance. Miller Freeman, 1998.
[7] Keith Ladouceur, Experimental Advances toward a Compact Dual-Species Laser Cooling Apparatus. 2008.
[8] Sanaz Footohi, Control System of Quantum Degenerate Gases Laboratory. 2006.
[9] Todd P. Meyrath, Digital RF Synthesizer: DC to 135 MHz. 2005.
[10] Texas Instruments, PCB Design Guidelines For Reduced EMI. November 1999.
32
Appendix A
Schematic Diagrams
This section contains the full schematic diagrams for the DDS circuit. Altium Designer was used to
create these figures.
1
2
3
4
A
A
U_DDS_IC
DDS_IC.SchDoc
U_CLK
CLK.SchDoc
B
SCLK_EN
Clock
U_Analog
Analog.SchDoc
FDBK_INB
FDBK_IN
SYSCLK
SYSCLKB
SCLK
SYSCLK
SYSCLKB
SCLK
U_Digital
Digital.SchDoc
OUT_CMOS
OUTB
OUT
DAC_OUTB
DAC_OUT
OUT_CMOS
OUTB
OUT
DAC_OUTB
DAC_OUT
FDBK_INB
FDBK_IN
Analog
SCLK
SDIO
CSB
BRDSel
SDIO
CSB
S[4..1]
S[4..1]
DDS
Digital
U_Power
Power.SchDoc
C
B
C
Power
D
D
1
2
3
Figure A.1: Schematic diagram, top level. Top Level.SchDoc
33
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
34
2
3
4
A
A
Primary Clock
GND
GND
COR7
R7
25
PIJ501
PIR1401
25 (OPT)
T3
5 COT3
1
PIT305
PIT301
PIJ502
PIR701
PIR802
COC53
C53
COW12
W12
PIC5401 PIC5402
PIR902
PIW1202
PIX103
PIX10
PIC4801
COX1
X1
25MHz (OPT)
PIW1201
PIC4802
GND
10pF
COC51
C51
PIC5101
PIC5102
PIX102PIX104
0
0.1uF
COR9
R9
B
PIW1101
0
COC54
C54
3
PIT303
ETC1-1-13
PIW1102
0.1uF
PIR801
4
PIT304
GND
COC48
C48
COW11
W11
PIC5301 PIC5302
COR8
R8
25 (OPT)
Refer to crystal data sheet for capacitor values (C48 & C51).
POSYSCLK
SYSCLK
3
SYSCLK_IN
NLSYSCLK0N
SYSCLK_N
1
COR14
R14
COJ5
J5
Refer to AD9912 data sheet for a list of compatible crystal oscillators.
PIR702
PIR1402
GND
10pF
NLSYSCLK0P
SYSCLK_P
POSYSCLKB
SYSCLKB
25
B
PIR901
GND
Serial Input Clock
COW6
W6
POSCLK0EN
SCLK_EN PIW602
PIW601
0
COW4
W4
GND
PIW402
VDD_DGT
PIW502
PIW401
COU2
U2
0
C
COW5
W5
1
PIW501
PIU201
GND
PIU202
0
2
EN
3
OUT
PIU203
GND VDD
PIU204
4
PIW102
VDD_DGT
C
POSCLK
SCLK
COW1
W1
0
PIW101
TXC 7C
Clock Oscillator (~25MHz)
COJ1
J1
SCLK_IN
Input BNC for Testing
PIJ101
PIJ102
GND
D
D
1
2
3
Figure A.2: Schematic diagram, clocks. CLK.SchDoc
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
35
2
3
4
50-Pin Molex Header (UTBus)
COP2
P2
A
PIP2050
PIP2048
PIP2046
PIP2044
PIP2042
PIP2040
PIP2038
PIP2036
PIP2034
PIP2032
PIP2030
PIP2028
PIP2026
PIP2024
PIP2022
PIP2020
PIP2018
PIP2016
B
PIP2014
PIP2012
PIP2010
PIP208
PIP206
PIP204
GND
PIP202
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
NLSTROBE
STROBE
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
A
PIP2049
NLADR7
ADR7
PIP2047
NLADR6
PIP2045ADR6
NLADR5
ADR5
NLADR4
ADR4
NLADR3
ADR3
NLADR2
ADR2
ADR1
PIP2035
NLADR0
ADR0
PIP2033
NLDAT15
DAT15
PIP2031
NLDAT14
DAT14
PIP2029
NLDAT13
DAT13
PIP2027
NLDAT12
DAT12
PIP2025
NLDAT11
DAT11
PIP2023
NLDAT10
DAT10
PIP2021
NLDAT9
DAT9
PIP2019
NLDAT8
DAT8
PIP2017
NLDAT7
DAT7
PIP2015
NLDAT6
DAT6
PIP2013
NLDAT5
DAT5
PIP2011
NLDAT4
DAT4
PIP209
NLDAT3
DAT3
PIP207
NLDAT2
DAT2
PIP205
NLDAT1
DAT1
PIP203
NLDAT0
DAT0
PIP201
AD9912 Startup Config.
PIP2043
PIP2041
COSW1B
SW1B
7
8
8
9
10
PISW1010 10
PIP2039
PIP2037
NLADR070000
ADR[7..0]
17
18
19
20
PISW107 7
PISW1017
PISW108
PISW1018
PISW109 9
PISW1019
GND
PISW1020
NLS4
S4
COR21 10K
R21
PIR2102
PIR2101
COR22 10K
R22
PIR2202
PIR2201
COR23 10K
R23
PIR2302
SDA10H0KD
PIR2301
COR24 10K
R24
PIR2402
PIR2401
NLS3
S3
NLS2
S2
NLS040010
S[4..1]
NLS1
S1
POS040010
POS4
POS3
POS2
POS1
S[4..1]
VDD_DGT
Address Buss Functionality:
B
ADR[7..2]
Board address. In order for the strobe to be recognized,
this must match the board address set with the DIP
switch.
ADR1:
Low => 16-bit data transfer
High => 8-bit data transfer, DAT[15..8] ignored
Header 25X2
ADR0:
Unused
C
C
Board Select
U_BoardSel
BoardSel.SchDoc
BRDSel
ADR[7..2]
SCLK
STROBE
NLADR070020
ADR[7..2]
POBRDSel
POBRDSEL
BRDSel
Parallel to Serial Data Converter
U_Par2Ser
Par2Ser.SchDoc
SH/LD
SH/LD
DAT[15..0]
SCLK
SZ
NLDAT0150000
DAT[15..0]
D
POSDIO
SDIO
SDIO
NLADR1
ADR1
CSB
NLCSB
CSB
SCLK
POSCLK
CSB
POCSB
D
1
2
3
Figure A.3: Schematic diagram, digital.
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
36
2
A
3
4
A
Board Address Comparator
PISW1012
PISW103 3
PISW1013
GND
PISW1014
SDA10H0KD
P0
P1
P2
P3
P4
P5
P6
P7
3
5
7
NLADR4
ADR4 PIU109
9
NLADR3
ADR3 PIU1012
12
NLADR2
ADR2 PIU1014
14
16
PIU1016
18
PIU1018
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIU102
COR16 10K
R16
PIR1602
PIU106
PIU104
PIR1601
PIU108
COR17 10K
R17
PIR1702
PIR1701
COR18 10K
R18
PIR1802
GND
COR19 10K
R19
PIR1902
NLADR7
ADR7
COR20 10K
R20
PIR2002
NLADR5
ADR5
PIR1801
NLADR6
ADR6
PIR2001
POADR7
POADR6
POADR5
POADR4
POADR3
POADR2
POADR070020
ADR[7..2]
2
4
6
8
11
PIU1011
13
PIU1013
15
PIU1015
17
PIU1017
COR15 10K
R15
PIR1502
PIR1501
PIR1901
B
OE
NLADR070020
ADR[7..2]
GND
PIU103
PIU105
PIU107
10
PIU1010
VCC
20
PIU1020
P=Q
PIU1019
VDD_DGT
19
POBRDSel
POBRDSEL
BRDSel
Board Select
Can be used to turn the clock
oscillator on or off.
B
GND
SN74HC688DW
Byte Comparator
VDD_DGT
PIU301
PIU40
12
4
PIU3012
3
PIU403
PIU4014
C
D
PR
Q
5
11
PIU405
PIU3011
D
PR
Q
9
2
PIU309
PIU302
3
CLK
PIU303
8
CLR Q PIU308
COU3B
U3B
SN74HC74D
CLK
PIU3013
6
CLR Q PIU406
COU4A
U4A PIU407
SN74HC74D
PIU401
D
VDD_DGT
PR
Q
5
PIU305
CLK
6
CLR Q PIU306
COU3A
U3A PIU307
SN74HC74D
PIU301
PIU3014
13
PIU402
1
2
POSTROBE
STROBE
PIU304
10
VDD_DGT
4
11
12
13
14
15
PISW1015
16
PISW1016
PISW1011
PISW102
1
PIU101
GND
POSH0L\D\
SH/LD
This active-low output will stay low
for one period of SCLK after a 0-to-1
transistion on STROBE, if the board
address matches.
1
COSW1A
SW1A
1
2
2
3
4
PISW104 4
5
PISW105 5
6
PISW106 6
PISW101 1
COU1
U1
VDD_DGT
Board Address DIP Switch
C
VDD_DGT
VDD_DGT
POSCLK
SCLK
NLSCLK
SCLK
VDD_DGT
10
PIU401
CLR and PRE are active-low
asychronous clear and preset
pins.
GND
12
PIU4012
D
GND
11
PIU4011
CLK
PR
Q
9
PIU409
Unused flip-flop
8
CLR Q PIU408
COU4B
U4B
SN74HC74D
13
PIU4013
D
D
VDD_DGT
1
2
3
4
Figure A.4: Schematic diagram, flip-flops and board select comparator.
APPENDIX A. SCHEMATIC DIAGRAMS
1
37
2
NLSH0L\D\
SH/LD
POSH0L\D\
SH/LD
3
4
COU7
U7
SH/LD
A
NLSCLK
SCLK
POSCLK
SCLK
SCLK
15
PIU7015
VDD_DGT
GND
NLSZ
SZ
POSZ
SZ
SZ = 0 for 16-bit transfer
SZ = 1 for 8-bit transfer
6
PIU706
7
PIU707
GND
NLDAT0150000
DAT[15..0]
PODAT0150000
PODAT15
PODAT14
PODAT13
PODAT12
PODAT11
PODAT10
PODAT9
PODAT8
PODAT7
PODAT6
PODAT5
PODAT4
PODAT3
PODAT2
PODAT1
PODAT0
DAT[15..0]
9
PIU709
NLDAT15
DAT15
NLDAT14
DAT14
NLDAT13
DAT13
NLDAT12
DAT12
NLDAT11
DAT11
NLDAT10
DAT10
NLDAT9
DAT9
NLDAT8
DAT8
GND
1
2
3
4
5
PIU705
10
PIU7010
11
PIU7011
12
PIU7012
14
PIU7014
PIU701
PIU702
PIU703
PIU704
8
PIU708
S/L
VCC
CLR
CLK INH
CLK
SI
A
B
C
D
E
F
G
H
QH
16
PIU7016
VDD_DGT
A
13
PIU7013
SH/LD
SCLK
NLDAT0
DAT0
PIU908
NLDAT5
DAT5
NLDAT4
DAT4
SN74HC166D
8-Bit Shift Reg.
NLDAT3
DAT3
NLDAT2
DAT2
NLDAT1
DAT1
B
VDD_DGT
PIU906
GND
NLDAT6
DAT6
16
PIU9016
PIU909
1
2
3
4
5
PIU905
10
PIU9010
11
PIU9011
12
PIU9012
14
PIU9014
NLDAT7
DAT7
GND
COU9
U9
15
S/L
VCC
9
CLR
6
CLK INH
7
PIU907 CLK
PIU9015
VDD_DGT
GND
PIU901
PIU902
PIU903
PIU904
8
SI
A
B
C
D
E
F
G
H
QH
13
POSDIO
SDIO
PIU9013
B
GND
SN74HC166D
8-Bit Shift Reg.
COU8
U8
SH/LD
SCLK
15
9
6
7
PIU807
S/L
VCC
CLR
CLK INH
CLK
1
2
3
4
5
PIU805
10
PIU8010
11
PIU8011
12
PIU8012
14
PIU8014
SI
A
B
C
D
E
F
G
H
PIU8015
VDD_DGT
GND
VDD_DGT
PIU809
PIU806
PIU801
PIU802
PIU803
PIU804
C
GND
8
QH
16
PIU8016
VDD_DGT
13
PIU8013
COU5
U5
SH/LD
SCLK
15
9
PIU5015
VDD_DGT
GND
PIU509
6
PIU506
7
PIU507
1
2
3
4
5
PIU505
10
PIU5010
11
PIU5011
12
PIU5012
14
PIU5014
PIU501
PIU502
PIU808
GND
PIU503
PIU504
SN74HC166D
8-Bit Shift Reg.
GND
8
PIU508
S/L
VCC
CLR
CLK INH
CLK
SI
A
B
C
D
E
F
G
H
QH
16
PIU5016
VDD_DGT
C
13
POCSB
CSB
PIU5013
GND
SN74HC166D
8-Bit Shift Reg.
D
D
1
2
3
Figure A.5: Schematic diagram, parallel-to-serial converter.
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
2
A
B
AVDD_1
AVDD_1
AVDD_1
AVDD_2
AVDD_1
AVDD_2
VDD_SYSCLK_1
AVDD_2
VDD_SYSCLK_2
AVDD_2
VDD_SYSCLK_2
VDD_DACDEC
VDD_SYSCLK_1
VDD_CMOS
VDD_SIO
VDD_DAC3
VDD_DAC3
VDD_DAC3
GND
GND
GND
GND
DVDD
DVDD
DVDD
VDD_SIO
GND
GND
GND
GND
GND
NLS040010
S[4..1]
POS040010
POS4
POS3
POS2
POS1
S[4..1]
GND
NLS1
S1
NLS2
S2
NLS3
S3
NLS4
S4
C
NLSDIO
SDIO
NLSDO
SDO
POSDIO
SDIO
38
11
PIU6011
19
PIU6019
23
PIU6023
36
24
42
25
44
PIU6044
26
PIU6026
45
PIU6045
29
PIU6029
53
PIU6053
30
PIU6030
37
PIU6037
14
PIU6014
46
PIU6046
47
PIU6047
49
PIU6049
33
PIU6033
39
PIU6039
43
PIU6043
52
PIU6052
3
PIU603
5
PIU605
7
PIU607
1
PIU601
2
PIU602
4
PIU604
6
PIU606
8
PIU608
56
PIU6056
57
PIU6057
PIU6036
PIU6024
PIU6042
PIU6025
AVDD_2
AVDD_3
AVDD_4
AVDD_5
AVDD_6
AVDD_7
AVDD_8
AVDD_9
AVDD_10
AVDD_11
AVDD_12
AVDD_13
AVDD
AVDD3_2
AVDD3_3
AVDD3_4
AVDD3_5
AVDD3
AVSS_2
AVSS_3
AVSS_4
AVSS
DVDD_2
DVDD_3
DVDD
DVDD_I/O
DVSS_2
DVSS_3
DVSS_4
DVSS_5
DVSS_6
DVSS
9
S1
10
S2
54
S3
55
PIU6055 S4
NC
NC_9
NC_8
NC_7
NC_6
NC_5
NC_4
NC_3
NC_2
EP
COU6
U6
AD9912
PIU6054
63
62
PIU6063
PIU6062
SYSCLKB
SCLK
SYSCLK
CLKMODESEL
SDIO
SDO
20
PIU6020
18
17
16
15
13
PIU6013
12
PIU6012
PIU6018
PIU6017
PIU6016
PIU6015
65
PIU6065
EXTERNAL
CLOCK OR
OSCILLATOR
GND
28
64 POSCLK
SCLK
27
PIU6027POSYSCLK
SYSCLK
32
PIU6032
PIW1502
COW16
W16
0
59
PIR2601
40
POFDBK0INB
FDBK_INB
41
PIU6041POFDBK0IN
FDBK_IN
PIW1501
PIR2602
GND
B
PIR2702
GND
10K
COC45
C45
61
PIU6061POCSB
CSB
60
NLIO0UPDATE
IO_UPDATE
31
NLLOOP0FILTER
LOOP_FILTER
IO_UPDATE
PIU6060
LOOP_FILTER
PIU6031
COW15
W15
0
PIW1601
PIR2902
510
COR26
R26
NLRESET
RESET
PIU6040
COR29
R29
PIR2901
PIC4501 PIC4502
COR27
R27
PIR2701
10K
10pF
COW10
W10
PIW1002
38
COC46
C46
COR4
R4
PIW1001
PIR402
0
2.2K
COW9
W9
COR3
R3
PIR401
PIC4601 PIC4602
34
35
PIU6034POOUTB
OUTB
PIW901
POOUT
OUT
COR28
R28
48 NLDAC0RSET
DAC_RSET
PIR2801
51
10K
PIU6051PODAC0OUTB
DAC_OUTB
50
PIU6050PODAC0OUT
DAC_OUT
COR25
R25
58 NLPWRDOWN
PWRDOWN
0
PIU6035
DAC_RSET
DAC_OUTB
DAC_OUT
PIU6048
PWRDOWN
PIU6058
PIR2501
PIR2802
GND
PIR2502
GND
PIW902
PIR301
VDD_SYSCLK_2
180pF
PIU6038POOUT0CMOS
OUT_CMOS
10K
These pins are part of the fanout and are connected to vias to
allow easier probing, but are otherwise unconnected:
GND
PIW1602
PIU6064
NLCLKMODESEL
CLKMODESEL
CRYSTAL
AVDD
PIU6028POSYSCLKB
SYSCLKB
PIU6059
OUTB
OUT
Startup Config. Pins
A
21
PIU6021
RESET
OUT_CMOS
4
22
PIU6022
FDBK_INB
FDBK_IN
CSB
PIU609
PIU6010
3
PIR302
GND
OPT (1K)
The loop filter component values shown above
(R4, C45 and C46) depend on the PLL
multiplier used and should be chosen
accordingly (see Table 6 of the AD9912
datasheet). Values shown are appropriate for
the default multiplier (40).
C
IO Pin Summary:
All are 3.3V CMOS
IO_UPDATE
PWRDOWN
RESET
SDO
D
1
IO_UPDATE (active high, internal 50k pull-down resistor)
RESET (active high, ground with 10k resistor if not used)
PWRDOWN (active high, internal 50k pull-down resistor)
CSB (active low, internal 100k pull-up resistor)
SDO
SDIO
SCLK (internal 50k pull-down resistor)
2
D
3
Figure A.6: Schematic diagram, AD9912.
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
39
2
3
5V Molex Connector
Bypass Capacitors and Ferrite Beads
COP1
P1
A
B
3
2
1
PIP103
PIC6401 PIC6402
GND
A
GND
5V T491X
470uF
Power2
Digital 1.8V
Analog 3.3V
COUP1
UP1
TPS78618
COUP2
UP2
TPS78633
2
5V
U_Power2
Power2.SchDoc
COC64
C64
GND
PIP102
PIP101
4
PIUP102
IN
Bypass
5
2
5V
PIUP105
PIUP202
5
IN
Bypass
PIUP205
EN
Out
PIUP204
B
DVDD
T491B
10uF
1
PIUP201
PIC401
PIC402
PIU103
PIC602
PIC601
COC4
C4
T491B
10uF
COC6
C6
0.1uF
PIC802
PIC801
PIC301
PIC302
COC8
C8
0.01uF
4
GND
COC2
C2
AVDD3
4
PIUP104
GND
Out
3
PIC201
PIC202
EN
COC3
C3
T491B
10uF
PIC501
PIC502
PIU203
3
1
PIUP101
PIUP106
Analog 1.8V
COUP3
UP3
TPS78633
TPS78618
PIUP402
IN
Bypass
5
2
5V
PIUP405
PIUP302
IN
PIU403
1
PIUP301
PIC6201
PIC6202
COC62
C62
T491B
10uF
PIC5902
PIC5901
COC59
C59
0.1uF
PIC5702
PIC5701
COC57
C57
0.01uF
PIC50 1
PIC50 2
EN
GND
Out
0.01uF
PIUP305
Out
4
PIUP304
C
AVDD
4
PIUP404
COC50
C50
T491B
10uF
PIU30
3
T491B
10uF
EN
GND
COC65
C65
3
PIC6501
PIC6502
COC9
C9
5
Bypass
DVDD3
1
PIUP401
PIC902
PIC901
GND
Digtal 3.3V
COUP4
UP4
2
5V
COC7
C7
0.1uF
PIUP206
GND
C
PIC702
PIC701
COC5
C5
T491B
10uF
PIUP406
PIC5201
PIC5202
COC52
C52
T491B
10uF
PIC5602
PIC5601
COC56
C56
0.1uF
PIC5802
PIC5801
COC58
C58
0.01uF
PIUP306
GND
GND
D
D
1
2
3
Figure A.7: Schematic diagram, power 1 (voltage regulators).
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
40
2
3
4
A
A
Power Isolation Diagram
Bypass Capacitors
0805 footprint for all ferrite beads and W14
1206 footprint for logic IC bypass caps (these are shown in the top row: C31,C49,...,C12)
Local Nets
Main Net
COF3
F3
Pins 36, 42,
44 & 45
AVDD_2
PIF301
PIF302
PIF302
AVDD_1
PIF201
PIF202
PIF202
VDD_SYSCLK_1
PIF501
PIF502
PIF502
AVDD
Analog 1.8V
Ferrite bead
COF2
F2
Pins 11, 19,
23 & 24
0402 footprint for AD9912 bypass caps
DVDD3
GND
DVDD3
B
COC31
C31
0.1uF
PIC4901
PIC4902
COC49
C49
0.1uF
PIC2501
PIC2502
COC25
C25
0.1uF
PIC3401
PIC3402
COC34
C34
0.1uF
PIC101
PIC102
COC1
C1
0.1uF
PIC40 1
PIC40 2
COC40
C40
0.1uF
PIC4701
PIC4702
COC47
C47
0.1uF
PIC10 1
PIC10 2
COC10
C10
0.1uF
PIC1 01
PIC1 02
COC11
C11
0.1uF
PIC1201
PIC1202
COC12
C12
0.1uF
Ferrite bead
COF5
F5
Pins 25 & 30
PIC3101
PIC3102
GND
Ferrite bead
COF6
F6
AD9912
Pins 26, 29 & loop filterVDD_SYSCLK_2
AVDD_1
Ferrite bead
COF1
F1
Pin 53
VDD_DACDEC
B
PIF601
PIF602
PIF602
PIC3801
PIC3802
PIF101
PIF102
PIF102
GND
COW14
W14
Ferrite bead
PIW1402
COC38
C38
0.1uF
PIC3701
PIC3702
COC37
C37
0.1uF
PIC3201
PIC3202
COC32
C32
0.1uF
AVDD_2
PIC3901
PIC3902
COC39
C39
0.1uF
PIC4101
PIC4102
COC41
C41
0.1uF
GND
PIC3601
PIC3602
COC36
C36
0.1uF
PIC3501
PIC3502
COC35
C35
0.1uF
PIC6701
PIC6702
COC67
C67
0.1uF
PIW1401
0
COF4
F4
Pin 36
VDD_CMOS
VDD_DACDEC
PIF401
PIF402
PIF402
Ferrite bead
GND
VDD_DAC3
AVDD3
Analog 3.3V
DVDD
Digital 1.8V
DVDD3
Digtal 3.3V
PIC20 1
PIC20 2
VDD_SYSCLK_1
COC20
C20
0.1uF
GND
PIC4 01
PIC4 02
VDD_SYSCLK_2
COC44
C44
0.1uF
PIC4301
PIC4302
GND
COC43
C43
0.1uF
PIC4201
PIC4202
COC42
C42
0.1uF
Pins 46, 47 & 49
AVDD3
Pins 3, 5 & 7
Pins 1 & 14
C
Digital Input Logic
All ICs except AD9912
DVDD
VDD_SIO
VDD_DGT
GND
DVDD
GND
PIC3 01
PIC3 02
PIC2801
PIC2802
COC33
C33
0.1uF
PIC30 1
PIC30 2
COC28
C28
0.1uF
PIC2701
PIC2702
COC30
C30
0.1uF
PIC2901
PIC2902
COC27
C27
0.1uF
PIC2601
PIC2602
VDD_CMOS
COC29
C29
0.1uF
GND
PIC6 01
PIC6 02
COC66
C66
0.1uF
C
COC26
C26
0.1uF
D
D
1
2
3
4
Figure A.8: Schematic diagram, power 2 (bypass capacitors and ferrite beads).
APPENDIX A. SCHEMATIC DIAGRAMS
1
41
2
3
PIW201
PODAC0OUTB
DAC_OUTB
NLDAC0OUT0P
DAC_OUT_P
PIR102
COR1
R1
A
PIR101
OPT
PIR202
COR2
R2
GND
NLDAC0OUT0N
DAC_OUT_N
4
PIT103
PIT105
5
PIT102
6
PIT101
PIR201
COJ2
J2
PIJ202
PIW302
PIW701
DUT OUT/FILTER IN
PIJ201
COW3
W3
0
PIW202
3
GND
A
COW7
W7
0
2
1
PIT106
OPT
PODAC0OUT
DAC_OUT
PIT104
NLFILT0IN
FILT_IN
PIW301
COW2
W2
0
COT1
T1
4
PIW702
GND
ADT2-1T-1P+
RF Transformer
U_Reconstruction Filter
Reconstruction Filter.SchDoc
RF_IN
COJ3
J3
NLFILT0OUTPIJ301
FILT_OUT
RF_OUT
DUT FILTER OUT
PIJ302
PIW802
COW8
W8
0
COT2
T2
POFDBK0IN
FDBK_IN
NLFDBK0IN0N
FDBK_IN_N
PIR502
COR5
R5
100
B
POFDBK0INB
FDBK_INB
NLFDBK0IN0P
FDBK_IN_P
PIR501
PIT204
4
PIT203
3
PIT205
5
PIT202
6
PIT201
GND
GND
PIW801
2
COJ4
J4
NLFDBK0INPIJ401
FDBK_IN
1
PIT206
FDBK_IN
PIJ402
ADT2-1T-1P+
RF Transformer
B
GND
GND
PIR1301
COR13
R13
10K
COC61
C61
POOUT
OUT
NLOUT0P
OUT_P
PIR10 1
PIC5502
PIR1 02
PIR1 01
COR6
R6
10K
PIR602
GND
COR11
R11
1K
PIR601
NLOUT0N
OUT_N
OUT
PIJ801
PIJ802
PIR10 2
PIC5501
0.1uF
COJ8
J8
NLOUT
OUT
10nF
COR10
R10
10K
COC55
C55
GND
C
POOUTB
OUTB
PIR1302
PIC6101 PIC6102
C
COJ7
J7
COC60
C60
PIC6001 PIC6002
PIR1201
COR12
R12
10K
10nF
PIR1202
NLOUTB
OUTB
OUTB
PIJ701
PIJ702
GND
GND
POOUT0CMOS
OUT_CMOS
COW13
W13
NLOUT0CMOS
OUT_CMOS
PIC6302 PIW13010
C63
COC63
PIC6301 OPT
COJ6
J6
CMOS OUT
PIW1302
PIJ601
PIJ602
GND
GND
D
1
2
D
3
Figure A.9: Schematic diagram, analog.
4
APPENDIX A. SCHEMATIC DIAGRAMS
1
42
2
3
4
A
A
GND
GND
GND
GND
PIC1402
PIC1401
PIC1602
PIC1601
PIC1702
PIC1701
PIC1902
PIC1901
COC14
C14
2.7pF
COC16
C16
5.6pF
COC13
C13
B
PIC1301
COC17
C17
6.8pF
COC18
C18
COL2
L2
PIC1302
PIL201
PIL202
PIC1801
22nH
5.6pF
COC19
C19
3.9pF
B
PIC1802
1.0pF
PORF0IN
RF_IN
PORF0OUT
RF_OUT
COC15
C15
COL1
L1
PIL101
PIL102
PIC1501
18nH
PIC2102
COC21
C21
PIC2101 2.7pF
PIC1502
COL3
L3
PIL301
PIC2 02
COC22
C22
PIC2 01 5.6pF
PIL302
27nH
2.7pF
PIC2302
COC23
C23
PIC2301 6.8pF
PIC2402
COC24
C24
PIC2401 3.9pF
C
C
GND
GND
GND
GND
400MHz 7th Order Elliptic Low-Pass Filter
0402 footprint for all components shown here
D
D
1
2
3
Figure A.10: Schematic diagram, reconstruction filter.
4
Appendix B
PCB Fabrication Drawings
This section contains printouts generated from the Gerber files used for PCB fabrication. These files,
along with hole/via drilling information provide the PCB manufacturer with most of the information
needed to construct the boards. Unless noted in the caption, the Gerber files shown are positive,
meaning that dark areas indicate that material should be present (either copper, the insulating
soldermasks or the silkscreens). The ground and power plane files are negative, meaning that dark
areas indicate that material should be removed.
Figure B.1: Fabrication Drawings, top copper layer.
43
APPENDIX B. PCB FABRICATION DRAWINGS
Figure B.2: Fabrication Drawings, ground plane (negative).
Figure B.3: Fabrication Drawings, power plane (negative).
44
APPENDIX B. PCB FABRICATION DRAWINGS
Figure B.4: Fabrication Drawings, bottom copper layer.
Figure B.5: Fabrication Drawings, top silkscreen.
45
APPENDIX B. PCB FABRICATION DRAWINGS
Figure B.6: Fabrication Drawings, bottom silkscreen.
Figure B.7: Fabrication Drawings, top soldermask.
46
APPENDIX B. PCB FABRICATION DRAWINGS
Figure B.8: Fabrication Drawings, bottom soldermask.
Figure B.9: Fabrication Drawings, drill drawing.
47
Appendix C
3D PCB Renderings
This section contains 3D renderings of the top and bottom of the PCB. Altium Designer was used
to create these figures. Figures C.1 and C.2 use a somewhat realistic colour scheme.
Figure C.1: 3D Rendering of the DDS, top view. Created using Altium Designer.
48
APPENDIX C. 3D PCB RENDERINGS
Figure C.2: 3D Rendering of the DDS, bottom view. Created using Altium Designer.
49
APPENDIX C. 3D PCB RENDERINGS
Figure C.3: 3D Rendering of the DDS, angled view. Created using Altium Designer.
50
Appendix D
PCB Parts List
Table D.1: Bill of Materials
Comment
Description
Footprint Designator
0.1µF
Capacitor
1206
T491B
B
0.01µF
Solid Tantalum Chip
Capacitor,
Standard
T491 Series - Industrial
Grade
Capacitor
5.6pF
2.7pF
6.8pF
1.0pF
3.9pF
0.1µF
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
0402
0402
0402
0402
0402
0402
10pF
180pF
0.1µF
10nF
OPT
T491X
0402
0402
0402
0402
1206
X
Ferrite bead
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Solid Tantalum Chip
Capacitor,
Standard
T491 Series - Industrial
Grade
Ferrite Bead
SCLK IN
BNC Elbow Connector
BCN
Pads
51
1206
0805
C1, C6, C7,
C10, C11, C12,
C31, C40, C47,
C49, C56, C59
C2, C3, C4, C5,
C50, C52, C62,
C65
C8,
C58
C13,
C14,
C17,
C18
C19,
C20,
C27,
C30,
C34,
C37,
C41,
C44,
C45,
C46
C53,
C60,
C63
C64
C9,
C57,
C16, C22
C15, C21
C23
C24
C25, C26,
C28, C29,
C32, C33,
C35, C36,
C38, C39,
C42, C43,
C66, C67
C48, C51
C54, C55
C61
F1, F2, F3, F4,
F5, F6
J1
APPENDIX D. PCB PARTS LIST
Comment
Description
DUT
BNC Elbow Connector
OUT/FILTER
IN
DUT
FIL- BNC Elbow Connector
TER OUT
BNC Elbow Connector
FDBK IN
52
Footprint Designator
BCN
Pads
J2
J3
SYSCLK IN
BNC Elbow Connector
CMOS OUT
BNC Elbow Connector
OUTB
BNC Elbow Connector
OUT
BNC Elbow Connector
18nH
22nH
27nH
70543-0107
Inductor
Inductor
Inductor
Header, 3-Pin
Header 25X2
50Ω
1kΩ
2.2kΩ
100Ω
10kΩ
N2550-5002RB
Resistor
Resistor
Resistor
Resistor
Resistor
BCN
Pads
BCN
Pads
BCN
Pads
BCN
Pads
BCN
Pads
BCN
Pads
0402
0402
0402
Power
Header
UTBUS
0402
0402
0402
0402
0402
25Ω
25Ω
1kΩ
25Ω
10kΩ
Resistor
Resistor
Resistor
Resistor
Resistor
0402
0402
0402
1206
1206
510Ω
SDA10H0KD
Resistor
C&K SDA Series Low
Profile DIP Switches,
10 Pos
6-Pin Transformer
1206
DIPSW20
P2
R1, R2
R3
R4
R5
R6, R10,
R13
R7, R9
R8
R11
R14
R15, R16,
R18, R19,
R21, R22,
R24, R25,
R27, R28
R29
SW1
CD542
T1, T2
SM22
T3
ADT2-1T1P+
ETC1-1-13
E-Series RF 1:1 Transmission Line Transformer, 4.5-3000MHz
SN74HC688DW8-Bit Identity Comparator
TXC 7C
TXC Clock Oscillator
(SCLK)
J4
J5
J6
J7
J8
L1
L2
L3
P1
DW020 M U1
4-pin
SMD
U2
R12,
R17,
R20,
R23,
R26,
APPENDIX D. PCB PARTS LIST
Comment
Description
SN74HC74D
53
Footprint Designator
Dual D-Type PositiveEdge-Triggered FlipFlop with Clear and
Preset
SN74HC166D 8-Bit
Parallel-Load
Shift Register
AD9912
Direct Digital Synthesizer
TPS78618
Texas Instruments 5Pin Voltage Regulator
TPS78633
Texas Instruments 5Pin Voltage Regulator
0Ω
Jumpers
D014 N
U3, U4
D016 N
U5, U7, U8, U9
64-pin
SMD
SOT2236M
SOT2236M
1206
U6
0Ω
Jumpers
0402
0Ω
Fox
HC49SDLF
Jumpers
25MHz Crystal Oscillator (SYSCLK)
0805
4-pin
SMD
UP1, UP3
UP2, UP4
W1, W2, W3,
W4, W5, W6,
W7, W8, W13,
W15, W16
W9, W10, W11,
W12
W14
X1