Real-time Application Exercises
Electrical and Computer Engineering
VIII. Delay Line Using Real-Time Application
By Prawat Nagvajara
Synopsis
The design implements a delay line, for example
used in signal processing [1] and audio effect
[2]. The design output voltage vOUT(t) is equal to
the input voltage vIN(t) delayed by  seconds,
i.e., vOUT(t) = vIN(t-). It uses Analog-to-Digital
Converter (ADC) [3], [4], to sample the analog
input voltage at a rate 1/TS samples per second.
The design application code implements the
delay line by storing the samples on an array
data structure. For an array size of D samples,
the design reproduces the input, delayed by TSD
seconds, by converting the sample to analog
output using a Digital-to-Analog Converter
(DAC) [5]. Figure 1 below shows a block
diagram describing the signal processing
involved where the ADC and DAC are hardware
peripherals and the array is a software object.
vIN(t)
vOUT(t)
ADC
array
Fig. 2 Schematic
DAC
The following figures show the configurations
for the ADC_SAR_SEQ (Fig. 3), the Timer_1 (Fig.
4), the IDAC (Fig. 5) and the Opamp (Fig. 6).
Fig. 1 Signal Processing Block Diagram
Schematic
Implementation of the delay line as a real-time
application using the PSoC creator consists of
the voltage ADC and DAC (Fig. 2). The voltage
DAC comprises the current DAC (IDAC) with an
external 8.7K Ohms load resistor and a unity
gain Opamp (voltage follower) [6]. The sample
period TS is defined by the timer_1 period. The
timer Terminal Count (tc) drives the interrupt
isr_clock. The interrupt routine code uses the
ADC GetResult16 API to store the sample in an
array data structure.
Fig. 3 ADC_SAR_SEQ Configuration
1
Real-time Application Exercises
Fig. 7 Pins Assignment
Code
The interrupt routine implements a delay using
circular buffer [7]. The buffer is declared as an
array int16 buf[D]. The routine sets IDAC value
with buf[ptr], stores the new ADC sample at the
same location and ptr++. The pointer ptr now
points to the value sampled at D samples
earlier. The pointer value is modulo D.
Fig. 4 Timer_1 Configuration
Fig. 5 IDAC Configuration
Fig. 6 Opamp Configuration
The pins are configured with Analog High
Impedance Drive. Pins assignment (Fig. 7) P1[5]
is specific for Opamp input V+ terminal and
P1[3] Opamp output, i.e. OA1:vout_x10 . P2[0]
is specific for SARMUX:in[0].
2
Real-time Application Exercises
time for the API IDAC_Set_Value((uint8)
buf[ptr]). The design can take into account
precisely these addition execution times and
provides better accuracy for the expected
delay.
Verification
Using a sine wave signal generator,
vIN(t) = Voffset + Vppsin2πFt,
Fig. 8 Delayed Square Waveform
Verification of the amplitude of the output
signal involves the comparison of the amplitude
measurement and the voltage drop across the
8.2K Ohms load resistor. This involves the ADC
sampled values and IDAC output current. The
peak-to-peak output voltage is 1.31V and the
input voltage is 200mV.
(1)
where Voffset = 1.1V, Vpp = 200mV.
The verification consists of the measuring the
input signal vIN(t) at Pin_4 and the output of the
design vOUT(t) at Pin_3 (see Fig. 2) on the
oscilloscope Channel 1 - vIN(t) and Channel 2 –
vOUT(t) for different values of sample period TS,
input signal frequency F, and delay D, for
instance,
An excerpt from the ADC Datasheet [8] “For
single-ended conversions with the Single ended
negative input parameter set to Vss, the
conversion is effectively 11-bit, because voltages
below Vss are illegal on any PSoC 4 pin. Because
of this, the “Unsigned” option of the Single
ended result format parameter is not available.
Noise on the +Input pin with a level slightly
below internal Vss, produces a result that is
negative.”
a) TS = 10μs, F = 500Hz and 1 KHz and D = 10
and 20 samples;
b) TS = 20μs, F = 500Hz and 1 KHz and D = 10
samples and 20 samples.
The measured time delays between the two
signals verify the design correctness. Figure 8
below shows a 500 Hz square wave verification
for TS = 10μs and D = 20 samples, which
corresponds to 200μs delay. The time
difference measured ∆x = 205μs. This is a 2.5%
error from the expected 200μs. The cause of
the error is due to the time for executing the
call to the interrupt routine and the execution
Thus the 200mV peak-to-peak input voltage
corresponds to 124 digital uint16 returned
value by ADC_SAR_SEQ_GetResult16(0). The
resolution is 3.3V/2047 = 1.61mV per digital
value. This corresponds to 148.8μA IDAC output
current (124 x 1.2uA per digital value). The
resolution of the IDAC current is 1.2 uA/bit (see
Fig. 5). Thus, the expected voltage drop across
3
Real-time Application Exercises
8.2K Ohms is 1.22V. The measured peak-topeak voltage is 1.31V (Fig. 8). The discrepancy is
due to the accuracy in ADC, IDAC values and the
resistor tolerance.
3. Understanding SAR ADCs: Their
Architecture and Comparison with
Other ADCs, Tutorial 1080, Maxim
Integrated, www.maximintegrated.
com/ en/app-notes/index.mvp/id/1080
Figure 9 below shows verification for 1 KHz sine
wave; sample period TS = 10μs and delay D = 10
samples; which corresponds to 100μs delay.
The top waveform is the input signal and the
bottom is the reproduced delayed signal. The
time difference measured ∆x = 110μs.
4. ADCS7476 Datasheet, Texas Instrument
www.ti.com/lit/ds/symlink/
adcs7476.pdf
5. Walt Kester, Basic DAC Architectures II:
Binary DACs, Analog Devices, Tutorials
MT-015 www.analog.com/media/en/
training-seminars/tutorials/MT-015.pdf
6. Bruce Carter and Thomas R. Brown,
Handbook of Operational Amplifier
Applications, Application, Report
SBOA092A –October 2001, Texas
Instrument,www.ti.com/lit/an/sboa092
a/sboa092a.pdf
7. en.wikipedia.org/wiki/Circular_buffer
Fig. 9 Delayed Sine Waveform
8. PSoC 4 Sequencing Successive
Approximation ADC PSoC® Creator™
Component Datasheet
Future Work
1. Using UART serial terminal to change the new
value of D in real-time. Verify the correctness.
9. en.wikipedia.org/wiki/Linear_phase
2. Input audio signal from a microphone and
output the delayed signal to a speaker.
Conclusions
Microcontroller real-time application and
peripherals such as ADC and DAC are ubiquitous
in analog signals processing. The design is in
fact the linear phase digital filter [9].
References
1. Digital Delay Line, en.wikipedia.org/
wiki/Digital_delay_line
2. Delay (Audio Effect) en.wikipedia.org/
wiki/Delay_(audio_effect)
4