Computer Science 246
Advanced Computer
Architecture
Spring 2008
Harvard University
Instructor: Prof. David Brooks
dbrooks@eecs.harvard.edu
Course Outline
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Instructor
Prerequisites
Topics of Study
Course Expectations
Grading
Class Scheduling Conflicts
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Instructor
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Instructor: David Brooks
(dbrooks@eecs.harvard.edu)
• Office Hours: TBD, MD141, stop by/email
whenever
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Prerequisites
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CS141 (or equivalent)
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Logic Design (computer arithmetic)
Basic RISC ISA
Pipelining (control/data hazards, forwarding)
i.e. Hennessey & Patterson Jr. (HW/SW
Interface)
C Programming, UNIX for Project (or similar
skills)
Compilers, OS, Circuits/VLSI background is
a plus, not needed
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Readings and Resources
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Text: “Computer Architecture: A
Quantitative Approach,” Hennessy and
Patterson
Key research papers (will be available on
the web or paper copies)
SimpleScalar toolset
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Widely used architectural simulator
SPEC2000 benchmarks
Will be used for some HW/Projects
Power/thermal modeling extensions available
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Course Expectations
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Lecture Material
• Short homework/quizzes to cover this material
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Seminar style part of course:
• Expectation: you will read the assigned papers
before class so we can have a lively discussion
about them
• Paper reviews –short “paper review”
highlighting interesting points,
strengths/weaknesses of the paper
• Bring discussion points to class
• Discussion leadership – Students will be
assigned to present the paper/lead the
discussions
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Course Expectations
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Course project
• Several possible ideas will be given
• Also you may come up with your own
• Depending on enrollment, I will schedule
weekly/bi-weekly meetings with each
individual/group (1/2hr per project) to discuss
results/progress
• There will be two presentations
–First, a short “progress update” (late April)
–Second, a final presentation scheduled at the
end of reading week
–Finally, a project writeup written in research
paper style
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Grading
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Grade Formula
• Homeworks and/or Quiz – 25%
• Class Participation – 25%
• Project (including final project presentation)–
50%
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Topics of CS246
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Introduction to Computer Architecture and
Power-Aware Computing
Modern CPU Design
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Deep pipelines/Multiple Issue
Dynamic Scheduling/Speculative Execution
Memory Hierarchy Design
Pentium Architecture Case Study
Multiprocessors and Multithreading
Embedded computing devices
Dynamic Frequency/Voltage Scaling
Thermal-aware processor design
Power-related reliability issues
System-Level Power Issues
Software approaches power management
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Readings from Previous Years
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High-level Power modeling (power abstractions)
Power Measurement for OS control
Temperature Aware Computing
Di/Dt Modeling
Leakage Power Modeling and Control
Frequency and Voltage Scheduling Algorithms
Power in Data Centers, Google Cluster Architecture
Dynamic Power Reduction in Memory
Disk Power Modeling/Management
Application and Compiler Power Management
Dynamic adaptation for Multimedia applications
Architectures for wireless sensor devices
Low-power routing algorithms for wireless networked devices
Intel XScale Microprocessor, IBM Watchpad
Human Powered Computing
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Why take CS246?
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Learn how modern computing hardware
works
Understand where computing hardware is
going in the future
• And learn how to contribute to this future…
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How does this impact system software
and applications?
• Essential to understand OS/compilers/PL
• For everyone else, it can help you write better
code!
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How are future technologies going to
impact computing systems?
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Architectural Inflection Point
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Computer architects strive to give
maximum performance with programmer
abstraction
• Compilers, OS part of this abstraction
• e.g. Pipelining, superscalar, speculative
execution, branch prediction, caching, virtual
memory…
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Technology has brought us to an
inflection point
• Multiple processors on a single chip -- Why?
–Design complexity, ILP/pipelining-limits,
power dissipation, etc
• How to provide the abstraction?
• Some burden will shift back to programmers
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Topics of Study
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Focus on what modern computer architects
worry about (both academia and industry)
Get through the basics of modern
processor design
Look at technology trends: multithreading,
CMP, power-, reliability-aware design
Recent research ideas, and the future of
computing hardware
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What is Computer Architecture?
Operating
System
Applications
(AI, DB,
Graphics)
Software
Instruction Set Architecture
Microarchitecture
System Architecture
Technology
Trends
Prog. Lang,
Compilers
Application
Trends
Hardware
VLSI/Hardware
Implementations
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Application Areas
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General-Purpose Laptop/Desktop
• Productivity, interactive graphics, video, audio
• Optimize price-performance
• Examples: Intel Pentium 4, AMD Athlon XP
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Embedded Computers
• PDAs, cell-phones, sensors => Price, Energy
efficiency, Form-Factor
• Examples: Intel XScale, StrongARM (SA-110)
• Game Machines, Network uPs => PricePerformance
• Examples: Sony Emotion Engine, IBM 750FX
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Application Areas
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Commercial Servers
• Database, transaction processing, search
engines
• Performance, Availability, Scalability
• Server downtime could cost a brokerage
company more than $6M/hour
• Examples: Sun Fire 15K, IBM p690, Google
Cluster
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Scientific Applications
• Protein Folding, Weather Modeling, CompBio,
Defense
• Floating-point arithmetic, Huge Memories
• Examples: IBM DeepBlue, BlueGene, Cray T3E,
etc.
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Moore’s Law
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Every 18-24 months
• Feature sizes shrink by 0.7x
• Number of transistors per die increases by 2x
• Speed of transistors increases by 1.4x
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But we are starting to hit some
roadblocks…
Also, what to do with all of these
transistors???
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Moore’s Law (Tx Density)
Transistors Per Die
1,000,000,000
Itanium2
100,000,000
Itanium
Pentium
III
10,000,000
PentiumII
Pentium
1,000,000
486
386
100,000
80286
8086
10,000
4004
1,000
1970
1980
1990
2000
2010
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How have we used these transistors?
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More functionality on one chip
• Early 1980s – 32-bit microprocessors
• Late 1980s – On Chip Level 1 Caches
• Early/Mid 1990s – 64-bit microprocessors,
superscalar (ILP)
• Late 1990s – On Chip Level 2 Caches
• Early/Mid 2000s – Chip Multiprocessors, On Chip
Level 3 Caches
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What is next?
• How much more cache can we put on a chip?
(Itanium2)
• How many more cores can we put on a chip?
(Niagara, etc)
• What else can we put on chips?
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Moore’s Law (Performance)
Relative Performance
1600
1400
1200
1000
Pentium III
Why has Performance
Outstripped Moore’s
Law?
800
DEC
Alpha
600
400
200
0
1984
1.58x per year
MIPS
R2000
1986 1988
IBM
Power1
1990
DEC
HP
Alpha
9000
1992 1994
HP 9000
1.35x per year
1996 1998
2000
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Performance vs. Technology
Scaling
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Architectural Innovations
• Massive pipelining (good and bad!)
• Huge caches
• Branch Prediction, Register Renaming, OOOissue/execution, Speculation (hardware/software
versions of all of these)
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Circuit/Logic Innovations
• New logic circuit families (dynamic logic)
• Better CAD tools
• Advanced computer arithmetic
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Power Dissipation Trends
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Power Density (W/cm )
1000
Nuclear Reactor
100
Pentium 4 (Prescott)
Pentium 4
Pentium 3
Hot Plate
Pentium 2
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Pentium Pro
Pentium
1
1980
386
486
1990
2000
2010
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Power Issues in Microprocessors
Capacitive (Dynamic) Power
Static (Leakage) Power
Vdd
Vin
VIN
Vout
VOUT
IGate
CL
ISub
CL
Di/Dt (Vdd/Gnd Bounce)
Voltage (V)
Current (A)
Temperature
20 cycles
Minimum Voltage
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Temperature/di-dt-Constrained
Power-Aware Computing Applications
Energy-Constrained Computing
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The Battery Gap
Diverging Gap Between Actual Battery Capacities and Energy Needs
5000
10kbps
64kbps
384kbps
Interactive
Energy (mAh)
4000
3000
2000
2Mbps
Downlink
dominated
PIM, SMS,
Voice
Mobile videoConferencing,
Collaboration
Video email,
Voice recognition,
Mobile commerce
Fuel Cells
Web browser,
MMS, Video clips
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Lithium
Polymer
Lithium Ion
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2000
2001
2002
2003
2004
2005
2006
2007
Battery
capacity
(mAh)
Energy
requirement
(mAh)
Source:
Anand
Raghunathan,
NEC Labs
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Where does the juice go in laptops?
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Others have measured ~55% processor
increase under max load in laptops
[Hsu+Kremer, 2002]
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Packaging cost
From Cray (local power generator and refrigeration)…
Source: Gordon Bell, “A Seymour Cray perspective”
http://www.research.microsoft.com/users/gbell/craytalk/
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Packaging cost
To today…
• IBM S/390: refrigeration:
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Provides performance (2% perf for 10ºC) and
reliability
Source: R. R. Schmidt, B. D. Notohardjono “High-end server low temperature cooling”
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IBM Journal of R&D
Intel Itanium packaging
Complex and expensive (note heatpipe)
Source: H. Xie et al. “Packaging the Itanium Microprocessor”
Electronic Components and Technology Conference 2002
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P4 packaging
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Simpler, but still…
Total Power-Related
PC System Cost ($)
40
30
20
10
0
0
10
20
30
40
Power (Watts)
From Tiwari, et al., DAC98
Source: Intel web site
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Cooking Aware Computing
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Server Farms
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Internet data centers are like heavy-duty
factories
• e.g. small Datacenter 25,000 sq.feet, 8000
servers, 2MegaWatts
• Intergate Datacenter, Tukwila, WA: 1.5 Mill. Sq.Ft,
~500 MW
• Wants lowest net cost per server per sq foot of
data center space
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Cost driven by:
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Racking height
Cooling air flow
Power delivery
Maintenance ease (access, weight)
25% of total cost due to power
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Environment
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Environment Protection Agency (EPA): computers
consume 10% of commercial electricity
consumption
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This incl. peripherals, possibly also manufacturing
A DOE report suggested this percentage is much lower
(3.0-3.5%)
No consensus, but it’s still a lot
Interesting to look at the numbers:
– http://enduse.lbl.gov/projects/infotech.html
Data center growth was cited as a contribution to the
2000/2001 California Energy Crisis
Equivalent power (with only 30% efficiency) for AC
CFCs used for refrigeration
Lap burn
Fan noise
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Now we know why power is important
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What can we do about it?
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Two components to the problem:
• #1: Understand where and why power is
dissipated
• #2: Think about ways to reduce it at all levels of
computing hierarchy
• In the past, #1 is difficult to accomplish except
at the circuit level
• Consequently most low-power efforts were all
circuit related
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Modeling + Design
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First Component (Modeling/Measurement):
• Come up with a way to:
–Diagnose where power is going in your
system
–Quantify potential savings
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Second Component (Design)
• Try out lots of ideas
• Or characterize tradeoffs of ideas…
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This class will focus on both of these at
many levels of the computing hierarchy
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Next Time
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Course website:
http://www.eecs.harvard.edu/~dbrooks/cs246
Some readings for next week:
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Web Page Browsing:
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“Power-Aware Microarchitecture: Design and Modeling
Challenges for Next-Generation Microprocessors,” IEEE
MICRO.
“Power: A First-Class Architectural Design Constraint,”
IEEE Computer
“Thermal Crisis: Challenges and Potential Solutions”
Information Technology and Resource Use
– http://enduse.lbl.gov/projects/infotech.html
Sun’s ECO-responsible data center
– http://www.sun.com/aboutsun/environment/epa.jsp
Questions?
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