ELE 2110A Electronic Circuits
Week 11: Differential Amplifiers
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Lecture 11 - 1
Topics to cover …
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Large signal analysis
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AC analysis
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Half-circuit analysis
Reading Assignment:
Chap 15.1-15.8 of Jaeger and Blalock or
Chap 7.1 - 7.3, of Sedra and Smith
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Lecture 11 - 2
BJT Differential Pair
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z
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Two identical transistors with emitters shorted together, connecting to a
resistor or a current source. Transistors operate in active mode.
Designed to amplify voltage difference between the two inputs
One of the most used circuit building blocks
– E.g., as the input stage of opamps
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Lecture 11 - 3
Large Signal Analysis
I = i E 1 + i E 2 = iC 1 / α + iC 2 / α
⇒
αI
iC 1
⇒ iC 1 =
=
iC 2
+1
iC 1
αI
iC 2
+1
iC 1
iC 1 =
iC 2
αI
1 + e − vid / VT
αI
=
1 + e + vid / VT
iC 1 = I S e v BE 1 / VT
iC 2 = I S e v BE 2 / VT
iC 1 / iC 2 = e ( v BE 1 − v BE 2 ) / VT = e vid / VT
where v BE 1 − v BE 2 = v B 1 − v B 2 = vid
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Lecture 11 - 4
Large Signal Analysis
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|vd| = |vB1-vB2| < VT for use as a
linear amplifier
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For |vd| > 4VT (≈100mV), the tail
current flows almost entirely in
one of the two transistors
– This high sensitivity makes the
differential pair a fast current
switch
– The transistors are either in active
mode or in cutoff mode
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Also contributes to high switching
speed
Lecture 11 - 5
MOS Differential Pair
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Lecture 11 - 6
Large Signal Analysis
Assuming identical devices and neglecting the output
resistance and body effect, the drain currents are
⎧
2
1 ' W
=
−
i
k
(
v
V
)
⎪ D1 2 n L GS 1 t
⎨
W
⎪iD 2 = 12 k n'
(vGS 2 − Vt ) 2
L
⎩
⎧
⎪⎪ iD1 =
⎨
⎪ i =
⎪⎩ D 2
Since,
W
(vGS 1 − Vt )
L
1 ' W
(vGS 2 − Vt )
2 kn
L
1
2
k n'
Fig. 6.29 The MOSFET differential pair.
vGS1 − vGS 2 = vid
We have
iD1 − iD 2
Solving eqs (1) & (2) yields
W
= 12 k n' vid (1)
L
The current-source bias imposes the
constrain
iD1 + iD 2 = I
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(2)
⎧
(vid / 2) 2
I
⎛ vid ⎞
' W
⎪iD1 = + k n I ⎜ ⎟ 1 −
W
L ⎝ 2 ⎠
2
⎪
I k n'
⎪
L
⎨
2
⎪i = I − k ' W I ⎛ vid ⎞ 1 − (vid / 2)
⎜ ⎟
n
⎪ D2 2
L ⎝ 2 ⎠
' W
I
k
⎪
n
L
⎩
Lecture 11 - 7
Large Signal Analysis
At the bias point, vid = 0, leading to iD1 = iD 2 =
Correspondingly, vGS1 = vGS 2 = VGS
where
I 1 'W
2
= k n (VGS − Vt )
2 2 L
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I
2
2
⎧
⎞
⎛
/
2
I
I
v
v
⎛ id ⎞
⎪iD1 = +
⎟⎟
⎜ ⎟ 1 − ⎜⎜ id
⎪⎪
2 VGS − Vt ⎝ 2 ⎠
V
V
−
t ⎠
⎝ GS
∴⎨
2
⎪
⎞
⎛
I
I
v
v
/
2
⎛ id ⎞
⎟⎟
⎜ ⎟ 1 − ⎜⎜ id
⎪iD 2 = −
2
2
V
V
V
V
−
−
⎠
⎪⎩
GS
t ⎝
t ⎠
⎝ GS
Lecture 11 - 8
Large Signal Analysis
For vid / 2 << VGS − Vt (small signal approximation)
⎧
I
I
⎛ vid ⎞
⎪⎪iD1 = 2 + V − V ⎜ 2 ⎟
⎠
GS
t ⎝
⎨
I
⎛ vid ⎞
⎪iD 2 = I −
⎜ ⎟
⎪⎩
2 VGS − Vt ⎝ 2 ⎠
Since g m =
2( I / 2)
I
=
VGS − Vt VGS − Vt
We have the signal component id of iD as
At full switching situation (that is, iD1=I and
iD2=0, or vice versa), the value of vid is:
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id = g m (vid / 2)
vid
max
= 2 (VGS − Vt )
Lecture 11 - 9
Topics to cover …
z
Large signal analysis
z
AC analysis
z
Half-circuit analysis
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Lecture 11 - 10
Modeling Inputs
Common-mode component:
(the average)
Differential-mode component:
(the difference)
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v1 + v2
vic =
2
vid = v1 − v2
Lecture 11 - 11
Differential Mode Input
0
Analyze the circuit by
superposition of DM and CM signals
vid
2
First set the common-mode input to 0:
−
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Lecture 11 - 12
AC Analysis for Differential-Mode Input
−
vid
2
v
v = id − ve
3 2
v
v
v
3
4
Ignoring ro, we have gmv3 + + gmv4 + = e
rπ
rπ R
EE
v
1
( gm + )(−2ve) = e
R
rπ
EE
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ve = 0
v
v = − id − ve
4
2
v
1
(gm + )(v + v ) = e
rπ 3 4 R
EE
Emitter = AC ground for DM input.
No bypass cap is needed!
Lecture 11 - 13
Voltage Gain for Differential Output
−
∴v = v / 2
3 id
v
v = − gm R id
c1
C 2
vid
2
v = −v / 2
4
id
v
v = + gm R id
c2
C 2
Differential output:
v = v − v = − gm R v
C id
od c1 c2
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ve = 0
Differential-mode gain is:
v
A ≡ od
= − gm R
C
dd v
id v = 0
ic
Lecture 11 - 14
Voltage Gain for Single-ended Output
−
vid
2
v
v = − gm R id
c1
C 2
ve = 0
v
v = + gm R id
c2
C 2
If either vc1 or vc2 is used alone as output, output is said to be singleended.
A
v
g R
m
C = dd
A ≡ c1
=−
dd1 v
2
2
id v = 0
ic
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A
v
g R
m
C = − dd
A
≡ c2
=
dd 2 v
2
2
id v = 0
ic
Lecture 11 - 15
Differential-Mode Input Resistance
−
vid
2
ve = 0
Differential-mode input resistance:
v
∴R ≡ id = 2rπ
id i
b1
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since
(v / 2 )
i = id
b1
rπ
Lecture 11 - 16
Output Resistances
−
vid
2
ve = 0
Differential-mode output resistance is the resistance seen
between VC1 and VC2:
R = 2(R r ) ≅ 2R
C o
C
od
Single-ended output resistance is the resistance seen
between VC1 (or VC2) and ground:
R ≅R
C
od
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Lecture 11 - 17
Common Mode Input
0
0
Set differential-mode input to 0:
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Lecture 11 - 18
AC Analysis for Common-Mode Input
Ignoring ro:
2(1 + β )ib =
ve = vic − ib rπ
Output voltages are:
ve
REE
Circuit is symmetrical
v
ic
i =
b r + 2(β +1 )R
π
EE
− βR
C
v = v = − βi R =
c1 c2
b C r + 2(β +1 )R
π
R
v ≅ C v
ic
ic 2R
EE
EE
Differential output = 0
Common-mode voltage gain for single-ended output
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Lecture 11 - 19
Emitter Voltage
Circuit is symmetrical
v
ic
i =
b r + 2(β +1 )R
π
EE
ve = 2(β +1 )i R =
b EE
2(β +1 )R
EE v ≅ v
ic ic
rπ + 2(β +1 )R
EE
Emitter not AC ground for CM input.
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Lecture 11 - 20
Common-Mode Input Resistance
Circuit is symmetrical
CM input resistance is the resistance seen between the shorted bases
(Vic) and ground:
rπ + 2(β +1 )R
v
r
ic
EE = π +(β +1 )R
R =
=
ic 2i
EE
2
2
b
Two ib are drawn from the input voltage source consisting two parallel Vic.
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Lecture 11 - 21
Common-Mode Rejection Ratio
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CMRR is defined as
Adm
CMRR ≡
Acm
– represents ability of amplifier to amplify desired DM input signal and
reject undesired CM input signal.
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For output defined differentially, the common-mode gain of
a balanced amplifier is zero Æ CMRR is infinite
– Many noises appear in common form to the input and thus do not
appear at the output
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Lecture 11 - 22
Resistor Mismatch
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Consider mismatches between RC (which always exists):
R
v ≅ − C1 v
ic
c1 2R
EE
R
v ≅ − C2 v
ic
c2
2R
EE
Δ+
-Δ
R −R
∆R R
2
1
C
C
v = v −v ≅
v = C C v
ic R 2R
ic
od c1 c2
2R
EE
EE
C
where
RC1 − RC 2
∆RC
=
(RC1 + RC 2 ) / 2
RC
represents fractional mismatch
⎛
⎞
⎜
⎟
g
R
R
∆
Adm
m C
⎜
⎟
C
∴ CMRR ≡
=
= gm R ⎜
EE ⎜ R ⎟⎟
Acm ∆R
R
⎜
C
C
C ⎟⎠
⎝
R 2R
EE
C
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−1
REE should be maximized
for good CMRR
Lecture 11 - 23
DM and CM Gains
Define the DM and CM
outputs as
v =v −v
od c1 c2
v
voc = c1
+v
c2
2
Output and input are related
by the gain matrix:
A
⎡v
⎤
⎢ od ⎥
dd
⎢
⎥=
A
⎢⎣ voc ⎥⎦
dc
⎡
⎢
⎢
⎢
⎢⎣
v ⎤
A
cd id ⎥⎥
Acc vic ⎥⎦
⎤⎡
⎥⎢
⎥⎢
⎥⎢
⎥⎦ ⎣
where
Add = differential-mode gain
Acd = common-mode to differential-mode
conversion gain
Acc = common-mode gain
Adc = differential mode to common-mode
conversion gain
For ideal symmetrical amplifier,
Acd = Adc = 0.
⎤ ⎡v
⎤
⎡v
⎤ ⎡A
0
⎢
⎥
⎢
id ⎥
∴⎢⎢ od ⎥⎥ = ⎢ dd
⎥⎢
v ⎥
⎢⎣ voc ⎥⎦ ⎢ 0 Acc ⎥ ⎢ ic ⎥
⎦
⎣
⎦⎣
Purely differential-mode input gives purely
differential-mode output and vice versa.
ELE2110A © 2008
Lecture 11 - 24
Topics to cover …
z
Large signal analysis
z
AC analysis
z
Half-circuit analysis
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Lecture 11 - 25
Half-Circuit Analysis
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Redraw the differential amplifier in a fully
symmetrical form
– power supplies are split into two equal
halves in parallel
– emitter resistor is separated into two equal
resistors in parallel
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For differential mode signals, points on
the line of symmetry are grounds for ac
analysis
– VCC and VEE are AC grounds
– ve is AC ground as proven previously
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For common-mode signals, points on line
of symmetry are replaced by open circuits
– b/c no current flows across the line of
symmetry
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Lecture 11 - 26
Differential-mode Half-circuits
Direct analysis of the half-circuits yield:
v
= − gm R id
c1
C 2
v
v = + gm R id
c2
C 2
v
vo = v
c1
−v
c2
= − gm R v
C id
R = v / i = 2rπ
id id b1
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The two power supply lines and
emitter become ac grounds
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The half-circuit represents a C-E
amplifier stage
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R = 2( R ro )
C
od
Lecture 11 - 27
Common-mode Half-circuit
For DC
For AC
Half circuit
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All points on line of symmetry become open circuits
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Lecture 11 - 28
Common-mode Input Voltage Range
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The CM input signal range for small-signal
assumption to be valid is similar to that of an
emitter-degenerated CE amplifier:
vic ≤ 5mV (1 + g m 2 REE )
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REE is very large in most cases
Æ Wide common-mode input range
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Lecture 11 - 29
CM Input Voltage Range
Another condition is that BJT must be in active mode:
=V
− I R −V ≥ 0
V
CB CC C C IC
V −V
+V
BE
EE
IC
I =α
C
2R
EE
α R ⎛⎜⎜V −V ⎞⎟⎟
V
− C ⎝ EE BE ⎠
CC
2R
EE
∴V ≤
IC
αR
C
1+
2R
EE
For example, if VCC=VEE, VEE >> VBE, and RC = REE,
V
V ≤ CC
IC
3
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Lecture 11 - 30
Biasing with Current Source
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Differential amplifiers biased using current
sources has
– A more stabilized operating point
– A higher effective value of REE to improve
CMRR
V
I
=I − 0
DC SS R
SS
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Equivalent of Iss
Lecture 11 - 31
DC Analysis
IS = ISS /2.
DC Half-circuit
K
2
= n ⎛⎜⎜V −V ⎞⎟⎟
D
GS TN ⎠
2 ⎝
I
2I
D =V
V
=V
+
+ SS
TN
GS TN
Kn
Kn
I
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V
D1
V
=V
DS
D2
=V
DD
=0
− I R and V
D D
OD
= V −V = V
− I R +V
D S
DD D D GS
Lecture 11 - 32
Example
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z
z
Problem: Find Q-points of transistors in the differential amplifier and
the upper limit of input CM voltage.
Given data: VDD=VSS=12 V, ISS =200 µA, RSS = 500 kΩ, RD = 62 kΩ,
λ = 0.0133 V-1, Kn = 5 mA/ V2, VTN =1V
Analysis:
I
I
= SS = 100 µA
D
2
V
= 1+
GS
V
DS
200 µA
= 1.20V
2
5mA/V
= 12V - (100µA)(62kΩ) +1.2V = 7V
To maintain pinch-off operation of M1 for nonzero VIC ,
V
= V - ⎛⎜⎜V
- I R ⎞⎟⎟ ≤ V
GD
IC ⎝ DD D D ⎠ TN
∴V ≤ V
- I R +V
= 6.8V
DD D D TN
IC
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Lecture 11 - 33
Half Circuit for Differential-mode Input
Gain for DM output is
ac ground
v
A = od
dd v
id v
= − gm R
ic
=0
D
Gain for single-ended output is
Half Circuit
v
v = − gm R id
D 2
d1
v
v = + gm R id
D 2
d2
∴v = − gm R v
D id
od
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A
gm R
1
d
D
A
=
=−
= dd
dd 1 v
2
2
id v = 0
ic
v
A
v
gm R
2
d
D
A
=
=+
= − dd
dd 2 v
2
2
id v = 0
ic
DM input and output resistance:
R =∞
id
R = 2R
D
od
Lecture 11 - 34
Reference Equations
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Lecture 11 - 35
Half Circuit for Common-mode Input
Half Circuit
Rss = Two 2Rss in parallel
Common-mode half-circuit = common-source
amplifier with 2RSS as source resistor
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Lecture 11 - 36
AC Analysis for CM Input
− gm R
D v
v =v =
ic
d1 d 2 1+ 2 g R
m SS
Common-mode gain:
gm R
R
voc
D
Acc =
=−
≅− D
v
1+ 2 g m R
2R
ic v = 0
SS
SS
id
Half Circuit
CM input to DM output conversion gain = 0 because
v = v −v = 0
od d1 d 2
Common-mode input resistance:
R =∞
ic
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Lecture 11 - 37
Common-Mode Rejection ratio
z
For DM output,
Adm Adm
CMRR =
=
→∞
Acm
0
– Mismatch will result in finite CMRR as in the BJT differential pair.
z
For single-ended output,
Adm Add / 2 − ( gm RD ) / 2
=
=
= gmR
CMRR =
SS
Acm
Acc
− R /(2R )
D
SS
– RSS should be maximized
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Lecture 11 - 38
Class Exercise
Draw the common-mode and differential-mode half circuits for the
differential pair shown below.
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Lecture 11 - 39
Summary
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Properties of the differential pair
– It amplifies difference between input voltages and reject their
common-mode component
z
Most noises, such as power supply noise, appear to be common
mode signal and not amplified by the amplifier.
– CMRR represents its ability to reject CM input signal.
– It can produce AC ground (for DM input) at emitter without using
bypass capacitors
– Input common mode range is very wide
z
Half circuit analysis technique
– Points on the line of symmetry are open-circuits for CM signal
– Points on the line of symmetry are AC grounds for DM signal
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Lecture 11 - 40