Electronic II (ECE235b)
Differential Amplifiers
Anestis Dounavis
The University of Western Ontario
Faculty of Engineering Science
Differential Amplifiers



Differential amplifiers are the most widely used building blocks in analog IC design. For
instance, the input stage of every op amp is a differential pair.
Main reasons why differential amplifiers are well suited for IC fabrication: 1) capable of
providing matched devices 2) IC technology provides the availability of large number
transistors at relatively low cost. (Note differential amplifiers require twice as many transistors
than single ended circuits).
Differential amplifiers have the following advantages over single stage amplifiers: 1) they are
less sensitive to noise 2) they can be connected to other stages without the need of large bypass
or coupling capacitors.
7.3 The BJT Differential Pair
Figure 7.12 shows the basic BJT differential-pair configuration which consists of 2 matched transistors
Q1 and Q2.
Figure 7.12 The basic BJT differential-pair configuration.
The current source I is usually implemented by current mirrors.
7.3.1 Basic Operation
To see how the BJT differential pair works, consider first the case when the 2 bases are joined together
and connected to a common-mode voltage (Figure 7.13a)
Figure 7.13 (Continued) (c) The differential pair with a large differential input signal of polarity
opposite to that in (b). (d) The differential pair with a small differential input signal vi. Note that we
have assumed the bias current source I to be ideal (i.e., it has an infinite output resistance) and thus I
remains constant with the change in vCM.


Since the transistors Q1 and Q2 are matched, and assuming and ideal current source I, then the
current I will divide equally between the 2 devices.
If vCM varies as long as the transistors remain in active region the current I will still be divided
equally. Thus the differential pair does not respond to or rejects common-mode input signals
Next, let v B1  1 V and v B 2  0 .
 With this differential input, Q1 is on and Q2 is turned off.
Next, let v B1  1 V and v B 2  0 .
 With this differential input, Q1 is off and Q2 is turned on.
From this analysis, we see that the differential pair certainly responds to large difference mode (or
differential) signals. In fact with relatively small difference voltages we are able to steer the entire bias
current from one side of the pair to the other.
In Figure 7.13d, the BJT amplifier has a common mode input and a small differential input (a few
millivolts), which results in one transistor conducting a current of I/2+I and the other transistor having
a current of I/2-I.
 The output voltage between the 2 collectors is 2IRC .
Exercise 7.7
Find v E , vC1 , vC 2 . Assume | v BE | is 0.7V and   1 .
7.3.2 Large Signal Operation
Let the voltage at the common emitter be v E , thus the exponential relationship applied to each
transistor in Figure 7.12 can be written as:
I
i E 1  S e ( vB 1  vE ) / VT

I
i E 2  S e (v B 2 v E ) / VT

Combining these 2 equation yields
iE1
(v  v ) / V
 e B1 B 2 T
iE 2
The above equations can be manipulated to yield
iE1
1
1


(v B 2 v B1 ) / VT
iE1  iE 2 1  iE 2 / iE1 1  e
iE 2
1
1


( vB 1 v B 2 ) / V T
iE1  iE 2 1  iE1 / iE 2 1  e
In addition, the currents must satisfy
i E1  i E 2  I
The differential voltage is defined as
v B1  v B 2  vid
Thus
iE1  iE 2
I
(Eq 1)

(v B 2 v B1 ) / VT
1 e
1  e  vid / V T
iE1  iE 2
I
(Eq2)
iE 2 

(v B1  vB 2 ) / VT
v /V
1 e
1  e id T
The collector currents are obtained by multiplying Eq1 and Eq2 by .
 The fundamental operation of the differential amplifier is illustrated by Eq 1 and 2.
 Note that the amplifier responds to the difference voltage vid .
 Also relatively small voltage difference vid , will cause the current I to flow almost entirely in
iE1 

one direction. Note that a voltage difference of 4VT  100mV is enough to switch the current
from one side to another. Thus the BJT differential amplifier can be used as a fast switch.
Figure 7.14 shows the plot of the currents as a function of vid .
Figure 7.14 Transfer characteristics of the BJT differential pair of Fig. 7.12 assuming a . 1.

To remain in the linear region for small signal analysis the difference input is limited to
2VT  50mV
A technique to extend the differential input is to include 2 equal emitter resistances as shown in Figure
7.15.
Figure 7.15 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the
linear range of operation can be extended) by including resistances in the emitters.


The resulting transfer characteristics for 3 different emitter resistances are sketched in Figure
7.15b.
Thus increasing the emitter resistance increases the linear region at the price of reducing gain.
7.3.3 Small Signal Operation
Figure 7.16 shows the differential pair with vid applied.
Figure 7.16 The currents and voltages in the differential amplifier when a small differential input
signal vid is applied.
In Figure 7.16 it is implied that a DC common mode input voltage has been somehow established.
Collector Currents when differential voltage is applied
From Eq1 and Eq2 the collector currents can be expressed as
I
i C1 
1  e v id / VT
I
iC 2 
1 e vid / VT
Or by multiplying the numerator and denominator by e vid / 2VT gives
Ie vid / 2V T
i C1  vid / 2VT
e
 e vid / 2VT
Assuming that vid  2VT , we can then expand the exponential as a 2 term series:
 I (1  vid /( 2VT ))
 I I vid
i C1 


(Eq3)
(1  vid /( 2VT ))  (1  vid /( 2VT ))
2 2VT 2
A similar manipulation of iC 2 yields
I  I vid
iC 2 

(Eq4)
2 2VT 2
 When vid  0 , the bias current I divides equally between the 2 transistors.
 When a small signal is applied at vid , iC1 increases by an increment ic and iC 2 decreases by an
increment ic , where the increment ic is given by:
v
I vid
ic 
 g m id
(Eq5)
2VT 2
2
IC
I

where g m 
VT 2VT
 vid /2 of Eq5 imply that the vid voltage applied is divided equally between the 2 transistors due
to symmetry.
An Alternative Viewpoint
Consider Figure 7.17. The emitter resistance is defined as
V
V
re  T  T
IE I / 2
Thus the small signal current ie is
v
I vid
i e  id 
2 re 2VT 2
The small signal ic is
v
v
I vid
i c  i e  id 
 g m id
2 re
2VT 2
2
Figure 7.17 A simple technique for determining the signal currents in a differential amplifier excited
by a differential voltage signal vid; dc quantities are not shown.
Figure 7.18 A differential amplifier with emitter resistances. Only signal quantities are shown (in
color).
For the case when resistances are included in the emitters, as shown in Figure 7.18, the small signal
currents become
v id
v id
ie 
i c  i e 
2( re  RE )
2( re  RE )
Input Differential Resistance
Rid 
v id
 (   1)re
id
(for Figure 7.17)
Rid 
v id
 (   1)( re  RE )
id
(for Figure 7.18)
Differential Voltage Gain
If the output is taken differentially (between the 2 collectors), then the differential gain will be
v  
v 

  g m RC id    g m RC id 
v v
2  
2 
(for figure 7.17)
Ad  c1 c 2  
  g m RC
vid
v id
If the output is measured at one end say between the collector of Q1 and ground then
1
Ad ,1   g m RC
(for figure 7.17)
2
For the differential amplifier with resistances the differential gain (between the 2 collectors) is
v  vc 2
  ( 2 RC )
RC
Ad  c1


(for figure 7.18)
vid
2(re  RE )
re  RE
Equivalence of the Differential Amplifier to a Common-emitter Amplifier
The results obtained above are similar to those obtained for the common-emitter amplifier. This is
illustrated in Figure 7.19. (Figure 7.19 includes the output resistance R EE of the biased current source.)
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

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In many cases the input signal is as shown in Figure 7.20. In this case the voltage at the emitter
is not zero and the R EE resistance will effect the operation.
However if R EE is large ( R EE  re ) which is usually the case then the differential voltage vid
is still divided equally.
Since in Figure 7.19, vc 2  v c1 , the 2 transistors yield similar results, thus only side one is
needed to analyze the differential small-signal operation of the differential amplifier.
This circuit is referred to as the differential half-circuit and is shown in Figure 7.21
Figure 7.19 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers
in (b). This equivalence applies only for differential input signals. Either of the two common-emitter
amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency
response, and so on, of the differential amplifier.
Figure 7.20 The differential amplifier fed in a single-ended fashion.
Figure 7.21 (a) The differential half-circuit and (b) its equivalent circuit model.
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
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The model parameters r  , g m and r o are evaluated at the biased current I/2.
The differential voltage gain (between the 2 collectors) of the half circuit is
v c1
Ad 
  g m ( RC || ro )
(v id / 2)
The input differential resistance of the differential amplifier is twice that of the half-circuit that
is 2r  .
The differential half-circuit for Figure 7.18 is common emitter transistor with a resistance R e in
the emitter.
Common-Mode Gain and CMRR
Figure 7.22(a) shows a differential amplifier with common-mode voltage vicm . From the symmetry of
the circuit an equivalent circuit representation is shown in Figure 7.22b.
Figure 7.22 (a) The differential amplifier fed by a common-mode voltage signal vicm. (b) Equivalent
“half-circuits” for common-mode calculations.
 In Figure 7.22b the transistors Q1 and q2 are biased at I/2 and have a resistance 2 R EE .

The common-mode output voltage is
v c1  vc 2  v icm




RC
RC
 vicm
2 REE  re
2 REE
If the output in taken differentially, then the output common-mode voltage
v o  v c1  vc 2  0
If voltage is measure at one end only, the common mode gain is
 RC
RC
Acm  

(Eq6)
2 REE  re 2 REE
1
Since the differential gain at one end is Ad ,1   g m RC , the common-mode rejection ration
2
(CMRR) is
A
CMRR  d  g m R EE
Acm
The CMRR in dB is
CMRR  20 log

Ad
Acm
The circuit of Figure 7.22b is called the common-mode half-circuits.
The above analysis assumes that the circuit is perfectly matched. In practice circuits are not perfectly
symmetrical, with the result that the common-mode gain will not be zero even if the output is taken
differentially.
 To illustrate this point consider the case of perfect symmetry except for a mismatch RC (i.e. let
the resistance at Q1 be RC and the resistance at Q2 be RC  RC .
 The voltages at the collector are:
RC
v c1  vicm
2R EE  re
 ( RC  RC )
v c 2  vicm
2 REE  re
 Thus the output voltage across the 2 collector nodes are:
RC
v o  vc1  v c 2  v icm
2 REE  re
 The common mode gain due to the mismatch will be
 RC
RC
R R C
Acm 

 C
2 REE  re 2 REE 2 REE RC
 The common mode gain due to the mismatch is much smaller than Eq6. Therefore the input
differential stage of an op amp is always a balanced one, with the output taken differentially.
The output voltage can be expressed as
 v  v2 
v o  Ad ( v1  v 2 )  Acm  1

 2 
Input Common-Mode Resistance
The definition of the common-mode input resistance is shown in Figure 7.23.
Figure 7.23 (a) Definition of the input common-mode resistance Ricm. (b) The equivalent commonmode half-circuit.
The input resistance of Figure 7.23b) can be expressed as (see section 6.9 for derivation)
2 Ricm  (   1)(2 REE || r0 )
or
r
Ricm  (   1)( REE || 0 )
2
Example 7.1 (Sedra and Smith)
Calculate
1. The input differential resistance
2. Overall differential gain voltage gain
3. The worst-case common-mode voltage gain if the 2 collector resistances are accurate within
 1% .
4. The CMRR in dB.
Example 7.4 (Sedra and Smith)