A NEESH N AINANI
(+1)650-521-2623; aneesh_nainani@amat.com,nainani@stanford.edu
Personal Information
• Biography : Aneesh Nainani was born in Rajasthan, India. He received his B.Tech and
M.Tech degrees in electrical engineering from the Indian Institute of Technology Bombay,
Mumbai, India, both in 2007 and the Ph.D. degree in electrical engineering from Stanford
University, Stanford, CA, in 2011. During his graduate studies, he was an intern at
CEA-LETI, IBM Microelectronics, SEMATECH, and Applied Materials, Inc. He is currently
a Senior Technologist with Applied Materials, Santa Clara, CA, and also holds a Lecturer
and Visiting Scholar appointment at Stanford University. He currently serves on the
technical working group at IRTS and on the Technical Advisory Board for Device Sciences
at SRC. He has published more than 40 papers on III-V CMOS, nanocrystal flash memory,
and thin-film solar cells. His research interests are in the physics and technology of
semiconductors devices.
Dr. Nainani was a recipient of several awards, including the Intel PhD Fellowship, the
School of Engineering Fellowship from Stanford University, and the National Talent
Scholarship from the Government of India
• Present Title Senior Technologist, Applied Materials, Santa Clara, CA
Lecturer, Stanford University, Stanford, CA
Visiting Scholar, Stanford University, Stanford, CA
• Citizenship- Indian, US Permanent Resident
• Education PhD, Electrical Engineering, Stanford University, 2007-2011, GPA-3.96/4.0
B.Tech and M.Tech, Electrical Engineering, Indian Institute of Technology (IIT)-Bombay,
2002-2007, GPA-9.1/10
• URL - www.stanford.edu/∼nainani
Awards and Honors
• Recipient of Intel PhD Fellowship for Academic Year 2009-10 .
• Gold Medal at Indian National Physics Olympiad 2002.
• Selected for the International Physics Olympiad Training Camp 2002 and Ranked 9th
throughout India.
• Recipient of National Talent Scholarship (NTS) awarded to only 750 students across India.
• Recipient of Science Talent Award given to only 20 students across the state.
• Fellowship for PhD studies from School of Engineering, Stanford University for the year
2007-8 .
• Academic Scholarship by IIT-Bombay for the year 2005-06.
Professional Activities
• Member of Technical Working Group at International Technology Roadmap for
Semiconductors (ITRS)
• Member of Technical Advisory Board for Device Sciences at Semiconductor Research
Corporation (SRC)
• Ad hoc reviewer : IEEE Electron Device Letters, IEEE Transactions on Electron Devices,
Solid State Electronics
Talks Delivered
• 2012 : Dec : San Francisco, IEDM 2012 May : Invited ECS 2011, Seattle ; March : Invited
Synopsys Inc., Mountain View
• 2011 : January : Intel Corporation, Santa Clara, CA; February : IMEC, Belgium; TSMC,
Belgium; IBM Research, Yorktown, NY; March : Mayo Clinic, Rochester, MN
• 2010 : May : INMP, Stanford, CA;August : Intel Corporation, Hilsboro, OR; September :
SISPAD 2010, Bolognia, Italy; SSDM 2010 , Tokyo, Japan; Applied Materials, Santa Clara
CA; November : Agilent Technologies, Santa Rosa, CA; December : IEDM 2010, San
Francisco, CA; Global Foundries, Sunnyvale, CA, invited IEEE EDS Seminar, IIT-Bombay,
Mumbai, India
• 2009 : September : SISPAD 2009, San Diego, CA; Sematech, Austin, TX; October : SSDM
2009 , Sendai, Japan;December : IEDM 2009, Baltimore, MD; IIT-Bombay, Mumbai, India
• 2008 :January : invited Intel Corporation, Santa Clara, CA; September : IBM, Hopewell
Junction, NY
• 2007 :March : ICMTD 2007, Giens, France; July : IPFA 2007, Bangalore, India; September :
CEA-LETI, Grenoble, France; December: IEDM 2007, Washington, DC
Work Experience
• Applied Materials, Santa Clara, USA (June-2011 to present)
Conducting research activities and path finding work for advance logic and advance
memory devices that are critical to Applied Materials business. I also play a key role in the
external engagements of Applied Materials with other semiconductor companies and
universities and its Global R&D efforts.
• Lecturer, Department of Electrical Engineering, Stanford University (Sep-2012 to present)
I developed and taught a new graduate level course EE292L on Nanomanufactuing. I also
have also taught EE216: Principals and Models of Semiconductor Devices and co-taught
EE311: Advanced Integrated Circuits Technology
I use an adapted version of flip-classroom model in all my classes where classroom lectures
are supplemented with short screencast videos made by me.
URL for classes: http://nano.class.stanford.edu , http://devices.class2go.stanford.edu
• Research Assistant, Center of Integrates Systems, Stanford University, Stanford, USA (Sept
2007-June 2011)
Conducted independent research work on variety of semiconductor devices. Lead on
project on Sb-based III-V MOSFET devices. Work involved fabrication of devices at the
Stanford Nanofabrication Facility and their characterization at Stanford
Nanocharacterization Lab. Also explored the physics and device issues in : Ge based
semiconductor devices, Tunneling contacts, NAND flash memory etc.
• Summer Intern, Applied Materials, Santa Clara, USA (June-Sept 2010)
Worked on modeling of high efficiency thin film solar cells. Full 3D optical simulations
were combined with 3D electrical simulations to evaluate the impact of different advanced
cell designs on efficiency improvement and identify possible show stoppers.
• Summer Intern, SEMATECH, Austin, USA (June-Sept 2009)
Worked in semiconductor characterization lab, focused on wafer bending experiments.
Studied the effect of uniaxial stress on III-V semiconductors and flash memory.
Piezoresistance coefficients were calculated for channel candidates for III-V CMOS.
• Summer Co-op, IBM Semiconductor Research and Development Center (SRDC), Hopewell
Junction, USA (June-Sept 2008)
Worked on the characterization and modeling of electrically programmable FUSE (eFUSE).
Did 3D electrical and thermodynamic analysis for the device which could identify the
cause of the problems being faced by the development team. TCAD was used to propose
an optimum design for eFUSE. Characterization of the devices was performed to tie up
modeling with actual data and verify some of the insights from modeling.
• Visiting Researcher, Micro and Nanotechnology Innovation Center (MINATEC), Grenoble,
France (July-Sept 2007)
Looked at various issues in advanced non volatile memory devices. Developed a model for
AFM/EFM experiments on nanocrystals.
Previous Research Projects
• PhD Thesis Project—High performance III-V pMOSFET
Prof Krishna Saraswat, Stanford University funded by Intel, USA and Stanford INMP Program
As scaling of Silicon CMOS is becoming increasingly difficult, use of alternate
materials with high carrier mobilities is being explored extensively. III-V
semiconductor’s have much higher electron mobility and recently n-channel devices
with very high electron mobilities and little velocity saturation have been
demonstrated. However the hole mobilities in III-V compounds have always lagged
as compared to Silicon. For successful integration of III-V materials in mainstream
CMOS it is preferable to develop III-V PMOSFETs with high mobilities. In the present
work we explored multiple approaches - Different Materials, Stoichiometry, Quantum
Wells and Strain to enhance the hole transport in III-V channel MOSFETs.
Effect of biaxial/uniaxial strain on the valence band structure and hole mobility for
Sb-based channel materials was studied experimentally. Surface / buried channel
III-V pMOSFETs with SS of 120mV/decade, ION /IOF F > 104 and having more than
50/100% mobility gain on Germanium over the entire sheet range have been
fabricated using a sub 350°C self-aligned process flow.
• Masters Thesis Project—Modelling of Nanocrystal Flash Memories
Prof Souvik Mahapatra, Prof Juzer Vasi, IIT-Bombay sponsored by Applied Materials, USA
Worked on the modelling of Nanocrystal Flash Memories, which are tipped to be the
successor of FG Flash memories - the present industry workhorse . We proposed and
developed a Capacitive Charging Model, a first comprehensive model to study the
program, erase and retention of these kind of memory cells taking into account the
inter-dot coupling between nanocrystals and using Monte Carlo distribution of dots. I
developed the complete framework and verified the simulator with experimental
results. We explored the effect of scaling, nanocrystal dot size and density, nanocrystal
material on the performance of these devices. I also worked on a problem to calculate
the current tunnelling between nanocrystals spherical in shape.
• Undergraduate Research Opportunity Program (UROP) —C-V Characterization of sub 100
nm channel length MOSFETS
Prof M.B. Patil, IIT-Bombay
The project involved making a new setup in the characterization lab with extensive
GPIB programming in C++ to interface characterization equipment with the HP GPIB
card. The project concluded with the development of a graphical interface for the
novice user along with testing and experimentation of sample programs on the same.
• ARMputer—An ARM Based Minicomputer
Prof Dinesh Sharma, IIT-Bombay for Tata Consultancy Services
Developed an ARM7 processor based minicomputer booting Linux. Features include
SD Card as Hard Drive, Serial, IrDA, Parallel and VGA ports with a full fledged Linux
2.6 OS, on a board sized 3" by 4". The kernel patches generated as a by-product of
porting Linux for this particular configuration have been contributed to Open Source.
• Electronic Design Project—VANI
Prof P.C. Pandey, Prof Dinesh Sharma, IIT-Bombay
We made a recordable speech output pad for people with speech disablity. The data
was sampled using a MSP430 family mixed singal microcontroller and stored on a SD
Flash Card over a FAT-16 like file system.
Selected Publications
• A. Nainani, S. Gupta, V. Moroz, M. Choi, Y. Kim, Y. Cho, J. Jelatos, T. Manderkar, A. Brand,
E.X. Ping, M. Abraham, K. Schuegraf, Is Strain Engineering Scalable in FinFET Era? :
Teaching the Old Dog Some New Tricks,IEEE 57th International Electron Device Meeting
(IEDM) 2012, pp. 427-430
• A. Nainani, T. Irisawa, Z. Yuan, Y.Sun, T. Krishnamohan, M. Reason, B.R. Bennett, J.B. Boos,
M. Ancona,Y. Nishi, K.C. Saraswat, Development of High-k Dielectric for Antimonides and
a Sub 350ºC III-V pMOSFET Outperforming Germanium, IEEE 57th International Electron
Device Meeting (IEDM) 2010, pp. 138-141
• A. Nainani, S. Raghunathan, D. Witte, M. Kobayashi, T. Irisawa, T. Krishnamohan, K.
Saraswat, B. R. Bennett, M. G. Ancona, J. B. Boos, Engineering of Strained III-V
Heterostructures for High Hole Mobility, IEEE 56th International Electron Device Meeting
(IEDM) 2009, pp. 857-860
• A. Nainani, S. Palit, P.K. Singh, U. Ganguly, J.Vasi, S. Mahaptra, Development of a 3D
Simulator for Metal Nanocrystal (NC) Flash Memories under NAND operation, IEEE 54th
International Electron Device Meeting (IEDM) 2007, pp. 947-950.
• A. Nainani, J. Yum , J. Barnett , R. Hill , N. Goel , J. Huang , P. Majhi , R. Jammy , K.C.
Saraswat, Study of piezoresistance under unixial stress for technologically relevant III-V
semiconductors using wafer bending experiments, Applied Physics Lettes, 96, 242110 (2010)
• Aneesh Nainani, Ze Yuan, Archana Kumar, J. Brad Boos, Brian R. Bennett and Krishna
Saraswat, III-Sb MOSFETs Opportunities and Challenges, invited talk at 221st ECS Meeting,
(2012).
• Aneesh Nainani, Yun Sun, Toshifumi Irisawa, Ze Yuan, Masaharu Kobayashi, Piero A.
Pianetta, Yoshio Nishi, Brian R. Bennett, J. B. Boos and Krishna Saraswat, Device quality
Sb-based compound semiconductor surface: A comparative study of chemical cleaning,
Journal of Applied Physics, vol. 109, 030110 (2011).
• Aneesh Nainani, Ze Yuan , Tejas Krishnamohan , Brian R. Bennett , J. Brad Boos , Matthew
Reason , Mario G. Ancona , Yoshio Nishi , Krishna C. Saraswat, InGaSb channel
p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure
design, Journal of Applied Physics, vol. 110, 014503 (2011).
• Aneesh Nainani, Toshifumi Irisawa , Ze Yuan , Brian R. Bennett , J. Brad Boos , Yoshio
Nishi , Krishna C. Saraswat, Optimization of the Al2 O3 GaSb Interface and a High-Mobility
GaSb pMOSFET, IEEE Transactions on Electron Devices, vol. 58(10), pp. 3407-3415 (2011).
• Aneesh Nainani, Toshifumi Irisawa, Brian R. Bennett, J. Brad Boos, Mario G. Ancona,
Krishna C. Saraswat, Study of Shubnikov-de Haas oscillations and measurement of hole
effective mass in compressively strained InX Ga1−X Sb quantum wells, Solid-State
Electronics, vol. 61(1), pp. 138-141, (2011).
• A. Nainani, Z. Yuan, T. Krishnamohan, K. Saraswat, Optimal Design of III-V
Heterostructure MOSFETs , IEEE Simulation of Semiconductor Processes and Devices (SISPAD)
2010, pp. 103-6
• A. Nainani, D. Kim, T. Krishnamohan, K. Saraswat, Hole Mobility and its enhancement
with Strain in Technologically relevant III-V’s , IEEE Simulation of Semiconductor Processes
and Devices (SISPAD) 2009, pp. 47-51
• A. Nainani, T. Irisawa, Y. Sun, F. Crnogorac, K. Saraswat, A sub 350°C GaSb pMOSFET
with ALD high-k dielectric, Solid State Device Metting (SSDM) 2010, pp. 133-4
• A. Nainani, M. Kobayashi, D. Witte, T. Irisawa, T. Krishnamohan, K. Saraswat, B. R.
Bennett, M. G. Ancona, J. B. Boos, Investigation of Strained Sb Channels with high Hole
Mobility, Solid State Device Metting (SSDM) 2009, pp. 254-255
• A. Nainani, C. Kothandaraman, N. Robson, SS. Iyer, Structural optimization of the
electrical programmable fuse (eFUSE) for the 45nm node, submitted to IEEE Transactions on
Electron Devices.
• A. Nainani, A. Roy, G. Mukhopadhyay, J. Vasi, Electrostatics and its effect on Spatial
Distribution of tunneling current in metal Nanocrytal memories, IEEE International
Conference on Memory Technology and Design 2007, pp. 161-164.
• Aneesh Nainani, Brian R. Bennett, J. Brad Boos, Mario G. Ancona, Krishna C. Saraswat,
Enhancing hole mobility in III-V semiconductors, Journal of Applied Physics, vol. 111, issue
10, pp. 103706, 2012.
• M. Agrawal, A. Nainani, M. Frei, Design and optimization of next generation high aspect
ratio periodic thin film photovoltaic cells, 37th IEEE Photovoltaic Specialists Conference,
Seattle, WA, Jun 2011.
• Z. Yuan, A. Nainani, Y. Sun, J.-Y. J. Lin, P. Pianetta, and K. C. Saraswat, Schottky barrier
height reduction for metal/n-GaSb contact by inserting TiO2 interfacial layer with low
tunneling resistance, Applied Physics Letters, vol. 98, 172106 (2011).
• Z. Yuan, A. Nainani, J.-Y. J. Lin, B. R. Bennett, J.B. Boos, M. G. Ancona and K. C. Saraswat,
Fermi-level pinning at metal/GaSb interface and demonstration of Inx Ga1−x Sb channel
Schottky pMOSFETs with metal S/D, Device Research Conference, pp. 143-144 (2011)
• Z. Yuan, A. Nainani, X. Guan, H.S.P Wong and K. C. Saraswat, Tight-binding Study of Γ-L
Bandstructure Engineering for Ballistic III-V nMOSFETs, IEEE Simulation of Semiconductor
Processes and Devices (SISPAD) 2011
• Se-Hoon Lee, Aneesh Nainani, Jungwoo Oh, Kanghoon Jeon, P.D. Kirsch, P. Majhi, L.F.
Register, S.K. Banerjee, R. Jammy, "on-State Performance Enhancement and
Channel-Direction-Dependent Performance of a Biaxial Compressive Strained Si0.5 Ge0.5
Quantum-Well pMOSFET Along <110> and <100> Channel Directions", IEEE Transactions
on Electron Devices, vol.58, no.4, pp.985-995 (2011)
• P.K. Singh, A. Nainani, Extensive NAND and NOR Reliability analysis of Tungsten dot NC
devices embedded in HfAlO high-k dielectric, IEEE 14th International Symposium on the
Physical and Failure Analysis of Integrated Circuits 2007, pp. 197-201.
• S. Lee, A. Nainani, J. Oh, P. Kirsch, S.K. Banerjee, R. Jammy, Hole Band Anisotropy Effect
on ON-State Performance of Biaxial Compressive Strained SiGe-based Short Channel QW
pMOSFETs: Experimental Observations, VLSI Technology, Systems and Applications 2010, pp.
126-7
• J. Hu, A. Nainani, Y Sun, K. C. Saraswat, H.S.P Wong, Impact of Fixed Charge on
Metal-Insulator-Semiconductor Barrier Height Reduction, Applied Physics Letters, vol. 99,
issue 25, 252104, 2011
• A Pal, A. Nainani, S. Gupta, and K. C. Saraswat, Performance Improvement of 1-Transistor
DRAM by Band Engineering, IEEE Electron Device Letters, v. 33(1), pp. 29-31.
• Ze Yuan, Aneesh Nainani, Brian R. Bennett, J. Brad Boos, Mario G. Ancona and K. C.
Saraswat, Amelioration of interface state response using band engineering in III-V
quantum well metal-oxide-semiconductor field-effect transistors , Applied Physics Letters,
vol. 100, issue 14, 143503, 2012
• Ze Yuan, Aneesh Nainani, Archana Kumar, Ximeng Guan, Brian R. Bennett, J. Brad Boos,
Mario G. Ancona, H.S. Philip Wong and K. C. Saraswat, InGaSb: single channel solution for
realizing all-III-V CMOS , 2012 Symposium on VLSI Technology and Circuits.
• Ze Yuan, Aneesh Nainani, Brian R. Bennett , J. Brad Boos , Mario G. Ancona , Krishna C.
Saraswat, Heterostructure Design and Demonstration of InGaSb Channel III-V CMOS
Transistors, International Semiconductor Device Research Symposium (ISDRS) 2011
• J.-Y. Jason Lin, Arunanshu M. Roy, Aneesh Nainani, Yun Sun, and Krishna C. Saraswat,
Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial
layer to reduce Schottky barrier height, Applied Physics Letters, 98, 092113 (2011).
• D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H. S-. P. Wong, K. C.
Saraswat, High Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms, IEEE
Transactions on Electron Devices, vol.58, no.1, pp.59-66, (2011)
• D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H. S-. P. Wong, K. C.
Saraswat, Experimental Demonstration of High Mobility Ge NMOS, IEEE 56th International
Electron Device Meeting (IEDM) 2009, pp. 454-457.
• S. Mittal, S. Gupta, A. Nainani, M. C. Abraham, K. Schuegraf, S. Lodha, and U. Ganguly,
Epitaxialy defined (ED) FinFET: to reduce Vt variability and enable multiple Vt, 70th
Annual Device Research Conference (DRC), pp.127-128, 2012.
• Sushant Mittal, Shashank Gupta, Aneesh Nainani, Mathew Abhraham, Klaus Schuegraf,
Saurabh Lodha, and U. Ganguly, Epi Defined ED FinFET: An alternate device architecture
for high mobility Ge channel integration in PMOSFET, IEEE International Nanoelectronics
Conference, 2013
• P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M.C. Abraham,
S. Kapadia, U. Ganguly, S. Lodha, ZnO: an attractive option for n-type metal-interfacial
layer-semiconductor (Si, Ge, SiC) contacts , 2012 Symposium on VLSI Technology and Circuits,
pp. 83 -84, 2012
• K. Chaudhuri, P. Bhatt, A. Nainani, M. Abraham, M. Subramaniam, S. Kapadia, K.
Schuegraf, U. Ganguly, and S. Lodha, Comparison of Plasma and Thermal Nitridation of
GeO2 Interfacial Layer for Ge CMOS , 43rd IEEE Semiconductor Interface Specialists
Conference, 2012
• Woo Shik Jung, Ju Hyung Nam, Jason Lin, Seunghwa Ryu, Aneesh Nainani, and Krishna
C. Saraswat, Enhancement of Phosphorus Dopant Activation and Diffusion of Suppression
by Fluorine Co-implant in Epitaxially grown in Germanium , International SiGe Technology
and Device Meeting, 2012
• W.-S. Jung, J.-H. Park, A. Nainani, D. Nam, and K. C. Saraswat, Fluorine passivation of
vacancy defects in bulk germanium for Ge metal-oxide-semiconductor field-effect
transistor application, Applied Physics Letters, vol. 101, no. 7, pp. 072104, 2012.
• S. Gupta, R. Chen, B. Magyari-Kope, H. Lin, A. Nainani, Y. Nishi, J. Harris, K.C. Saraswat,
GeSn Technology: Extending the Ge Electronics Roadmap, 2011 IEEE International Electron
Devices Meeting (IEDM), pp. 398-401, (2011).
• Prashanth Paramahans, Ravi Kesh Mishra, Pavan Kishore, Prasenjit Ray, Aneesh Nainani,
Yi-Chiau Huang, Mathew Abraham, Udayan Ganguly and Saurabh Lodha, Fermi-level
unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer,
Applied Physics Letters, Volume 101, Issue 18, 182105, (2012)
• S. Verma, G. Bersuker, D.C. Gilmer, A. Padovani, H. Park, A. Nainani, D. Heh, J. Huang, J.
Jiang, K. Parat, P.D. Kirsch, L. Larcher, H.-H. Tseng, K.C. Saraswat, R. Jammy, A Novel
Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2 HfSiO SiO2) TANOS with
excellent ProgramErase and Endurance to 105 cycles, IEEE International Memory Workshop
(IMW) 2009, pp. 1-2
• S. Verma, G. Bersuker, D. C. Gilmer, A. Padovani, H. Park, A. Nainani, J. Huang, K. Parat,
P. D. Kirsch, L. Larcher, HH. Tseng, K. C. Saraswat, R. Jammy, Understanding Endurance
Degradation Through Transconductance measurement for Flash Memory, 6th International
Symposium on Advanced Gate Stack Technology, 2009
• G. Thareja, J. Liang, S. Chopra, B. Adams, N. Patil, S. L. Cheng, A. Nainani, E. Tasyurek, Y.
Kim, S. Moffatt, R. Brennan, J. McVittie, T. Kamins, K. Saraswat, and Y. Nishi, High
performance germanium n-MOSFET with antimony dopant activation beyond
1x1020 cm−3 ", 2010 IEEE International Electron Devices Meeting (IEDM). pp. 245-248.
Miscellaneous
• General Secretary of the Electrical Engineering Student Assosication (EESA)
(Feb’05-March’06). I honed my skills as a leader and organized several events under my
guidance. In my tenure as General Secretary, I proactively organized a Student-Faculty
Panel Discussion and resurrected the Dept Library, ideas that were completely new to the
position.
• Participated in Standard Charted Mumbai Marathon 2006 & San Francisco Half Marathon
2010.