ADDITIONAL SOLVED PROBLEMS FOR TEXT
ELECTRONIC DEVICES AND CIRCUITS
Principles and Applications
by- N. P. Deshpande
Chapter 2: Semiconductor Physics
Additional Solved Problems
ASP 2.1: A Si crystal is doped with 5 x 1016 Arsenic atoms per cm3 initially. It is also
doped with 3.3 x 1016 atome/cm3 and then with 1018 atome/cm3 of Boron atoms.
Determine- 1) The type of resultant semiconductor 2) Concentration of majority carriers.
Solution: 1) Phosphorus is a pentavalent impurity. Hence it is of donor type. Each atom
of P will contribute an electron to semiconductor. Arsenic is also a pentavalent impurity.
Since already 5 x 1016 atoms/cm3 of Arsenic are present, total donor density is ND = 8.3 x
1016 atoms/cm3.
2) Additional doping by Boron atoms (acceptor type impurity) converts the Si from ntype to p-type since acceptor concentration is more that total donor concentration. Net
acceptor density is less tan number of Boron atoms added due to compensation. Hence
extrinsic Si is of p-type and density of holes (majority carriers isp = NA(B) – [ND(As) + ND(P)] = 1018 – [5 x 1016 + 3.3 x 1016]
= 9.17 x 1017 /cm3
ASP 2.2: Determine the Fermi probability f(E) for an electron at 300 0K having energy
level of 4kT above Ef.
Solution: The desired Fermi probability is given by relation1
f (E ) =
1+ e
⎛ E−Ef ⎞
⎜
⎟
⎝ kT ⎠
=
1
1+ e
⎛ 4 kT ⎞
⎟
⎜
⎝ kT ⎠
= 0.0179or1.79%
ASP 2.3: Find the rate of change of conductivity with respect to temperature for intrinsic
Ge at 300 0K.
Solution: Intrinsic concentration is given by relationni = B T3/2e-Eg/2kT
and conductivity is given by relation-
1
σ = n i q (µ n + µ p ) = BT 3 / 2 e
− E g / 2 kT
(µ
n
+ µp )
For intrinsic semiconductor, n = p = ni.
Differentiating expression for σ w.r.t. T and noting that B(µn + µp) is independent of
temperature, we getEg
dσ
3
=
+
dT 2T 2kT 2
Substituting Eg = Eg0 = 0.785 eV, T = 300 0K and k = 8.62 x 105 eV/0K, we getEg
dσ
3
3
0.785
=
+
=
+
= 0.0556 / 0 K
2
dT 2T 2kT
2 x 300 2 x8.62 x10 −5 x (300 )2
ASP 2.4: An intrinsic Si sample doped with 1018 atoms/cm3 of Arsenic is raised from 300
0
K to 340 0K. Find the change in difference between Ef and Ei.
Solution: Since Arsenic is pentavalent impurity. Extrinsic semiconductor will be of ntype. For n-type Si, n ≈ ND and
⎛n
E f − E i = kT ln⎜⎜
⎝ ni
⎞
⎟⎟
⎠
At 300 0K and kT = 0.02586 eV. Substituting these values in above expression, we get⎛n
E f − E i = kT ln⎜⎜
⎝ ni
⎞
⎛ 1018
⎟⎟ = 0.02586 ln⎜⎜
10
⎝ 1.5x10
⎠
⎞
⎟⎟ = 0.4658 eV
⎠
At 340 0K and kT = 0.02931 eV. Substituting these values in above expression, we get⎛n
E f − E i = kT ln⎜⎜
⎝ ni
⎞
⎛ 1018
⎟⎟ = 0.02931 ln⎜⎜
10
⎝ 1.5x10
⎠
⎞
⎟⎟ = 0.528 eV
⎠
Hence change in (Ef – Ei) from 300 0K to 340 0K is 0.528 – 0.4658 = 0.0622 eV
ASP 2.5: Addition of Arsenic atoms per Si atom to the extent of 10.4 x 107 results in a 10
Ω-cm resistivity extrinsic semiconductor at 300 0K. What must be the atomic density in
intrinsic Si?
Solution: Conductivity of extrinsic Si is-
2
1
−1
= 0.1 (Ω − cm )
ρn
The conductivity is also given byσn =
σ n = nqµ n
Hence we need to determine n (≈ND) first. µn = 1300 cm2/V-s form standard properties
table.
∴n ≈ ND =
σn
0 .1
=
= 4.8x1014 / cm 3
−19
qµ n 1.6 x10 x1300
Since ratio of Si atoms to As atoms is 10.4 x 107, ni = 4.8 x 1014 x 10.4 x 107 = 4.99 x
1022 /cm3.
ASP 2.6: When intrinsic Si at 300 0K is doped with acceptor impurity, its conductivity
becomes 1.5 (Ω-m)-1. Determine- 1) Hole concentration 2) Electron concentration 3)
Ratio of hole to electron concentration.
Solution: Since acceptor impurity is added, the resulting semiconductor will be of p-type.
Conductivity of p-type semiconductor is given by-
σp
1.5
= 1.875x10 20 / m 3
−19
qµ p 1.6 x10 x 0.05
Electron concentration can be determined from Mass action law. Hence-
σ p = pqµ p
∴p =
(
)
=
2
n2
1.5x1016
n= i =
= 1.2x1012 / m 3
p 1.875x10 20
The ratio of hole to electron concentration is=
1.875x10 20
= 1.56x10 8
1.2x1012
Chapter 2: Semiconductor Physics
Additional Exercise Problems
AE 2.1: Calculate the intrinsic carrier concentration of Si and Ge at 300 0K and 400 0K
taking into account the variation of Eg with temperature.
AE 2.2: If band gap energy for a sample of Si is found to be 1.0 eV, what must be the
temperature of the sample?
3
AE 2.3: Plot the graph of f(E) versus temperature for a semiconductor with E = 6.2 eV
and Ef = 5.9 eV for temperature range of 20 0C to 100 0C. Comment on results.
AE 2.4: If intrinsic Si at 300 0K is doped with 1016 atoms/cm3 of Boron atoms, what will
be the thermal equilibrium electron and hole concentration values? From the calculated
values of concentrations, deduce the type of extrinsic semiconductor.
AE 2.5: Find resistivity of intrinsic Ge at 300 0K. If acceptor impurity to the extent of 1
atom per 107 atoms of Ge is added, what will be the change in resistivity?
AE 2.6: Interconnections inside the integrated circuits are made using Copper or
Aluminum. If a strip conductor has length of 2.00 mm, cross sectional area of 3 x10-12 m2
and the resistance of 10Ω, what must be the electron concentration? Assume mobility of
electrons to be 2000 cm2/V-s.
AE 2.7: Find density of donor atoms if resistivity of intrinsic Si is found to be 8 Ω-cm.
What is the ratio of majority to minority carrier concentrations in extrinsic Si?
AE 2.8: For a p-type Si bar used in Hall effect experiment, d = W = 3 mm. The current
through bar is 40 µA and Hall voltage is 200 mV. If magnitude of flux density used is
0.12 Wb/m2, find the resistivity of bar. Assume mobility of holes to be 500 cm2/V-s.
AE 2.9: A n-type Si sample is doped with donor impurity of 1015 atoms /cm3. If length of
Si sample is 2.00 mm and cross sectional area is 5 x 10-9 m2, determine- 1) Voltage
needed across the bar to produce a current of 1.2 µA 2) Conductivity of the bar.
AE 2.10: An external voltage of 12V is applied to intrinsic Si cube with all dimensions to
be 10 mm. If ni = 1.5 x 1010 electrons/cm3, determine- 1) Drift velocity of charge carriers
2) Drift current density due to electrons 3) Drift current density due to holes 4) Total drift
current density 5) Total current in the bar.
AE 2.11: A bar of intrinsic Si has cross sectional area of 4.2 x 10-4 m2. If electron density
is 1.2 x 1016 /m3, what should be the length of bar so that a current of 1.2 mA results in it
when 10V are applied across the bar? Assume µn = 0.13 m2/V-s, µp = 0.05 m2/V-s.
4
Chapter 3: Diodes and Their Applications
Additional Solved Problems
ASP 3.1: If the barrier potential for certain Si diode at room is 0.6V and the
concentration of donor atoms is 1021 /m3, determine the concentration of acceptor atoms.
Solution: At room temperature VT = 0.02586V. VO = 0.6V, ni for Si = 1.5 x 1010 /m3 and
ND = 1021 /m3. Substituting these values in the expression for barrier potential, we get⎛N N
kT ⎛ N A N D ⎞
⎟ = VT ln⎜ A 2 D
ln⎜⎜
2
⎟
⎜ n
q ⎝ ni ⎠
i
⎝
⎡ N x10 21 ⎤
∴ 0.6 = 0.02586 ln ⎢ A
2 ⎥
⎢⎣ 1.5x1010 ⎥⎦
V0 =
(
⎞
⎟
⎟
⎠
)
Solving for NA, we get- NA = 2.618 x 1021 atoms/m3.
ASP 3.2: A Si p-n junction diode has reverse saturation current of 10-14A at room
temperature. Calculate the current through the forward biased diode at 67 0C if a forward
voltage of 0.7V is applied across the diode. Assume η = 1.
Solution: Both VT and IS change with temperature. At room temperature i.e. T1 = 300 0K,
IS1 = 10-14A, VT1 = 0.02586 V. At 67 0C, T2 = 273 + 67 = 340 0K.
T2
340
VT 2 =
=
= 0.02931 V
11600 11600
Reverse saturation current at T2 is given by-
I S 2 = I S1 x 2 (T 2−T1) / 10 = 10 −14 x 2 ( 340−300 ) / 10 = 16x10 −14 A
Current through diode is given byV / ηVT 2
I 2 = I S2 e
− 1 = 16 x10 −14 x (e 0.7 / 0.02931 − 1) = 3.768 mA
(
)
ASP 3.3: An ideal Si diode has reverse saturation current of 1 nA at room temperature
(300 0K). Find the dynamic resistance of diode for a forward bias of 1) 0.5 V 2) 0.6V and
3) 0.7V. Assume η = 2. Comment on results.
Solution: Dynamic resistance of diode is given by expression-
r=
ηVT
V
ηVT
ISe
VT = 0.02586 V at 300 0K. Hence ηVT = 0.05172 V.
5
1) Dynamic resistance for a forward bias of 0.5V isr=
ηVT
ISe
V
ηVT
=
0.05172
= 3.274k
10 − 9xe 0.5 / 0.05172
2) Dynamic resistance for a forward bias of 0.6V isr=
ηVT
ISe
V
ηVT
=
0.05172
= 473.6Ω
10 − 9 xe 0.6 / 0.05172
3) Dynamic resistance for a forward bias of 0.7V isr=
ηVT
V
ηVT
=
0.05172
= 68.5Ω
10 − 9 xe 0.7 / 0.05172
ISe
Comment: As the diode is forward biased beyond cut-in voltage, the dynamic resistance
drops at a rapid rate. This signifies the exponential nature of V-I characteristic of diode.
ASP 3.4: Determine the state of each diode for the circuit shown below for 1) R = 1k 2)
R = 10k. Diode D1 is Si diode with Rf = 20Ω and Vγ = 0.6V. Diode D2 is Ge diode with
Rf = 10Ω and Vγ = 0.2V.
R
D1
V = 20V
D2
Solution: Initially we assume that both diodes are ON. We then replace the diodes with
their equivalent circuits. The resultant circuit that we can use for analysis is shown
belowR
A
V = 20V
Vγ2
Rf1
Rf2
I1
I2
D1
K
1)
A
Vγ1
D2
K
For R = 1k, the KVL expression for loop containing D1 is-
-V + (I1 + I2)R + Rf1I1 + Vγ1 = 0
6
Similarly, KVL expression for loop containing D2 is-V + (I1 + I2)R + Rf2I2 + Vγ2 = 0
Substituting the values of resistors in k and current in mA, we get-20 + (I1 + I2) x 1 + 0.02I1 + 0.6 = 0
-20 + (I1 + I2) x 1 + 0.01I1 + 0.2 = 0
(1)
(2)
Subtracting (2) from (1), and rearranging terms, we getI2 = I1 + 40
Substituting in (1) and solving for I1, we get I1 = -10.19 mA.
Since I1 is negative, diode D1 must be OFF. Hence practically, I1 = 0. Substituting I1 = 0
in (2), we get I2 = 19.6 mA. Hence we conclude that D1 is OFF and D2 is ON.
For R = 10k, and assuming that both D1 and D2 are ON as before, the KVL
2)
expression for loop containing D1 is-V + (I1 + I2)R + Rf1I1 + Vγ1 = 0
Similarly, KVL expression for loop containing D2 is-V + (I1 + I2)R + Rf2I2 + Vγ2 = 0
Substituting the values of resistors in k and current in mA, we get-20 + (I1 + I2) x 10 + 0.02I1 + 0.6 = 0
-20 + (I1 + I2) x 10 + 0.01I2 + 0.2 = 0
(3)
(4)
Subtracting (4) from (3), and rearranging terms, we getI2 = I1 + 40
Substituting in (3) and solving for I1, we get I1 = -19 mA.
Since I1 is negative, diode D1 must be OFF. Hence practically, I1 = 0. Substituting I1 = 0
in (4), we get I2 = 1.978 mA. Hence we conclude that D1 is OFF and D2 is ON.
ASP 3.5: Determine the slope of transfer characteristic for parallel clipper circuit shown
in Figure below when the diode is ON. Forward resistance of diode is 10Ω. Comment on
result.
R
Vi
D
7
V0
Solution: When the diode is ON, it can be replaced by its DC equivalent circuit. The
resultant circuit is shown belowR
A
Vγ
Vi
Vo
Rf
K
Slope of transfer characteristic of this circuit is given by relation (3.26) which isSlope =
VO
Rf
10
=
=
= 9.9 x10 −3
Vi
R f + R 10 + 1000
Comment: The expression for slope indicates that it is desirable to have Rf << R for
better clipping. Since Rf is the characteristic of diode, we need to choose R >> Rf in any
practical diode clipping circuit.
ASP 3.6: Write expressions for VO for following clipping circuits when the diode is ON.
Assume that the forward resistance of diode is Rf and cut-in voltage Vγ.
R
R
D
Vi
V0
D
Vi
V
(a)
(b)
R
D
Vi
V
(c)
8
V0
V0
Solution: a) Let us assume that when diode is ON, current through R, D and V path is I.
When the diode is ON, we can replace it with its DC equivalent circuit. This is shown
belowR
A
Vγ
Vi
I
Vo
Rf
K
The KVL expression for path containing Vi, R and D is-Vi + IR + IRf + Vγ = 0
As seen from the figure, VO = IRf + Vγ.
b) The clipper circuit shown in Figure b) is a parallel bised clipper. The equivalent circuit
after replacing didoe with its DC equivalent circuit is shown below-
R
A
Vγ
I
Rf
Vo
Vi
K
V
The KVL expression for closed loop containing Vi, R and D is-Vi + IR + Vγ + IRf + V = 0
As seen from figure the output voltage is VO = IRf + Vγ + V.
c) The clipper circuit shown in Figure c) is a parallel bised clipper. It can be noted that
polarity of V is reversed.The equivalent circuit after replacing didoe with its DC
equivalent circuit is shown below-
9
R
A
Vγ
I
Rf
Vo
Vi
K
V
The KVL expression for closed loop containing Vi, R and D is-Vi + IR + Vγ + IRf - V = 0
As seen from figure the output voltage is VO = IRf + Vγ - V.
ASP 3.7: For HWR circuit shown in Figure below, determine peak and average i.e. Dc
output voltage. Assume drop across conducting diode to be 0.9V.
12:1
VD
+ VO
RL
230V, 50 Hz
AC
(External Load)
-
T1
Solution: Secondary voltage is determined by step-down ratio of transformer. Peak
primary voltage is given by-
Vm ( pri ) = 230x 2 = 325.27V
Using stpe-down ratio, peak value of seconadry voltage is given byVm (sec) =
Vm ( pri )
n
=
325.27
= 27.1V
12
Peak load voltage VL(p)= Vm(sec) – VD = 27.1 – 0.9 = 26.2 V
Average value of output voltage is given by-
10
Vdc =
Vm ( p )
π
= 8.34V
ASP 3.8: Determine the TUF for HWR circuit where secondary resistance is 2 Ω,
forward resisatnce of conducting diode is 3 Ω and equivalent load resistance is 100 Ω.
Comment on result.
Solution: TUF for HWR is given by expression (3.56)2 2
x
π2
1
=
2 2
x
π2
1
= 0.2729
RS + Rf
5
1+
1+
100
RL
Comment: This example satsfies the desirable condition for better TUF viz. (RS + Rf) <<
RL.Henc eTUF is very close to theoretical maximum value of 0.287.
TUF =
ASP 3.9: For the FWR circuit, determine- Vdc, Idc, Pdc, Irms and rectifier efficiency.
Assume drop across conducting diode to be 0. Rf = 5 Ω W, resistance of each half of
secondary- RS = 5 Ω and equivalent load resistance is 100 Ω. Step-down ratio of power
transformr is 12:1.
Solution: Secondary voltage is determined by step-down ratio of transformer. Peak
primary voltage is given by-
Vm ( pri ) = 230x 2 = 325.27V
Using stpe-down ratio, peak value of seconadry voltage is given byVm (sec) =
Vm ( pri )
n
=
325.27
= 27.1V
12
DC output voltage is given byVdc =
2Vm (sec)
π
=
2 x 27.1
= 17.25V
π
Peak secondary current is given byUsing stpe-down ratio, peak value of seconadry voltage is given byVm (sec)
27.1
= 0.271A
RL
100
DC load current is given byIm =
=
11
I dc =
2I m 2 x 0.271
=
= 0.1725A
π
π
RMS load current is given by-
I rms =
Im
2
=
0.1725
2
= 0.181A
DC power delivered to load is given by2
Vm2 R L
4 (27.1) × 100
4
=
×
= 2.46 W
Pdc = 2 ×
π
(R S + R f + R L )2 π 2 (5 + 5 + 100)2
Rectifier efficiency =
RL
8
8
100
×
= 2×
= 0.736or 73.6%
2
(R S + R f + R L ) π (5 + 5 + 100)
π
12
Chapter 3: Diodes and Their Applications
Additional Exercise Problems
AE 3.1: A Si p-n junction diode is doped with acceptor impurity of 2.5 x 1021 atoms/cm3
and a donor impurity of 1021 atoms/cm3. Calculate the barrier potential at a) Room
temperature b) 700C.
AE 3.2: A Si p-n junction diode has a reverse saturation current of 10-14A and is forward
biased to 0.7V. Assuming η = 1, plot the graph of forward voltage versus temperature for
temperature changing from 100C to 1000C. Comment on results.
AE 3.3: For the clipping circuits shown below, write closed loop KVL expression when
the diode is ON. Replace each diode with a series combination of Rf and Vγ.
R
Vi
R
D
V0
Vi
D
Vi
V0
D
D
R
V0
Vi
R
R
V0
R
D
Vi
D
V0
Vi
V
V0
V
AE 3.4: For a Ge diode operating at room temperature, η = 1. If VD is found to be 0.2V
for a forward current of 8 mA, a) what will be the forward current for VD = 0.25 V? b)
What must be the value of reverse saturation current?
AE 3.5: For the circuit shown below, sketch the transfer characteristic assuming ideal
diode. Input voltage range is +24 V.
13
R1
R3
10Ω
10Ω
D1
Vi
R2
10Ω
D2
V0
V1
5V
AE 3.6: Output voltage of a FWR circuit is 24V and load draws a current of 100 mA. If
resistance of each half of secondary winding of power transformer is 4 Ω, forward
resistance of conducting diode is also 4 Ω, determine- 1) DC power output 2) Rectifier
efficiency 3) PIV rating of diodes.
AE 3.7: For the regulator circuit shown below, if VZ = 12 V, ZZ = 5 Ω, IZK = 1 mA and
IZmax = 40 mA, what will be the maximum variation in output voltage. Input voltage is
constant and equal to +18 V.
R
100 Ω
Vi=18V
Z
12V
Vo
AE 3.8: For the zener voltage regulator shown below, determine- 1) Output voltage 2)
Load current 3) Voltage drop across R 4) Current through zener 5) Power dissipated by
zener.
R
2k2
Vi = 48V
Z
14
27V
Vo
Chapter 4: Field Effect Transistors and Applications
Additional Solved Problems
ASP 4.1: The circuit shown below uses JFET 2N 5459 with VGS(OFF) = -8.0 V and IDSS =
9 mA. Determine the minimum value of VDD that will put the device in saturation.
D
RD
470Ω
2N5459
G
+
-
S
VDD
Solution: For JFET in saturation, the minimum value of VDS = VP = |VGS(OFF)| = 8V.
For given circuit, VGS = 0. By definition, ID = IDSS for VGS = 0.
The KVL expression for loop containing VDD, RD and JFET is-
-VDD + IDRD + VDS = 0
Hence VDD = IDRD + VDS = (9)(0.47) + 8 = 12.23 V
ASP 4.2: Data sheet for JFET 2N5459 indicates IDSS = 9 mA. If VGS(OFF) = -8V, what will
be the drain current for- 1) VGS = -1 V 2) VGS = -2 V 3) VGS = -3 V 4) VGS = -4 V.
Solution: The drain current for different values of VGS is determined by Schockley’s
equation2
⎛ V ⎞
I D = I DSS ⎜⎜1 − GS ⎟⎟ where VP = |VGS(OFF)| = 8V
VP ⎠
⎝
2
2
2
2
2
2
2
2
⎛ V ⎞
⎛ 1⎞
1) For VGS = -1 V, I D = I DSS ⎜⎜1 − GS ⎟⎟ = 9⎜1 − ⎟ = 6.89mA
VP ⎠
⎝ 8⎠
⎝
⎛ V ⎞
⎛ 2⎞
2) For VGS = -2 V, I D = I DSS ⎜⎜1 − GS ⎟⎟ = 9⎜1 − ⎟ = 5.06mA
VP ⎠
⎝ 8⎠
⎝
⎛ V ⎞
⎛ 3⎞
3) For VGS = -3 V, I D = I DSS ⎜⎜1 − GS ⎟⎟ = 9⎜1 − ⎟ = 3.51mA
VP ⎠
⎝ 8⎠
⎝
⎛ V ⎞
⎛ 4⎞
4) For VGS = -4 V, I D = I DSS ⎜⎜1 − GS ⎟⎟ = 9⎜1 − ⎟ = 2.25mA
VP ⎠
⎝ 8⎠
⎝
15
ASP 4.3: Data sheet for JFET 2N5458 indicates IDSS = 6 mA, VGS(OFF) = -7.0 V. If yfs(max)
= 5500 µS, what will be the forward transconductance at VGS = -3.5V? Also determine
the value of drain current for this value of VGS.
Solution: yfs(max) is nothing but gm0 for JFET. In order to determine transconductance for
JFET at VGS = -3.5V we use the relation (and noting that - VP = |VGS(OFF)| = 7V
⎛ V ⎞
⎛ 3 .5 ⎞
g m = g mo ⎜⎜1 − GS ⎟⎟ = (5500 )⎜1 −
⎟ = 2750µS or 2750µA / V
7 ⎠
VP ⎠
⎝
⎝
The drain current for given value of VGS is obtained using Schockley’s equation2
2
⎛ V ⎞
⎛ 3.5 ⎞
I D = I DSS ⎜⎜1 − GS ⎟⎟ = 6.0⎜1 −
⎟ = 1.5mA
VP ⎠
7 ⎠
⎝
⎝
ASP 4.4: A certain JFET is required to be biased at mid-point. If IDSS for JFET is 9 mA
VGS = -2 V and VDD = 18V, what will be the values of RS and RD for self bias
arrangement?
Solution: For JFET biased at mid-point, VP = |VGS(OFF)| = VGS x 3.4 = -6.8V. The drain
current is half of IDSS i.e. 9/2 = 4.5 mA and VDS = VDD/2 = 9V. Resistance in series with
Source terminal is given byRS =
VGS
2V
=
= 444Ω
ID
4.5mA
Using KVL expression for output loop, and rearranging the terms, we can writeRD =
VDD − VDS
18 − 9
− RS =
− 0.444 = 1.556k
4 .5
ID
ASP 4.5: A JFET CS amplifier shown in figure below uses JFET 2N5459. If gm = 4
mA/V and rd = 100 k, what will be the voltage gain and output resistance of the
amplifier? Assume all capacitors to be arbitrarily large.
16
+VDD
RD
10k
CC2
Vi
-
+
CC1
-
+
RG
1M
VO
RS
220Ω
+
CS
-
Solution: Voltage gain for CS amplifier is given by relation-
AV = -gmReq
Where Req = rd || RD = 10k || 100k = 9.09k
Hence AV = -4 mA/V x 9.09k = -36.36
The output resistance is given by RO = rd || RD = 10k || 100k = 9.09k
ASP 4.6: What is the voltage gain and input resistance of JFET amplifier shown in figure
below? IGSS for JFET is 5 nA at VGS = -10V and transconductance of JFET is 1.2 mA/V.
VDD = +12V
CC1
Vi
-
+
CC2
+
RG
2.2M
RS
CS
10k
17
VO RL
10M
Solution: This is a Common Drain (CD) amplifier. The expression for voltage gain is-
g m R eq
AV =
where Req = RS || RL. In the present case, RL >> RS. Hence Req ≈
1 + g m R eq
RS. The voltage gain is-
AV =
g m R eq
1 + g m R eq
=
gmRS
1.2x10
=
= 0.923
1 + g m R S 1 + 1.2x10
Input resistance for device is given byR i' =
VGS 10V
=
= 2000M
I GSS 5nA
This input resistance of the device is shunted by external biasing resistor RG. Hence
amplifier input resistance isRi = R i' || R G ≈ R G = 2.2M
ASP 4.7: Data sheet for certain EMOSFET gives ID(on) = 200 mA, VGS(th) = 1.2 V. 1) If K
= 6.0 mA/V2, what must be the value of VGS? 2) Determine the value of ID for VGS = 4 V.
Solution:
1) K =
[V
GS
I D ( on )
− VGS( th )
]
2
[
hence VGS − VGS( th )
]
2
=
I D ( on )
K
=
200
= 33.33
6
∴ VGS − VGS( th ) = 5.77V
∴ VGS = 5.77V + VGS( th ) = 5.77 + 1.2 = 6.97V
2) Required value of Drain current is given byID = K[VGS-VGS(th)]2 = 6.0[4-1.2]2 = 47.04 mA
ASP 4.8: For EMOSFET biasing circuit shown in figure below, the device used has
VGS(th) = 1.2 V and ID(on) = 200 mA at VGS = 5 V. Determine the values of VGS, K, ID and
RD if VDS = 6V.
18
VDD = +24V
RD
R1
120k
D
G
S
R2
22k
Solution: The biasing arrangement shown uses a potential divider circuit. Since Source is
at ground potential, VGS is given byVGS =
K=
R2
22
xVDD =
x 24 = 3.71V
R1 + R 2
120 + 22
I D ( on )
[VGS − VGS( th ) ]
2
=
200
= 13.85mA / V 2
2
(5 − 1.2)
The drain current is given by relationID = K[VGS-VGS(th)]2 = 13.85 x [3.71-1.2]2 =87.25 mA
If we write a KVL expression for drain loop, and rearrange terms, external drain
resistance is given by relationRD =
VDD − VDS
24 − 6
=
= 206Ω
ID
87.25mA
19
Chapter 4: Field Effect Transistors and Applications
Additional Exercise Problems
AE 4.1: For certain JFET, VGS(OFF) = -8V and IDSS = 9 mA. Determine the values of ID for
VGS varying from 0 to –8V in steps of 1V and plot the transfer characteristic.
AE 4.2: A JFET used in self bias circuit has VGS(OFF) = -10V and IDSS = 12mA.
Determine the values of RD and RS for mid-point bias. The circuit uses VDD = +24V. Find
quiescent values of ID, VGS and VDS.
AE 4.3: For the circuit shown below, determine quiescent values of ID, VGS and VDS. The
JFET used has VGS(OFF) = 7V and IDSS = 8mA.
VDD = -12V
RD
1.2k
p-channel
JFET
RS
RG
470Ω
10M
AE 4.4: For the CS amplifier shown in figure below, what will be the output voltage if
20mV, 10 kHz AC input is applied to the amplifier. The JFET used has gm = 3.8mA/V.
+VDD
RD
1.2k
CC2
+
CC1
Vi
-
-
100µF
+
47µF
RG
10M
VO
RS
390Ω
+
CS
-
1000µF
20
RL
100k
AE 4.5: For the CG amplifier shown in figure below, the JFET used has gm = 3.8 mA/V.
Determine- 1) Voltage gain 2) Input resistance 3) Output resistance. Assume all
capacitors to be arbitrarily large.
VDD = +9V
RD
10k
CC1
Vi
-
CC2
+
+
RS
-
VO
1.8k
AE 4.6: For the MOSFET circuit shown in figure below, the device used has ID(on) = 3.2
mA at VGS = 4V and VGS(th) = 1.8V. Determine- 1) VGS and 2) VDS.
VDD = +12V
RD
R1
1k2
10M
D
G
S
R2
4.7M
21
AE 4.7: Data sheet of certain MOSFET indicates ID(on) = 8mA at VGS = -10V. If VGS(th) =
-2.8V. Determine ID for VGS = -4V.
AE 4.8: Draw the output voltage waveform for CS amplifier shown below. The
MOSFET used has gm = 4.5 mA/V and IDSS = 12mA. Assume all capacitors to be
arbitrarily large.
VDD = +24V
RD
1k2
CC2
VO
D
CC1
Vi
10mV
RMS
G
S
10M
RG
AE 4.9: For the circuit shown below, the MOSFET used has following parameters- ID(on)
= 16 mA at VGS = 8V, VGS(th) = 2.2V and gm = 3 mA/V. Determine VGS, ID and VDS.
VDD=+20V
R1
22k
RD
1k
CC2
+
-
CC1
Vi
-
+
VO
R2
8k2
22
RL
20k
Chapter 5: Bipolar junction Transistors and Applications
Additional Solved Problems
ASP 5.1: Calculate the values of IC and VCE for the circuit shown below. The transistor
used has β = 100. Assume VBE(active) = 0.7V.
VCC = +12V
RC
2k2
RB
100k
VBB
2V
Solution: Writing KVL expression for input loop gives us the value of base current. The
closed loop KVL expression for input loop is-
-VBB + IBRB + VBE(active) = 0
Rearranging terms, we getVBB − VBE ( active)
2 − 0.7
= 13µA
RB
100k
Assuming that the transistor is in active region, IC = βIB = 100 x 13 x10-6 = 1.3 mA.
To determine VCE, we write KVL expression for output loop. This givesIB =
=
-VCC + ICRC + VCE = 0
∴ VCE = VCC − I C R C = 12 − (1.3)(2.2) = 9.14V
Since VCB is positive (for npn transistor) and VCE is more than VCE(sat), transistor is indeed
in active region. This justifies our initial assumption. (VCB = VC – VB = 9.17 –0.7 =
8.44V).
ASP 5.2: For the circuit shown below, the transistor used has β = 100. Determine the
region of operation of transistor. Assume VBE(active) = 0.7V and VBE(sat) = 0.8V.
23
VCC = +24V
RC
4k7
RE
1k
RB
100k
VBB
3V
Solution: Initially we assume that transistor is in active region. KVL expression for input
loop is-
-VBB + IBRB + VBE(active) + IERE = 0
For the transistor in active region, IE = (1+β)IB. Substituting this in above KVL
expression, and rearranging terms, we getIB =
VBB − VBE ( active)
R B + (1 + β)R E
=
3 − 0.7
= 21µA
(100 + 101)10 3
For transistor assumed to be working in active region, IC = βIB = 100 x 21 x 10-6 =
2.1mA.
We can now determine VCE (hence VCB) to confirm our assumption that transistor is
indeed working in active region. KVL expression for output loop is-VCC + ICRC + VCE +IERE = 0
Hence VCE = VCC – ICRC –IERE = 24 - (2.1)(4.7) – (2.12)(1) = 12.01V
In order to determine VCB, we calculate VB and VC.
24
VB = VBE(active) + IERE = 0.7 + 2.12 = 2.82V
Similarly, VC = VCC-ICRC = 24 – (2.1)(4.7) = 17.2V
By definition, VCB = VC – VB = 17.2 – 2.82 = 14.38V
Since VCB is positive for npn transistor, the device is indeed in active region.
ASP 5.3: For CE amplifier shown in figure below, determine- 1) A I =
IO
2) AV 3) AVS
Ii
4) Ri 5) RO. The BJT used has following h-parameters
hie = 1k
hre = 2 x 10-4
hfe = 80
hoe = 20 µA/V
Assume all capacitors to be arbitrarily large.
+ VCC
RC
R1
100k
3k9
IO
CC2
VO
CC1
rs
Ii
1k
VS
+
CE
-
RE
1k
R2
10k
AC
Solution: The AC equivalent circuit for amplifier after replacing BJT with its hparameter model is shown belowrs
A
Ii
VS
R1
100k
B
hie
C
Ib
R2
10k
IO
hfe Ib hoe
hrevce
E
25
RC
3k9
VO
In this case, 1/hoe = 50k. This is much larger than RC i.e. 3k9. HenceA 'I =
IO
− h fe
− 80
=
=
= −74.2
I B 1 + h oe R C 1 + (20 x10 −6 )(3.9 x10 3 )
R i' = h ie + h re A 'I R C = 1x10 3 + (2x10 −4 )(−74.2)(3.9x10 3 ) = 942.12Ω
RB=R1||R2 = 100k||10k = 9.1k
AI =
IO IO Ib
=
x
Ii
I b Ii
Ib
is found out using Norton’s current division rule.
Ii
AI =
IO Ib
RB
9.1
= (− 74.2 )
= −67.24
× = A ′I ×
(9.1 + 0.942)
Ib Ii
R B + R ′i
Input resistance is given byR i = R i' || R B = (0.942k )(9.1k ) = 853Ω
Voltage gain A V =
A I R C (−67.24)(3.9)
=
= −307.42
Ri
0.853
Voltage gain taking into account rS–
A VS =
AVRi
(− 307.42)(0.853) = −141.52
=
R i + rS
0.853 + 1
Output admittance for transistorYO′ = h oe −
h fe h re
h ie + R ′S
where RS' is effective source resistance seen by the transistor.
R ′S = rS || R B =1 k || 9.1 k = 0.9 k
26
h fe h re
(
80)(2 × 10 −4 )
−6
∴ YO = h oe −
= 20 × 10 −
= 11.57 µA /V
h ie + R ′S
(1 + 0.9)10 3
'
∴ R ′O =
1
= 86.43 k
YO'
Effective output resistance will beR O = R ′O || R C = (86.43 k ) || (3.9 k ) = 3.73 k
ASP 5.4: For the amplifier shown below, calculate- 1) A I =
AV =
IO
2) R i' 3) Ri 4)
Ii
VO
V
5) A VS = O 6) R 'O 7) RO. The BJT used has following h-parameters
Vi
VS
hie = 1k
hre = 2.5 x 10-4
hfe = 60
hoe = 25 µA/V
Assume all capacitors to be arbitrarily large.
+ VCC
R1
100k
RC
3k9
IO
rs
1k
VS
CC2
VO
CC1
Ii
Vi
RL
R2
10k
RE
330Ω
CE
Solution:
To see whether approximate analysis is valid or not, we first calculate RL'
R 'L =
1
|| R C || R L = 40k || 3k9 || 4k 7 = 2.02k
hoe
h oe R 'L = 25 × 10 −6 × 2.02 × 10 3 = 0.05
27
4k7
Since h oe R 'L ≤ 0.1, we can use approximate analysis.
Figure below shows AC equivalent with BJT replaced by CE h-parameters. We have
omitted hrevce and hoe from the equivalent circuit, consistent with approximate analysis.
rs
C
Ib
1k
Ii
VS
hie
B
Vi
R2
100k
hfe Ib
R1
RC
10k
E
3k9
IC
IO
VO
RL
4k7
RO
Ri
AC equivalent for amplifier with BJT replaced by CE h-parameters
Current gain for device A 'I = − h fe = −60
Input resistance for device R i' = h ie = 1k
Input resistance for amplifier R i = R i' || R B = R i' || R 1 || R 2 = 1k || 100k || 10k = 0.9k
Current gain for amplifier is given by relation-
AI =
IO IO IC Ib ⎛ − R C
=
× × =⎜
Ii
I C I b I i ⎜⎝ R C + R L
⎞
⎛ RB
⎟⎟(h fe )⎜⎜
⎠
⎝ R B + h ie
⎞ ⎛ − 3 .9 ⎞
⎛ 9 .1 ⎞
⎟⎟ = ⎜
⎟(60 )⎜
⎟ = −24.49
⎝ 9 .1 + 1 ⎠
⎠ ⎝ 3 .9 + 4 .7 ⎠
Different ratios were found out using Norton’s current division rule.
Voltage gain for amplifierVO − h fe R 'L (−60)(2.02)
=
=
= −134.66
Vi
Ri
0.9
Voltage gain taking into account source resistanceAV =
A VS =
AVRi
(−134.66)(0.9)
= −63.79
=
R i + rS
0 .9 + 1
R 'O = ∞, for device (Approximate model).
28
R O = R 'L = R L || R C = 4k 7 || 3k9 = 2.13k
ASP 5.5: For the circuit shown in figure below, determine- 1) AI 2) Ri 3) AV and 4) RO.
The BJT used has following h-parametershie = 1k
hre = 2.5x10-4
hfe = 80
hoe = 25µA/V
Neglect the effect of biasing network. Assume all capacitors to be arbitrarily large.
+ VCC
R1
rs
CC1
CC2
VO
1k
VS
RE
R2
2k2
Solution: This is a Common Collector amplifier. Since h-parameters for CE are
specified, we use conversion formulae from Table 5.6.
hic = hie
hoc = hoe = 25 x 10-6
hfc = -(1+hfe) = -81
hrc = 1
Since hocRE < 0.1, we can use approximate analysis.
Current gain AI = 1+hfe = 1+80 =81
Input resistance, neglecting the effect of biasing network isRi = hie + (1+hfe)RE = 1.0 + (1+80)(2.2) = 178.2k
h ie
1
= 1−
= 0.994
178.2
Ri
r + h ie 1000 + 1000
= 24.69Ω
Output resistance R O = S
=
1 + h fe
1 + 80
Voltage gain A V = 1 −
29
ASP 5.6: A Common Base amplifier is driven by a voltage source having output
impedance of 50Ω. (Recall that CB amplifier’s input resistance is low). If load resistance
for amplifier is 10k and BJT used has following h-parameters-
hib = 27Ω
hrb = 2.5 x 10-4 hfb = -0.98
hob = 0.5µA/V
Determine- 1) AI 2) Ri 3) AV 4) AVS 5) AIS 6) RO. Neglect the effect of biasing
network.
Solution: Current gain A I =
− h fb
− (−0.98)
=
= 0.975
1 + h ob R L 1 + (0.5x10 −6 x10 x10 3 )
Input resistance Ri = hib + hrbAIRL = 27 + (2.5x10-4)(0.975)(10x103) = 29.43Ω
A I R L 0.975x10000
=
= 331.3
Ri
29.43
Voltage gain taking into account source resistance-
Voltage gain A V =
A VS =
AVRi
(331.3)(29.43)
=
= 122.75
R i + rS
29.43 + 50
Current gain taking into account source resistance
A IS =
A I rS
(0.975)(50)
=
= 0.613
R i + rS
29.43 + 50
Output admittance YO = h ob −
Output resistance R O =
h fb h rb
(−0.98)(2.5x10 −4 )
= 0.5x10 −6 −
= 3.68x10 −6 mho
h ib + rS
27 + 50
1
1
=
= 271.6k
YO 3.68x10 −6
ASP 5.7: For Emitter Follower stage shown below, the BJT used has following hparametershie = 1.1k
hfe = 100
Calculate the value of input resistance 1) Neglecting the effect of biasing network 2)
Taking into account the effect of biasing network.
30
+ VCC
R1
39k
CC1
Vi
CC2
VO
R2
RE
3k9
1k
Solution: 1) Input resistance without considering the effect of biasing network-
R i' = h ie + (1 + h fe )R E = 1.1 + (1 + 100)1 = 102.1k
2) Input resistance taking into account the effect of biasing networkR i = R i' || R B = R i' || R 1 || R 2 = 102.1k || 39k || 3.9k = 3.42k
ASP 5.8: For the amplifier shown below, the BJT used has hie = 1k and hfe = 120.
Calculate 1) Miller resistances RM1, RM2 and hence Ri of the circuit. 2) AI. Assume C to
be arbitrarily large.
+ VCC
R1
82k
C
R3
VO
10k
Vi
R2
Ri
RE
8k2
Ri’
31
1k
Solution: This is a circuit of Bootstrapped Emitter Follower. Since voltage gain of
emitter follower circuit is close to unity. Effect of RM2 on output side can be neglected.
Figure below shows AC equivalent circuit that we can use for computation of
performance parameters-
VO
RM1
Vi
Ri
R1
RE
82k
R2
1k
RM2
8k2
AC ground
Ri’
The effective load resistance, across which output the is developed isR 'E = R E || R 1 || R 2 || R M 2 = 1k || 82k || 2k2 = 0.881 k
R i' = h ie + (1 + h fe )R `E = 1.0 + (121) (0.881 k)= 106.8 k
h
1 .0
A V = 1 − ie` = 1 −
= 0.99
106.8
Ri
Since AV is close to unity, our initial assumption that effect of RM2 will be negligible is
justified.
R3
10 k
R M1 =
=
= 1 .0 M
1 − A V 1 - 0.99
R i = R i || R M1 ≈ R i = 106.8k
AI =
IO IO Ib
R M1
1000
=
× = (1 + h fe ) ×
= (121)
= 109.32
Ii
Ib Ii
R M1 + R i 8
1000 + 106
ASP 5.9: A two-stage RC coupled BJT amplifier uses identical transistors with hfe = 120
and hie = 1k. Voltage divider biasing network uses R1 = 100k and R2 = 10k. RC for each
stage is 10k. Determine overall 1) Input resistance 2) Output resistance 3) Voltage gain.
Assume coupling and bypass capacitors to be arbitrarily large.
32
Solution: (Refer to Figure 5.78 of text). Adopting notations of this figure, R1 = 100k R2 =
10k R3 = 100k R4 = 10k RC1 = RC2 = 10k.
1) Overall input resistance of the amplifier is given byRi = R1 || R2 || hie = 100k || 10k || 1k = 900Ω
2) Since hoe is not specified, its effect on output resistance can be neglected. Hence
overall output resistance is RC2 = 10k.
3) To calculate voltage gain, we first determine input resistance of second stage. This is
give byRi2 = R3 || R4 || hie = 100k || 10k || 1k = 900Ω or 0.9k
Effective load resistance on first stage R 'L1 = R C1 || R i 2 = 10k || 0.9k = 0.825k
Voltage gain of first stage A V1 =
− h fe R 'L1 − h fe R 'L1 (−50)(0.825)
=
=
= −45.8
R i1
Ri
0.9
Voltage gain of second stage A V 2 =
− h fe R C 2 (−50)(10)
=
= −555.55
R i2
( 0 .9 )
Overall voltage gain =AV1 x AV2 = (-45.8) x (-555.55) = 25444.44
ASP 5.10: A Class A transformer coupled audio power amplifier shown in figure below
uses a step-down transformer with turns ratio 4:1. The output is adjusted for maximum
symmetrical swing. Input voltage is sine wave. Determine- 1) AC power delivered to
load 2) DC power input 3) Power dissipation rating of the transistor.
+VCC =+18V
N1: N2=4:1
R1
V1
V2
CC
Vi
R2
RE
CE
33
4Ω
Solution: For an ideal case and for maximum symmetrical swing,
Pac = Vrms xI rms =
Vm
2
x
Im
2
where Vm and Im are peak values of secondary voltage and current respectively. For
V
maximum symmetrical swing, VCE(min) = 0 and IC(min) = 0. Hence I m = m .
RL
∴ Pac =
Vm
2
x
Im
2
=
Vm
2
x
Vm
2R L
=
Vm2
2R L
In an ideal case, Vm(pri) = VCC = 18V.
Secondary peak voltage is determined using transformer’s turns ratio. HenceVm (sec) =
∴ Pac =
Vm ( pri )
n
Vm2 (sec)
2R L
=
18
= 4.5V
4
2
(
4 .5 )
=
2x 4
= 2.53W
Quiescent collector current is given byI CQ =
VCC
V
18
= 2 CC =
= 0.281A
'
RL
n R L 16 x 4
DC power input = Pdc = VCC x ICQ = 18 x 0.281 = 5.062W
Power dissipated by transistor (assuming ideal transformer and neglecting the power
dissipated by biasing network) is the difference between DC power input and AC power
output. HencePD = Pdc – Pac = 5.062 – 2.531 = 2.531W
Comment: As expected the theoretical maximum efficiency is 50%.
34
Chapter 5: Bipolar Junction Transistors and Applications
Additional Exercise Problems
AE 5.1: For the circuit shown below, determine the value of RB that will saturate the
transistor. Assume VBE(sat) = 0.8V and VCE(sat) = 0.2V. The transistor used has β = 100.
VCC = +12V
RC
1k
RB
VBB +
-
1.5V
AE 5.2: For the circuit shown below, determine the values of VCEQ and ICQ. The BJT
used has β = 80. Assume VBE(active) = 0.7V. What is the value of effective load resistance?
VCC=+12V
RB
470k
RC
2k7
VO
CC1
CC2
Vi
RL
10k
AE 5.3: For a BJT having following h-parameters, plot the graph of AI versus RL where
RL varies from 100Ω to 1M.
AE 5.4: For certain CE amplifier, BJT used has following h-parametershie = 1k
hfe = 100
hre = 1 x 10-4
hoe = 25µA/V
Calculate 1) Current gain 2) Input resistance 3) Voltage gain 4) Output resistance.
Neglect the effect of biasing network.
35
AE 5.5: For a bootstrapped Darlington pair shown below, calculate- 1) Overall voltage
gain 2) Overall input resistance. The BJTs used have following h-parametershie = 1.2k
hfe = 60
hoe = 20µA/V
Assume all capacitors to be arbitrarily large.
+ VCC
R3
R1
10k
C
1M
Vi
Q1
Q2
VO
R2
1M
RE
1k
AE 5.6: For the circuit shown below, derive an expression for 1) Voltage gain 2) Output
resistance in terms of small signal parameters of devices. Assume hfe = hoe = 0 for BJT
and RG >> R1 and R2.
+V
Vi
Q1
Q2
RG
R1
R2
AE 5.7: For an ideal Class B amplifier of complementary-symmetry type, VCC = +24V
and RL = 8Ω. Calculate 1) Theoretical maximum AC power delivered to load 2) Power
dissipated by each transistor.
36
AE 5.8: A HF transistor uses a BJT having following hybrid-p parameters-
rb b ' = 120Ω
rb 'e = 1k
rce = 100k
Ce = 100pF
CC = 3pF gm = 10mA/V. If
upper cut-off frequency is observed to be 20MHz, what must be the value of load
resistance for the stage?
37
Chapter 6: Operational Amplifiers and Applications
Additional Solved Problems
ASP 6.1: For the circuit shown in figure below, % error between theoretical and practical
output voltage is found to be 4%. Assuming that the error is entirely due to input offset
voltage, what must its value?
+
VO
Vin
+
-
50 mV
Rf
50k
R1
1k
Solution: Theoretical output voltage of this non-inverting amplifier is given by⎛ R ⎞
⎛ 50 ⎞
VO = Vin ⎜⎜1 + f ⎟⎟ = 50⎜1 + ⎟ = 2.55V
R1 ⎠
1 ⎠
⎝
⎝
Let the practical output be denoted by VO' . Since there is a 4% error between theoretical
and practical output, we have VO' = VO + 0.04VO = 2.652V
Expression for VO' for non-inverting amplifier is⎛ R ⎞
⎛ R ⎞
⎛ R ⎞
VO' = Vin ⎜⎜1 + f ⎟⎟ + VIO ⎜⎜1 + f ⎟⎟ = VO + VIO ⎜⎜1 + f ⎟⎟
R1 ⎠
R1 ⎠
R1 ⎠
⎝
⎝
⎝
Rearranging the terms, we getVO' − VO 2.652 − 2.55
=
= 2mV
VIO =
51
⎛ Rf ⎞
⎜⎜1 +
⎟
R 1 ⎟⎠
⎝
ASP 6.2: For the circuit shown in figure below, the output ripple is 2mV peak-to-peak. If
ripple in the power supply is 40mV peak-to-peak, what must be the PSRR of OPAMP in
dB?
38
Vin
+
VO
Rf
99k
R1
1k
Solution: The voltage gain of this non-inverting amplifier is given by⎛ R ⎞ ⎛ 99 ⎞
A V = ⎜⎜1 + f ⎟⎟ = ⎜1 + ⎟ = 100
R1 ⎠ ⎝
1 ⎠
⎝
Ripple in the output = AV x VIO
Hence VIO =
PSRR =
Output ripple 2mV
=
= 20µV
AV
100
∆VS
40mV
=
= 2000
∆VIO 20µV
PSRR in dB =20log10(2000) = 66dB
ASP 6.3: Closed loop bandwidth of an inverting amplifier having gain of –100 is
observed to be 40kHz. If f2 = 10Hz, what must be the open loop gain of the amplifier?
Solution: Using relation 6.30 from text, the open loop gain of amplifier is given by-
AO =
A f f 2f 100x 40x10 3
=
= 4 x10 5
f2
10
ASP 6.4: For the summing amplifier shown in figure below, determine the output
voltage.
Rf
22k
V1 =+2V
R1 10k
VO
V2 = +1.2V
R2 22k
R3 47k
39
+
Solution: The expression for output voltage isVO = −
Rf
R
R
22
22
22
V1 − f V2 − f V3 = − (2) − (1.2) −
(−4) = −3.72V
R1
R2
R3
10
22
47
ASP 6.5: For certain OPAMP, the slew rate limited output voltage is measured to be
200mV. If fmax = 1MHz, what must be the slew rate of OPAMP?
Solution: Slew rate = 2πfma x Vm = 2π x 1 x 106 x 200 x 10-3 = 0.125 V/µsec
ASP 6.6: For the inverting amplifier shown in figure below, the open loop gain of
OPAMP used in 100000. Determine Zif and Zof if ZO of OPAMP is 75Ω.
Rf
100k
R1
Vin
10k
VO
+
Solution: Zif for the inverting amplifier is nothing but R1 = 10K.
Closed loop output impedance is given byZO
ZO
75
Z Of =
=
=
= 75mΩ
R1
10
1 + A Oβ
4
1 + 10 x
1+ AO
100
Rf
Chapter 6: Operational Amplifiers and Applications
Additional Exercise Problems
AE 6.1: Determine the CMRR (in dB) if open loop gain of certain OPAMP is 4 x 105 and
common mode gain is 0.1.
40
AE 6.2: For certain OPAMP, the bias current is 40nA. Determine % error in the output
due to bias current 1) For inverting amplifier 2) For non-inverting amplifier when Vin =
20mV, Rf = 100k, R1 = 10k. Assume OPAMP to be ideal otherwise.
AE 6.3: For certain OPAMP used in non-inverting configuration, determine % error in
the output if OPAMP has following parametersVIO=1.2 mV IB = 20nA
CMRR = 80 dB
AO = 105
Input voltage to OPAMP is 100mV, Rf = 49k, R1 = 1k.
AE 6.4: Design a summing amplifier to give an output voltage –
1
1
1
VO = V1 + V2 + V3
3
10
2
Determine % error in output voltage if +10% tolerance resistors are used in above
inverting summing amplifier.
AE 6.5: Determine % error in closed loop gain of inverting amplifier where Rf = 100k R1
= 10k and AO = 105. Assume the OPAMP to be otherwise ideal.
41
Chapter 7: Frequency Response
Additional Solved Problems
ASP 7.1: In square wave testing of amplifier, a 200Hz square wave input results in 35%
sag in the output and application of 10kHz square wave input results in 100nsec rise time
in the output. Determine the bandwidth of amplifier.
Solution: %sag =
fH =
πf L
x100
f
∴fL =
%sga x f 35x 200
=
= 22.28Hz
100π
100π
0.35
0.35
=
= 3.5MHz
tr
100x10 −9
Bandwidth = fH – fL = 3.5MHz – 22.28Hz ≈ 3.5MHz
ASP 7.2: For CE amplifier shown in figure below, determine 2) Mid-band gain of
amplifier 1) Low frequency 3 dB cut-off if BJT used has hfe = 100 and hie = 1.2k. Neglect
the effect of biasing network.
+ VCC
RC
R1
2k2
CC2
rs
1k
VS
VO
Cb
RL
470µF
RE
R2
CE
1000µF
Solution: 1) Mid-band gain is given by A VSO =
h fe R C 100 x 2.2
=
= 100
rS + h ie
1 + 1 .2
2) To determine lower 3 dB cut-off frequency, we need to first calculate equivalent
capacitance. This is given by1
1 1 + h fe
1
1 + 100
=
+
=
+
= 0.12227 x10 6
−6
−6
C1 C b
CE
470 x10
1000 x10
42
Hence C1 = 8.178µF
Lower 3 dB cut-off frequency is given byfL =
1
1
=
= 8.846Hz
−6
2πC1 (rS = h ie ) 2πx8.178x10 1x10 3 + 1.2x10 3
(
)
ASP 7.3: In a cascade amplifier having 3 non-interacting identical stages, individual
amplifier has lower cut-off frequency of 100Hz and upper cut-off frequency of 1.8MHz.
What will be the bandwidth of cascade amplifier?
Solution: Overall low frequency cut-off is given by
f1n =
[2
f1
]
1/ 2
=
[
100
]
1/ 2
=
100
= 196.14Hz
0.509
21/3 − 1
−1
Overall high frequency cut-off is given by1/n
f2 n = f2 (21/n – 1)1/2 =1.8x106(21/3 – 1)1/2 = 917.68kHz
Bandwidth of cascaded amplifier = f2n – f1n = 917.68kHz – 0.196kHz = 917.49kHz
Chapter 7: Frequency Response
Additional Exercise Problems
AE 7.1: For CE amplifier shown in figure below, determine the overall low frequency
response of the amplifier. The BJT used has hie = 1k and hfe = 100.
+ VCC
RC
R1
100k
VS
1k
CC2
VO
rs
Cb
50Ω
470µF
100µF
RE
R2
10k
1k
CE
220µF
AE 7.2: For Exercise problem 7.1 above, does the amplifier implement dominant pole? If
no, what modification will be necessary in the circuit?
43
AE 7.3: The RC coupled amplifier shown in figure below gives fL = 10Hz. What must be
the value of hie of BJT used? Assume emitter bypass capacitor to be arbitrarily large.
AE 7.4: In a cascade arrangement of RC coupled amplifiers with identical noninteracting stages plot the graph of bandwidth versus number of stages (n) for n varying
from 2 to 5. Given f1 = 10Hz and f2 = 30Khz. How many stages would be required to
realize an audio amplifier?
AE 7.5: A two-stage JFET amplifier uses identical FETs with following parameters-
gm = 10mA/V rd = 10k.
The amplifier uses RD = 10k, RG = 1M and equivalent shunt capacitance per stage is
20pF. Determine- 1) Value of Cb to give frequency response 2 dB down at 10Hz. 2)
Overall mid-band gain.
44
Chapter 8: Feedback and Oscillators
Additional Solved Problems
ASP 8.1: For the block diagram shown below, derive an expression for
A Vf =
VO
VS
VS
Vi1
+
Α1
VO1
Vi2
+
Α1
VO
-
-
β1
β1
Solution: By inspection of figure-
Vi1 = VS - β1VO
VO1 = A1 x Vi1 = A1(VS-β1VO)
At second summing junction,
Vi2 = VO1 – β2VO = A1(VS – β1VO) – β2VO
The output voltage VO = A2 x Vi2 = A2[A1(VS – β1VO) - β2VO]
Combining terms in VO,
VO[1 + A2β2 + A1A2β1] = A1A2VS
V
A1A 2
∴ A Vf = O =
VS 1 + A 2 β 2 + A 1 A 2 β1
ASP 8.2: An amplifier is designed o have open loop gain of 1000. The amplifier delivers
12W output to load. The input voltage to amplifier is 10mV. Measured % second
harmonic distortion is 4%. If a 40dB negative feedback is applied and the output power is
to remain same, determine 1) New value of input signal 2) % second harmonic distortion.
Solution: 1) A 40 dB negative feedback amount to 20log10(1 + Aβ) = 40. Hence 1 + Aβ
= 100. Gain with feedback Af is-
45
Af =
A
1000
=
= 9.9
1 + Aβ 1 + 100
For amplifier without feedback, the original output voltage was VO = AVi = 1000 x
10mV = 10V. For amplifier with feedback, the closed loop gain is 9.9. Hence input
voltage required to produce same output power will beVi' =
A
1000
Vi =
x10mV = 1.01V
Af
9.9
2) For amplifier with feedback, the distortion reduces by factor D. Hence with a 40dB
negative feedback, harmonic distortion will be (4 / 100) i.e. 0.04%.
ASP 8.3: Open loop gain of an amplifier varies to the extent of +100 in the nominal value
of 4000. It is necessary to stabilize the closed loop gain to +0.4%. Determine- 1)
Desensitivity 2) Closed loop gain of the amplifier.
Solution: Fractional change of gain is given by∆A f
1
∆A 1 ∆A
x
=
= x
Af
1 + Aβ A
D A
∴D =
Af ∆A 100 100
x
x
=
= 6.25
4000 0.4
∆Af A
2) Closed loop gain for this value of D will beAf =
A 4000
=
= 640
D 6.25
ASP 8.4: For the circuit shown in figure below, BJT used has following h-parameters
hie = 1k
hfe = 100
1) Identify the feedback topology 2) Calculate AVSf and Rif. Assume all capacitors to be
arbitrarily large.
+ VCC
R1
100k
rs
RC1
RC1
18k
10k
CC2
VO
CC1
CC3
Q2
Q1
1k
VS
R2
46
R
10k
1k
E
RE1
CE
Rf
1k
Solution: Current flowing through RE1 and RE2 is sampled and mixed with input at the
base of Q1.
Opening the output loop makes feedback zero. Hence this is a case of current
sampling. Since this current is mixed in shunt with input current, this is a case of shunt
mixing. Hence we can conclude that this circuit represents current shunt feedback.
The AC equivalent circuit that we can use for analysis is shown below-
RC1
18k
RC1
Q2
rs
Q1
RE1
1k
VS
10k
RB=R1||R2
RM1
Vi1
V2
RE2
2k7
R f A 'V
≈ R f = 27 k
A 'V − 1
Effective resistance in emitter lead of Q2 isR M2 =
R 'E 2 = R E1 + (R E 2 || R M 2 ) = 1k + 2.45k = 3.45k
Input resistance for second stageR i 2 = h ie + (1 + h fe )R 'E 2 = 1 + (101)(3.45) = 349.45k
47
V1
1k
Vi2
Stage 1 is a CE amplifier. Hence AV1 >> 1. Hence A 'V =
VO
RM2
V1
>> 1 . Sing Miller’s theorem,
Vi1
h
V2
1
= 1 − ie = 1 −
= 0.997
Vi 2
R i2
349.45
Let A 'V 2 =
V1
V V
2.45
= i x 2 =
x 0.997 = 0.7
Vi 2 V2 Vi 2 3.45
Effective load on Q1 R 'L1 = R C1 || R i 2 = 18k || 349.45k ≈ 18k
A V1 =
Vi 2
R'
18
= − h fe L1 = (−100) x = −1800
Vi1
R i1
1
Let A 'V = A v1 xA 'V 2 = −1800x 0.7 = −1260
R M1 =
Rf
27 k
=
= 21.41Ω
'
1 − A V 1 − (−1260)
VO
R
10
= − h fe x C 2 = −100 x
= −2.86
349.45
Vi 2
R i2
AV = AV1 x AV2 = (-1800) x(-2.86) = 5148
A V2 =
VO
R if
= A V xβ = A V x
VS
R if + rS
where Rif = RM1 || Ri1 || R1 || R2 ≈ RM1 = 21.41Ω
A VSf =
Hence A VSf =
VO
21.41
= A V xβ = 5148x
= 107.85
21.41 + 1000
VS
ASP 8.5: For the circuit shown in figure below, determine 1) Avf 2) Rif 3)Rof. Biasing
network is omitted for simplicity. The BJT used has hie = 1k and hfe = 80.
+ VCC
rs
VO
600Ω
VS
Vi
RE
1k
48
Solution: We neglect unity in comparison with hfe in following calculations.
Open loop gain for the amplifier is given byVO
h R
80 x1k
= fe E =
= 50
Vi
rS + h ie 0.6k + 1k
r + h ie + h fe R E 0.6 + 1 + (80)(1)
Desensitivity D = S
= 51
=
rS + h ie
0 .6 + 1
A
50
1) A Vf = V =
= 0.98
D
51
2) Rif = RiD = rS + hie + hfeRE = 0.6 + 1.0 + (80)(1) = 81.6k
AV =
3) R Of =
rS + h ie 0.6 + 1
=
= 20Ω
h fe
80
ASP 8.6: For the circuit shown below, the closed loop gain measured is 10. If OPAMP
has open loop gain of 5 x 105, what must be the value of Rf?
Vi
+
VO
Rf
R1
10k
Solution: A >> 1. Hence
A
1
≈
1 + Aβ β
1
∴β =
= 0.1
A Vf
A Vf =
For non-inverting amplifier, β =
R1
= 0 .1
R1 + R f
Substituting R1 = 10k, we get Rf = 90k
49
ASP 8.7: For BJT amplifier shown in figure below, determine 1) AV 2) Avf 3) Rif 4) Rof.
BJT used are identical with hfe = 50 and hie = 1k. Assume all capacitors to be arbitrarily
large.
+VCC
R1
150k
Vi
RC1
R3
150k
12k
RC2
CC3
CC2
CC1
Q1
R2
R5
VO
Q2
CC4
CE1
3k9
R4
10k
4k7
Rif
10k
RE2
1k
CE2
Rf
4k7
ROf
R6
100Ω
Solution: It is necessary to derive the equivalent circuit of this feedback amplifier
without feedback. To determine the input circuit, we set VO = 0. This will connect top
end of Rf to AC ground. Thus R6 and Rf will be in parallel with each other. If we denote
this by RE1, RE1 = R6 || Rf = 0.1k || 4.7k ≈ 0.1k.
Effective load on second stage R 'L 2 = R C 2 || (R f + R 6 ) = 10k || 4.8k = 3.24k
A V2 =
− h fe R 'L 2 − 50 x3.24
=
= −162
h ie
1
Effective load on first stage R 'L1 = R C1 || R 3 || R 4 || h ie = 12k || 150k || 10k || 1k = 840Ω
A V1 =
− h fe R 'L1
− 50x 0.84
=
= −6.88
h ie + (1 + hfe)R E 1 + (51)(0.1)
AV = AV1 x AV2 = (-6.88) x (-162) = 1114.56
β=
R6
0 .1
=
= 0.02
R 6 + R f 4 .7 + 0 .1
D = 1 + βAV = 1 + (0.02)(114.56) = 23.29
50
A Vf =
A V 1114.56
=
= 47.85
D
23.29
Input resistance without feedback Ri = hie + (1+hfe)RE = 1 + (51)(0.1) = 6.1k
Input resistance with feedback Rif = Ri x D = 6.1 x 23.29 = 142k
Output resistance without feedback RO = R 'L 2 = 3.24k
Output resistance with feedback R Of =
RO
3.24
=
= 0.139k = 139Ω
D
23.29
ASP 8.8: For the simplified circuit shown in figure below, 1) Identify the topology of
feedback 2) Determine Avf. The BJTs used are identical with hie = 1k and hfe = 100.
+ VCC
RC1
22k
Q2
rs
VO
Q1
1k
Ii
VS
RE1
2k2
RE2
2k2
Solution: If we short the output, feedback voltage across RE2 becomes zero. Hence this is
a case of voltage sampling. The feedback voltage across RE2 is mixed in series with input.
Hence this amplifier represents voltage series feedback topology.
To find the input circuit, we set VO = 0. This connects RE1 and RE2 in parallel
between Q1 emitter to ground.
To find the output circuit, we open circuit input loop. This connects RE1 + RE2
across output. The resultant AC equivalent circuit that we can use for analysis is shown
belowrs
IC1
B1
C1
B2
Ib1
2k
VO
Ib2
hfeIb1
RE1
hie
1k
Vs
Vi1
2k2
E
RC1
22k
51 V
hfeIb2
i2
hie
1k
Vf
RE2
2k2
As seen from figure, Vf = βVO =
R E2
VO
R E1 + R E 2
Hence β = 0.5.
Voltage gain without feedback A V =
VO VO Vi 2
=
x
= A V 2 xA V1
Vi
Vi 2 Vi1
Effective load on second stage R 'L 2 = R E1 + R E 2 = 4.4k
Input resistance of second stage Ri2 = hie.
Hence A V 2 =
− h fe xR 'L 2 − 50x 4.4
=
= −220
R i2
1
Effective load on first stage R 'L1 = R C1 || h ie = 22k || 1k = 0.956k
− h fe xR 'L1 − 50x 0.956
=
= −47.8
h ie
1
Overall voltage gain AV = AV2 x AV1 = (-220) x (-47.8) = 10516
Voltage gain of first stage A V1 =
Desensitivity D = 1 + βAV = 1 + (0.5)(10516) = 5259
Gain with feedback A Vf =
A V 10516
=
= 1.99
D
5259
ASP 8.9: A BJT Hartley oscillator uses variable trimmer capacitor to change the
frequency of oscillations. Capacitor varies between 5pF and 50pF. If L1 = L2 = 1mH,
determine the range of frequency for oscillator circuit. Neglect mutual coupling between
L1 and L2.
Solution: Leq = L1 + L2 = 2mH
52
fO =
1
2π L eq C
Hence f O max =
and f O min =
1
2π L eq C min
1
2π L eq C max
=
=
1
2π 2 x10 −3 x 5x10 −12
1
−3
2π 2 x10 x 50 x10 −12
= 1.59MHz
= 503.29kHz
ASP 8.10: For certain FET Colpitt oscillator (Figure 8.55), C1 = 0.01µF and C2 =
0.001µF. If L = 2µH, determine 1) Gain of oscillator circuit 2) Frequency of oscillations.
Assume Q of resonant circuit to be arbitrarily large.
Solution: Gain of oscillator circuit is given byC1
0 .1
=
= 10
C 2 0.001
Frequency of oscillations is given byA=
fO =
1
2π LC eq
Hence f O =
where C eq =
1
2π LC eq
=
C1 C 2
0.01x 0.001
=
= 0.09µF
C1 + C 2 0.01 + 0.001
1
−6
2π 2 x10 x 0.09 x10 −6
= 375.13kHz
Chapter 8: Feedback and Oscillators
Additional Exercise Problems
AE 8.1: For a negative feedback amplifier, open loop gain is 200 and β = 0.01. If input
signal of 10mV from microphone is applied, determine 1) Voltage gain with feedback 2)
output voltage 3) Feedback voltage.
AE 8.2: A negative feedback amplifier has open loop gain of 80dB. If β = 0.002, what
will be the change in closed loop gain if open loop gain changes by +12%.
AE 8.3: For a negative feedback amplifier, fL = 100Hz and fH = 20kHz. Open loop gain
of the amplifier is 1000. If β = 0.02, determine 1) Closed loop gain 2) Bandwidth with
feedback.
AE 8.4: For certain negative feedback amplifier, the open loop gain of 1000 falls to 160
when negative feedback is applied. Determine the feedback factor in dB.
53
AE 8.5: For the feedback amplifier shown in figure below, identify the feedback
topology. Calculate 1) Avf 2) Rif 3) Rof. The BJTs used have hfe = 100 and hie = 1.1k.
Assume all capacitors to be arbitrarily large. Biasing network is omitted for simplicity.
+ VCC
RC2
2k5
RC1
100k
CC1
CC3
CC2
VO
Q2
Q1
Vi
RE1
RE2
470Ω
CE
1k2
AE 8.6: For a two-stage JFET amplifier shown below, identify the topology of feedback
and determine 1) Avf 2) Rif 3) Rof. JFETs used have rd = 10k and gm = 4 mA/V.
+VDD
RD1
47k
RD2
22k
Q2
Q1
RG1
1M
VO
CC2
CC1
Vs
CC3
RS1
270Ω
RG2
1M
54
RS2
270Ω
CS
Rf
10k
AE 8.7: For a 3-stage BJT amplifier shown in figure below, derive an expression for 1)
Feedback factor 2) Avf.
+ VCC
RC2
RC1
RC3
VO
CC1
Vi
RE1
Q3
Q2
Q1
Rf
RE2
AE 8.8: For a BJT Hartley oscillator, L1 = 1 mH, L2 = 1 mH and M = 20µH. If a variable
capacitor is used to adjust the frequency of oscillations between 1kHz to 2 kHz,
determine the value of Cmin and Cmax.
AE 8.9: For certain quartz crystal, equivalent circuit components have following valuesLS = 0.39H RS = 4k
1) If series resonant frequency of oscillator is 1.000MHz, what must be the value of CS?
2) If parallel resonant frequency of oscillations is 1.2MHz, what would be the value of
CM?
55
Chapter 9: Linear Voltage Regulators and Voltage References
Additional Solved Problems
ASP 9.1: For FWR, capacitor filter arrangement, Vdc = 24V and equivalent load
resistance is 200Ω. If filter capacitor used is 1000µF, what will be the RMS ripple
voltage? Assume 50Hz mains operation.
Solution: Vrms =
Hence Vrms =
I dc
4 3fCR L
I dc
4 3fCR L
=
where I dc =
Vdc
24V
=
= 120mA
R L 200Ω
120 x10 −3
4x 3x50x1000x10 −6
= 34.64mV
ASP 9.2: A +12V Dc voltage is derived from FWR capacitor filter arrangement. The
power supply is used to drive 4-digit, 7-segment LED display. Each segment draws a
current of 5mA. If the display can tolerate RMS ripple of 0.8V, determine the value of
filter capacitor.
Solution: In the worst case, i.e. when all segments are ON, the current demanded by load
(display) is
Idc = No. of digits x No. of segments per digit x Current per segment = 4 x 7 x 5 =
140mA.
This load current, drawn from +12V supply amounts to the equivalent load resistance ofRL =
Vdc
12V
=
= 85.71Ω
I dc 140mA
Using the expression for ripple factor
r=
VrRMS
1
=
Vdc
4 3fCR L
∴C =
Vdc
1
12
1
x
=
x
= 505.2µF
VrRMS 4 3fCR L 0.8 4x 3x50x85.71
ASP 9.3: A +12V dc power supply provides current of 200mA. If DC voltage is derived
from FWR –LC filter arrangement powered by 50Hz AC mains, determine the value of
critical inductance.
Solution: We first calculate equivalent load resistance. This is given by-
56
Vdc
12V
=
= 60Ω
I dc
200mA
The value of critical inductance is given byRL =
LC =
RL
60
=
= 63.66mH
942.5 942.5
ASP 9.4: A DC regulated power supply has load regulation of 4% at full load current of
100mA. If no load voltage is +25V, determine 1) Full load voltage 2) Equivalent output
resistance of regulator.
Solution:
% Load regulation=
∴
VNL − VFL
x100
VNL
VNL − VFL
= 0.04
VNL
Since VNL = 25V, VFL = VNL+0.04VNL = 25 – (0.04)(25) = 24V
Equivalent output resistance=
VFL − VNL 25 − 24
=
= 10Ω
I FL
100mA
ASP 9.5: Design a IC 723 based voltage regulator (Refer to Figure 9.29) to give a
nominal output voltage of +5V with maximum load current of 100mA. Assume R2 = 5k
Solution: Referring to expressions 9.43 to 9.46, we can determine the required values.
R SC =
R2 =
0.66
0.66
=
= 6 .6 Ω
I L (max) 100mA
VO
V
(R 1 + R 2 ) = O (R 1 + R 2 )
VREF
7 .0 V
5.0
(R 1 + 5.0)
7.0
where resistor values are substituted in kΩ.
∴ 5.0 =
57
Hence R1 = 2k.
R 1R 2
2x5
=
= 1.42k
R1 + R 2 2 + 5
Practically one may use R3 as 1.5k.
To minimize offset error, R 3 =
Chapter 9: Linear Voltage Regulators and Voltage References
Additional Exercise Problems
AE 9.1: Output voltage of a FWR-filter capacitor arrangement shows a peak value of
9.8V and minimum value of 9.0V. If equivalent load resistance is 100Ω and filter
capacitor used is 1000µF, determine- 1) DC output voltage of the circuit 2) Ripple factor.
Assume 50 Hz AC mains operation.
AE 9.2: Many battery eliminators require 9V DC output. Design an eliminator circuit
that will provide a maximum of 120mA load current with maximum allowable ripple of
2%. Assume FWR-LC filter arrangement and 50Hz AC mains operation.
AE 9.3: Design a zener regulator circuit to give nominal output of +12V DC at 20mA. If
zener used has IZT = 10mA and maximum input voltage is 20V, determine variation in the
output voltage if input changes fro 16 to 20V for the selected zener. Also determine
maximum power that can be dissipation by the selected zener.
AE 9.4: A zener regulator circuit uses zener diode with following parametersVZ = 6.0V
IZT = 40mA ZZ = 2Ω
PZ = 750mW
IZmin = 1mA
If unregulated input changes between 12 to 18V, determine- 1) Maximum permissible IZ
2) Value of series limiting resistor 3) Power dissipation rating of series resistor 4)
Maximum permissible load current.
58