Department of Electrical & Computer Engineering
94 Brett Rd • Piscataway • New Jersey 08854-8058
Professor Paul Panayotatos
332:364 Analog Electronics Laboratory
Laboratory Experiment I
Composite Transistor Amplifiers
I.1
Introduction
Objectives
•
•
To demonstrate the properties of differential amplifiers
To demonstrate the properties of cascode amplifiers
Overview
This lab is designed to familiarize the student with the properties of the differential
and cascode amplifier circuit topologies. The laboratory experiment is divided into
two activities:
(A) The first activity involves the operation of a differential amplifier in both the
common mode and the differential mode.
(B) The second activity involves connecting the same two transistors in cascode
amplifier configuration. Cascode amplifiers combine the properties of commonemitter and common-base circuits. The properties of the individual stages of the
cascode amplifier will be compared to the properties of the composite (entire)
cascode amplifier.
The four actual laboratory experiments are designed to verify the concepts by direct
measurement of voltages.
Some of the necessary theory is presented below and the prelab exercises are
designed to promote familiarity with the concepts.
Designed by M. Caggiano
Latest revision: 8/27/08 by P. Panayotatos
Analog Electronics Lab-I p.2/10
I.2
Theory
I.2.1
Basic Operation of the BJT differential pair1
Figure 7.13 Different modes of operation of the BJT differential pair: (a) The
differential pair with a common-mode input signal vCM. (b) The differential pair with a
“large” differential input signal.
First consider the case of Figure 7.13a where the two bases are tied together. Then vB1=
vB2= vCM. If Q1 and Q2 are matched, and assuming an ideal bias current source I with
infinite output resistance2, it follows that the current I will remain constant and from
symmetry that I will divide equally between Q1 and Q2. Thus iE1=iE2= I/2, and the voltage
at the emitters will be vCM- VBE, where VBE is the base-emitter voltage (assumed to be
approximately 0.7 V) corresponding to an emitter current of I/2. The voltage at each
collector will be Vcc – 1/2 !IRc, and the difference in voltage between the two collectors
will be zero.
1
Adapted from Section 7.3.1, “Microelectronic Circuits” by Adel Sedra and Kenneth Smith, 5th Edition,
Oxford University Press, New York, 2004. Consult subsequent sections as needed.
2
None of these assumptions will be true in practice; keep this in mind when you interpret your results.
Analog Electronics Lab-I p.3/10
Now let us vary the value of the common-mode input signal vCM. Obviously, as long as Q1
and Q2 remain in the active region the current I will still divide equally between Q1 and
Q2, and the voltages at the collectors will not change. Thus the ideal differential pair does
not respond to (i.e., it rejects) common-mode input signals.
As another experiment, let the voltage vB2 be set to a constant value, say, zero (by
grounding B2), and let vB1 = +1 V (see Fig. 7.13b). With a bit of reasoning, it can be seen
that Q1 will be on and conducting all of the current I and that Q2 will be off. For Q1 to be
on (with VBE1 = 0.7 V). the emitter has to be at approximately +0.3 V, which keeps the
EBJ of Q2 reverse-biased. The collector voltages will be vC1 = Vcc – !IRc, and vC2 = Vcc.
Figure 7.13 (Continued) (c) The differential pair with a large differential input signal
of polarity opposite to that in (b). (d) The differential pair with a small differential
input signal vi. Note that we have assumed the bias current source I to be ideal (i.e., it
has an infinite output resistance) and thus I remains constant with the change in vCM.
Let us now change vB1 to -1 V (Fig. 7.13c). Again with some reasoning it can be seen
that Q1 will turn off and Q2 will carry all the current I. The common emitter will be at
-0.7 V, which means that the EBJ of Q1 will be reverse-biased by 0.3 V. The collector
voltages will be vC2 = Vcc – !IRc, and vC1 = Vcc.
From the foregoing, we see that the differential pair certainly responds to large
difference-mode (or differential) signals. In fact, with relatively small difference voltages
we are able to steer the entire bias current from one side of the pair to the other.
To use the BJT differential pair as a linear amplifier we apply a very small differential
signal (a few millivolts), which will result in one of the transistors conducting a current of
I/2 + "I: the current in the other transistor will be I/2 - "I, with "I being proportional to
Analog Electronics Lab-I p.4/10
the difference input voltage (see Fig. 7.13d). The output voltage taken between the two
collectors will be 2!"IRC, which is proportional to the differential input signal vi.
I.2.2
Basic Operation of the BJT cascode amplifier3
Figure 6.40 (a) The BJT cascode amplifier. (b) The circuit prepared for small-signal
analysis with various input and output resistances indicated. Note that rx is neglected.
(c) The cascode with the output open-circuited.
By placing a common-base (or common-gate) amplifier stage in cascade with a commonemitter (or common-source) amplifier stage, a very useful and versatile amplifier circuit
results. It is known is the cascode configuration and has been in use for nearly three
quarters of a century, obviously in a wide variety of technologies.
The basic idea behind the cascode amplifier is to combine the high input resistance and
large transconductance achieved in a common -emitter amplifier with the currentbuffering property and the superior high-frequency response of the common-base circuit.
The cascode amplifier can be designed to obtain a wider bandwidth but equal dc gain as
compared to the common- emitter amplifier. Alternatively, it can be designed to increase
the dc gain while leaving the gain-bandwidth product unchanged. Of course, there is a
continuum of possibilities between these two extremes.
Figure 6.40(a) shows the BJT cascode amplifier. Here transistor Q1 is connected in the
common-emitter configuration and provides its output to the input terminal (i.e., emitter)
of transistor Q2. Transistor Q2 has a constant dc voltage, VBIAS, applied to its base. Thus
the signal voltage at the base of Q2 is zero and Q2 is operating as a CB amplifier with a
constant current load, I. Obviously both Q1 and Q2 will be operating at dc collector
3
Adapted from Sections 6.8, 6.8.1 and 6.8.3, “Microelectronic Circuits” by Adel Sedra and Kenneth
Smith, 5th Edition, Oxford University Press, New York, 2004. Consult subsequent sections as needed.
Analog Electronics Lab-I p.5/10
currents equal to I. Also, the value of VBIAS has to be chosen so that both Q1 and Q2
operate in the active region at all times.
The small-signal analysis is indicated in Fig. 6.40(b), where the various input and output
resistances are shown. The BJT cascode has an input resistance of r#1 (neglecting rx). The
formula for Rin2 is the one found in the analysis of the common-base circuit namely:
Rin2 =
1
R
+ L
gm 2 + gm1 Avo2
The output resistance Rout = $2ro2 is found by substituting Re = ro2 in
Rout %(1+gmRe||r#)ro
and making the approximation that gm ro >> $. Recall that $ ro is the largest output
resistance that a CB transistor can provide.
The open-circuit voltage gain Avo and the no-load input resistance Ri can be found from
the circuit in Fig. 6.40(c) in which the output is open-circuited. Observe that Ri2 = r#2,
which is usually much smaller than ro1. As a result the total resistance between the
collector of Q1 and ground is approximately r#2 ; thus the voltage gain realized in the CE
transistor Q1 is -gm1r#2= -$. Recalling that the open-circuit voltage gain of a CB amplifier
is 1+gmro % &o we see that the voltage gain &vo is &vo = -$&o
I.3
Prelab Assignment: PSPICE simulation of experiments
Read the experiment that follows and simulate all activities that will be performed in the
laboratory using the computer software tool OrCAD PSPICE.
Make sure to bring the PSPICE results to the laboratory. In addition to being an aid in
immediately verifying measured results, they will be the basis of your Prelab grade for
this lab.
Specifically, the following items must be addressed using OrCAD PSPICE as part of the
prelab assignment:
• Circuit drawings with the nodes labeled and with DC node voltages;
• Magnitude and phase Bode plots of the voltage gains (i.e., generally Vout/Vin in dB).
Fill in all entries in the tables provided below that are labeled “calculated”.
Analog Electronics Lab-I p.6/10
I.4
Experiments
Suggested Equipment
Protoboard
Tektronix FG501A or Tektronix AFG3021 Function Generator
Agilent 34401A Digital Multimeter
Tektronix PS 503A Power Supply
Resistors: 3 x 10 kΩ, 2 x 470 Ω, 2 x 1kΩ, 10 Ω
Transistors: 2 x 2N3904
Capacitors: 2 x 100 µF
Variable Resistance Box
Laboratory Activities
I.4.A. Activity A:
Emitter-Coupled Pair Differential Amplifier
In this activity, the operation of a differential amplifier will be explored. There will be
three parts to this activity with different resistance values for R1 , R2 and R3 in each part.

I.4.A.a. Build the circuit given in Fig. I.1 with the following resistance values:
R1 = 470! , R2 = 0! , R3 = 470! .
Note that setting R2 = 0! shorts the bases of the two transistors together so that the
input becomes common-mode.
Q2
Q1
Fig. I.1: Circuit schematic of the emitter-coupled pair differential amplifier.
Analog Electronics Lab-I p.7/10
(i)
Measure the DC node voltages at the emitter, base, and collector of each
transistor of the circuit with the above resistor values. Ensure that the
measured node voltages correspond with the simulated/calculated voltages, to
within a 20% margin of error.
Activity A. Part a: R1 = 470! , R2 = 0! , R3 = 470! DC voltages
Vcalc (V)
Vmeas (V)
% error
VE1
VB1
VC1
VE2
VB2
VC2
(ii)
Input a sinusoidal signal of amplitude 1 V rms and frequency of 1 kHz to the
circuit and measure the AC voltages at the output of the signal generator, the
base of each transistor and the collector of each transistor (i.e., the output of
the amplifier).
(iii)
Determine the voltage gain of the circuit from the measurements outlined
above and cross-check these results with the computer simulation results
obtained as the prelab.
Activity A. Part a: R1 = 470! , R2 = 0! , R3 = 470! AC voltages
Vcalc
Vmeas Avmeas Avmeas Avcalc
Avcalc
%
V
V
V/V
dB
dB
V/V
error
Vs
Vb1
Vc1
Vb2
Vc2

I.4.A.b. Modify the circuit of Fig. I.1 with the resistance values of part b: R1 = 1k! ,
R2 = 10! , R3 = 0! . Note that setting R3 = 0! grounds the base of Q2.

Repeat activities (i), (ii) and (iii) for the values of part b.
Analog Electronics Lab-I p.8/10
Activity A. Part b: R1 = 1k! , R2 = 10! , R3 = 0! DC voltages
Vcalc (V)
Vmeas (V)
% error
VE1
VB1
VC1
VE2
VB2
VC2
Activity A. Part b: R1 = 1k! , R2 = 10! , R3 = 0! AC voltages
Vcalc
Vmeas
Avmeas Avmeas Avcalc % error
V
V
V/V
dB
dB
Vs
Vb1
Vc1
Vb2
Vc2

I.4.A.b. Modify the circuit of Fig. I.1 with the resistance values of part c: R1 = 470! ,
R2 = 10! , R3 = 470! .

Repeat activities (i), (ii) and (iii) for the values of part c.
Activity A. Part c: R1 = 470! , R2 = 10! , R3 = 470! . DC voltages
Vcalc (V)
VE1
VB1
VC1
VE2
VB2
VC2
Vmeas (V)
% error
Analog Electronics Lab-I p.9/10
Activity A. Part c: R1 = 470! , R2 = 10! , R3 = 470! . AC voltages
Vcalc
Vmeas
Avmeas Avmeas Avcalc % error
V
V
V/V
dB
dB
Vs
Vb1
Vc1
Vb2
Vc2
I.4.B. Activity B: Cascode Amplifier
In this activity, the operation of a cascode amplifier will be explored.

Build the circuit given in Fig. I.2.
Fig. I.2: Circuit schematic of the cascode amplifier.
(i)
With the input shorted to ground, measure and record the DC node voltages at
each collector. If you do not obtain node voltages within 20% of those
calculated, fix the circuit before proceeding.
Analog Electronics Lab-I p.10/10
Activity B. DC voltages
Vcalc (V)
Vmeas (V)
% error
VC1
VC2
(ii)
Input a sinusoidal signal of amplitude 1 V rms and frequency of 1 kHz to the
circuit and measure the AC voltages at the output of the signal generator, the
base of each transistor and the collector of each transistor (i.e., the output of
the amplifier).
(iii)
Determine the voltage gain of the circuit from the measurements outlined
above and cross-check these results with the computer simulation results
obtained as the prelab.
Vcalc
V
Activity B. AC voltages
Vmeas
Avmeas Avmeas
V
V/V
dB
Avcalc % error
dB
Vs
Vb1=Vi
Vc1
Vb2
Vc2
I.5
Report
The laboratory report should follow the outline given in the handout titled “Laboratory
Report Guidelines.”
The following items should be addressed in the appropriate sections of the report:
I.5.1-4. DC nodal analysis for each circuit and circuit variation (four in total) in this
laboratory experiment;
1.5.5-9. AC analysis (including voltage gains) for each circuit and circuit variation
(four in total) in this laboratory experiment;
1.5.10. Comparisons of the measured results with the calculated results, as well as with
the computer simulation results obtained as the prelab.