EE 171
Differential Amplifiers
University of California, Santa Cruz
May 17, 2007
EE 171
(Spring 2007)
1
Agenda
• Differential Pair Large Signal Analysis
• Differential Pair Small Signal Analysis
• Multi-stage design example: CMOS Op-amp
EE 171
(Spring 2007)
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Differential Pair
• Most op-amps use a differential pair as the input stage
• Two inputs
– Can be modeled as a differential voltage and a common-mode voltage
vid = v i1 − v i 2
Basic BJT differential amplifier.
EE 171
(Spring 2007)
v ic =
1
(vi1 + vi 2 )
2
3
Input: Pure Common Mode Signal
• Vi1 = Vi2
– Vid = 0, Vic = Vi1 or Vi2
– Single input source
• By symmetry, IEE splits equally between Q1 and Q2
– IE1 = IE2 = IEE/2
• Differential output voltage will be zero.
• Output voltage is not
affected by a signal
that is the same on
both inputs
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v o 2 = VCC − I EER C
2
4
Input: Pure Differential Signal
• Vi1 = – Vi2
– Vid = Vi1 or Vi2, Vic = 0
• Positive voltage applied to the base of Q1 turns it on more than Q2
– For a large enough signal, Q2 is off
– IE1 = IEE and IE2 = 0
• Output voltage is maximized
– Emitter currents show maximum difference
• Amplified through BJT
– vod = –RcIEE
I E1 + I E 2 = I EE
EE 171
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Transfer Characteristics
• Output clips for input voltages above 4 VT
Common mode
Collector currents versus differential input voltage.
EE 171
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Only -0.1 v
(at room temp)
Voltage transfer characteristic
of the BJT differential amplifier.
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Emitter Degeneration
• To increase the horizontal range, add an emitter resistor (REF)
– Higher input impedance and lower AC gain (think common-emitter
amplifier)
• Lower distortion (more linear transfer characteristic)
For REF = 40(VT/IEE)
Differential amplifier with emitter degeneration resistors.
EE 171
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was –4VT
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Differential Amplifier Output
• Output can be both nodes (balanced) or just one
node (single-ended)
– In the single ended case, we do not need one of the
collector resistors.
Either a balanced or single-ended output is available from the differential amplifier.
EE 171
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Differential Pair with Current Mirror Load
• To further reduce resistor count, a current mirror can be used
– Low base current: ic3 = ic1
– By symmetry: ic3 = ic4
– io = ic4 – ic2 = ic1 – ic2 (differential output)
• World’s simplest op-amp
– Gain is a bit low but could be
useful in integrated applications
Emitter-coupled pair with current-mirror load.
EE 171
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Small Signal Analysis
• Small signal equivalent circuit
– REB: model for the current source (output impedance: large)
• Use symmetry
– Break circuit into two symmetric half circuits
• Can only be done if the input signals are purely common mode or differential
mode
rπ
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rπ
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Small Signal Analysis: Differential Mode
• Node J = ground
– Circuit is symmetric and the voltage at this node does not change
(virtual ground)
• Write KVL equations to
find gain and Rin
v id
= rπ i b1 + ( β + 1)i b1R EF
2
– Input: vid (voltage difference
between BJT bases)
v o1 = −R C β i b1
– Output: single branch
A vds =
v o1
R Cβ
=−
vid
2[rπ + ( β + 1) R EF ]
• Rout: short input
R id =
vid
= 2[rπ + ( β + 1) R EF ]
i b1
R os = R C
• For balanced output, gain and Rout
are 2x larger
v out = v o1 − vo 2
EE 171
(Spring 2007)
rπ
A vdb = 2 A vds
R ob = 2R os
Half-circuit for a differential input signal.
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Small Signal Analysis: Common-mode
• Split current source resistance
• Use symmetry
– No current across the dotted line
Only ½ of total input current
Additonal R
(vs. differential circuit)
Small-signal equivalent circuit with a pure common-mode input signal.
EE 171
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Half-circuit for a pure
common-mode input signal.
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Common Mode Results
Extra term (lower common mode gain)
A vcm =
R icm
v o1
R Cβ
=−
v icm
rπ + (β + 1)(R EF + 2R EB )
v icm
rπ + (β + 1) R EF
=
=
+ (β + 1)R EB
i b1 + i b 2
2
R os = R C
Same gain and input
resistance for balanced
and single-ended outputs
R ob = 2R os
Summary: Table 7.2 (p. 450)
EE 171
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Design of Differential Amplifiers
• Want a high differential gain and a low common mode gain
To further increase CMRR,
cascade differential amps
(Figure 7.29a)
Differential and
common mode
components
Input signals
(not quite sinusoids)
2.5
Output signal
Common mode signal removed
Differential signal amplified
2
1.5
1
0.5
0
-0.5
0
0.02
0.04
0.06
0.08
0.1
vi1
vi2
-1
-1.5
-2
-2.5
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Design of Differential Amplifiers
• Operating point: choose so that no clipping occurs
– VCEQ > 0.2 v + voltage swing on output
– ICEQ > peak AC current flow through load
– Choices here determine current source (IEE: 2 x ICEQ), rπ, and
collector resistance (Rc)
• REF can be chosen to yield a certain differential gain (Avd)
• Choice of current source determines REB (and CMRR)
• See Example 7.4 and Exercise 7.13
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PNP Differential Pair
• Current source on top
• Collector resistors on bottom
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Design Example: A Two Stage CMOS Op-amp
• 1st stage: differential amplifier
– Input: M3 and M4 (PMOS transistors)
– Current source: M1 and M8 (PMOS implementation)
• Current steers to M3 side or M4 side depending on input voltages
– Current mirror: M6 and M7
(replaces Rc)
– Output: io1 (single-ended)
• io1 = iD4 – iD3
• 2nd stage: NMOS common
source amplifier
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MOS Differential Amplifiers
• Large signal characteristics: similar to BJT
• Small signal circuit
– Results: Table 7.3
(Rin infinitely large)
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CMOS Op-Amp: Input Stage (Small Signal Model)
• For the two stage CMOS op-amp here, resistors (RD) are not
used and the transistors are PMOS
– Requires slight changes in the small signal circuit (add output resistors)
Assume differential input
(virtual ground by symmetry)
v gs7
rd 6
+ g m 6 v gs6 + g m 4 vgs 4 +
gm4 = gm3
g m 5 v gs6 + g m3 vgs3 ≈ 0
gm5 = gm6
vgs7
rd 4
=0
(by symmetry)
(assume rd3, rd5 large)
EE 171
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A=
v gs 7
vd
= −g m 4
rd 4rd 6
rd 4 + rd6
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CMOS Op-Amp: Output Stage
• Gain of second stage
AV2= –gm7(rd7 || rd2)
• Total gain is the product
AV = gm4 gm7(rd4 || rd6) (rd7 || rd2)
Small-signal equivalent circuit for the
output stage consisting of M7 and M2.
• Frequency response of whole
op-amp will be composed of the
response of the first stage and
the response of the second stage
– Resembles frequency response
of at typical op-amp (Fig. 2.25)
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