IOJETR TRANSACTIONS ON ELECTRICAL DRIVES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
Current Control for Three-Phase Diode Rectifier
Abstract—In this paper, a dc link active power filter (APF) for three-phase diode rectifier is proposed.
The proposed dc link APF, which is composed of two series-connected bidirectional boost converters,
intends to eliminate the input current harmonics. It is paralleled at the dc link of the diode rectifier and is
coupled to the ac input with three line-frequency switches. Compared with the full power processed
power factor correction (PFC) solution, the dc link APF is partially power processed in that it only
compensates for the harmonic current component at the dc link. Thus, it features with lower power
processing. Moreover, it exhibits better total harmonic distortion of the ac line current when compared
with the traditional ac side shunt APF. Voltage and current loop models are developed for average
current control, and the selection of the current loop bandwidth is presented. Switching stresses of the ac
APF, the dc link APF, and the six-switch PFC are also calculated and analyzed. Experimental and
simulation results demonstrate the effectiveness of this dc link APF.
Index Terms—Active power filter (APF), bandwidth, compensation performance, diode rectifier, power
factor correction (PFC).
I.
INTRODUCTION
A four-quadrant inverter is commonly used in the power stage of the ac side APF, and an ac side APF always
needs complicated harmonic current detection and control. On the other hand, the three-phase power factor
correction (PFC), which is a full power processing solution, has been extensively studied [12]–[19]. The most
popular topology of the three-phase PFC is a six-switch bridge. This type of PFC has the feature of bidirectional
power flowing capability. In some specific applications, unidirectional PFC topologies such as the Vienna
converter [15], [16] and the series connected dual boost converter [19], [20] are considered. Both bidirectional
and unidirectional three-phase PFCs are required to process all the load power. Thus, most of them suffer from
higher silicon cost as compared with the APF solutions which require only partial power processing. Multipulse
rectifiers, which employ low frequency phase shift transformer to synthesize reasonable line current waveform,
are also reported for the reduction of the silicon cost [17], [18]. Due to the application of low frequency
transformer, the volume is a critical limitation.
For three-phase diode rectifiers, low cost harmonic elimination methods, which adopt a few passive or
active components to inject triple-order harmonic currents at the dc link of the three-phase diode rectifier for
line current correction and harmonic injection, have been reported [21]–[27]. The circuit presented in [21] is a
series connected dual-boost converter with tuned LC filter which functions as a third order harmonic current
injection network. Later, the tuned LC filter is replaced with a low frequency zigzag connected transformer so
that the parameter variation effect of the LC filter can be avoided [22]. The active switches in these two
topologies need to process all the output power at high switching frequency while the LC filter suffers from
parameter sensitivity, and low frequency zigzag transformer still appears large volume. To eliminate active
switches, passive harmonic current injection circuits, which combine separate LC filter and low frequency
stardelta transformer, have been proposed [23]–[25]. Similar to the circuits in [21], [22], these circuits still
experience parameter sensitivity and large volume. To dodge the parameter sensitivity effect of the passive filter
network in [23]–[25], a compact high frequency active current shaping network has been developed to replace
the passive filter, and three ac switches are employed to take place of the bulky low frequency transformer [26].
In this paper, we propose a dc link APF for three-phase diode rectifiers. Although the dc link filter for a
single phase rectifier has been studied [28], [29], extension to the three phase is not straightforward and requires
new topology and control strategy. The dc link APF studied in this paper differs from the active dc filter in
HVDC [30] in terms of the connection structure and the function. The active dc filter is connected at the bottom
of an existing passive dc filter at the rectifier station. It is mainly used to reduce the dc current ripples and to
increase the dynamic response of the dc current ripple filter [30]. The proposed topology consists of two seriesconnected bidirectional boost converters, which function as harmonic current generators to compensate for the
phase currents to be in phase with the corresponding line voltages, not just triple current injection as in [21]–
[27]. Moreover, three line-frequency ac switches decouple the three phase circuit to the two-phase circuit to
simplify the control effort. Compensation performance of this three-phase dc link APF is analyzed and is
evaluated under limited switching frequency and limited current loop bandwidth. The current loop bandwidth
selection is presented based on the frequency domain evaluation. In addition, the voltage loop and current loop
models are developed for the control design, and switching stress is calculated and analyzed. Performance
comparison with the ac side APF and three-phase PFC is also conducted.
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II.
PROPOSED DC LINK ACTIVE POWER FILTER
Consider a three-phase diode rectifier with a dc load as shown in Fig. 1. The dc load is modeled with a
simple RL load. It can be justified even under the output capacitor filter condition in that an inductor is usually
placed in front of the capacitor to smooth the dc link current. If there is no other mechanism to improve the
input current quality of the diode rectifier, the input line currents are polluted with series harmonic components.
To alleviate the harmonic pollution, a dc link APF is proposed. This dc link APF is coupled to the ac input with
three ac switches working at line frequency and connected to the load, as shown in Fig. 1. It consists of two
series-connected bidirectional boost converters, which contain positive part components Lp, Sp1, Sp2, Cp and
negative part components Ln, Sn1, Sn2, Cn.
The operation principle of the dc link APF can be examined as the series connected dual-boost three-phase
PFC [19], [20].
Fig. 1. Schematic of proposed dc link active power filter for three-phase diode rectifier
Fig. 2. Line period division and ac switches conduction states.
Fig. 3. Equivalent circuit for the interval I.
The input line voltages are divided into six intervals, I–VI, as shown in Fig. 2. In each interval, only one ac
switch conducts. For example, in interval I, Sb conducts while Sa and Sc are off. The dc link APF is simplified to
a series-conducted bidirectional boost converter. Fig. 3 shows the equivalent circuit of the dc link APF for
interval I.
The dc link currents have correspondence with the ac input currents. Distinct interval produces different
correspondence. For example, the currents ip, im, in are ia, ib, and ic, respectively, in interval I. The input voltage
vpm of the positive boost converter is equal to vab, so is the voltage vmn of the negative boost converter equal to
vbc. The dc load is modeled with a constant dc current source.
If the line current ix can be controlled in proportion to the corresponding line voltage in each interval such
as
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where x = {p, m, n}, vp, vm, vn are the voltages between node p, m, n and node o in Fig. 1, Re is the equivalent
phase resistance. Then, the line currents also hold the same proportionality to the corresponding line voltages
[19], [20],1 i.e.,
where y = {a, b, c}. vp and vn are the positive and negative envelopes of the line voltages, and vm is the
complement voltage
In the steady state, the dc voltages of the capacitors are assumed to be equal
and their dc component is Vc. Due to the equivalent series connected boost converter topology, the
complementary high frequency switches Sp1, Sp2 and Sn1, Sn2 can be controlled to regulate the dc rail current ip
and in, respectively, to satisfy the relationship (1).
When Sp1 is on and Sp2 is off, the voltage across the inductor Lp is positive, i.e.,
Then the inductor current iLp will increase. When Sp1 is off and Sp2 is on, the voltage across Lp is negative
The inductor current iLp decreases. This current regulation process also can be applied to the negative
part boost topology.
Typical operation waveforms of the dc link APF rectifier are shown in Fig. 4 under the symmetrical
sinusoidal input condition. The voltages and currents are drawn with p.u. values. The voltage base is the
amplitude value of the phase voltage, and the current base is the dc load current which is assumed to be constant
dc with 50 Hz line frequency. The top panel illustrates the voltages vpm and vnm of the positive part and negative
part boost converter, respectively. The middle panel displays the current waveforms in the positive boost
converter. Those in the negative part have similar waveforms and are not shown. The bottom panel exhibits the
input phase voltage and the line current of phase a. From Fourier analysis of the line current of a three-phase
diode rectifier with inductive load, the phase current amplitude can be obtained by
This indicates the quantitative relationship of the currents shown in the middle panel in Fig. 4. As can
be seen from Fig. 4, the current processed by the dc link APF is just part of the load current. This situation
enables the reduction of power rating, like the traditional ac side APF. CONTROL OF DC LINK APF
A. Control Structure
Average current control [31] is employed to control the dc link APF for digital implementation. The input
voltage feedforward [32] is also adopted here to eliminate the input voltage effect to the current loop. Fig. 5
shows the block diagram of the overall current control, which consists of one outer voltage loop and two inner
current loops. Vm is the amplitude of the carrier signal, which is the signal employed in the sine-triangle PWM
to generate duty ratios.
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Fig.4. Typical operation waveforms of the proposed dc link APF.
The sum of the voltages from the two dc capacitors is compared with a dc voltage reference Uref. The
difference is fed to the voltage loop compensator, a PI controller PI1 to obtain the equivalent phase conductance
ge. Multiplying ge to
Fig.5. Average current control with input voltage feedforward.
the respective line voltage yields the reference currents of the positive part and the negative part boost converter
The reference currents ipref and inref are compared with the sensed dc rail currents ip and in, respectively.
The differences are fed to the inner current loop compensators Gc, which consists of two PI controllers PI2 and
PI3. The output of the current compensator determines the duty ratios through the PWM circuits. dp and dn are,
respectively, the duty ratios of the switches Sp1 and Sn1.Moreover, the duty ratios of switches Sp2 and Sn2 are (1 −
dp) and (1 − dn), respectively. The dashed line indicates the input voltage feedforward that eliminates the input
voltage coupling effect.
B. Voltage Loop Model
As in the conventional cascaded loop control, the bandwidth of the outer voltage loop is much smaller than
that of the inner current loop. Hence, dynamics of the current loop (e.g., inductor current) can be ignored when
modeling the voltage loop. Double averaging method [33] is applied to obtain a simple first-order power stage
voltage model with small signal linearization. From Fig. 3 and according to power balance, we have
where vcp and vcn are voltage across the capacitors Cp and Cn, respectively. All the time variables in (12)
represent the values averaged in one switching period. Averaging (12) for one third of the line period yields
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where Vp is the amplitude of the phase voltage, and C is the capacitance under symmetrical conditions, Cp = Cn
= C. Consider the perturbation on ge and vcp + vcn, and neglect the perturbation of Iload, we obtain the transfer
function
The voltage loop model is shown in Fig. 6, in which Hv(s) is the voltage sensing scale for practical
implementation. Gv(s) is the voltage compensator transfer function, represented by a traditional PI controller.
C. Current Loop Model
In each interval shown in Fig. 2, the equivalent circuit in Fig. 3 has symmetric structure. Thus, the current
loop can be analyzed in either the positive part or the negative part boost converter. The positive part is selected
here. When analyzing the fast current loop, the voltage dynamics can be approximated by a simple constant dc
voltage source. Then, the output of the voltage loop is treated as a constant admittance Ge. This shows that the
inductor current response is coupled with the input voltage. Adding the feedforward part to the current loop, the
inductor current becomes
The input voltage coupling is eliminated through the voltage feedforward.
Control design is straightforward because both the voltage model and the current model are simple
first-order models. The simple PI controller can be tuned to meet the control objectives [35]. The main concern
becomes the determination of the frequency bandwidth of the voltage loop and the current loop. Since each loop
has its own control target, the voltage loop bandwidth should be set smaller than the lowest order voltage ripple
in the dc bus voltage. In addition, the current loop bandwidth is required to be as high as possible to improve the
current compensation performance. Generally, the current loop bandwidth is limited to 1/5 to 1/10 of the
switching frequency [31].
III.
COMPENSATION PERFORMANCE EVALUATION
This section describes the relationship between the compensation performance and the current loop
bandwidth of the proposed dc link APF and evaluates the compensation performances of the dc link APF and
the traditional ac side APF. Both APFs have the following characteristics on compensation performance
1) If the current harmonic components in the line current could be neglected with infinite current loop
bandwidth, then the THD of the line current is assumed zero for the dc link and the ac side APF.
2) For finite current loop bandwidth, only the frequency components with harmonic orders smaller than the
bandwidth will be compensated.
3) The switching frequency related current ripples are ignored because these harmonics are easy to be filtered
out and usually are much higher than the harmonic order specified by the standards.
The line current in ac side APF still contains the current harmonics with frequencies higher than the
current loop bandwidth, and these high frequency components directly affect the line current THD. In contrast,
for dc link APF, the compensated harmonics with frequency less than the current loop bandwidth will appear in
the dc rail currents (ip and in) to form the desired current waveforms (as shown in the middle panel of Fig. 4).
That is, due to the finite current loop bandwidth, the compensated positive part inductor current contains only
finite number of harmonics and can be expressed as
where values of n are the integer multiples of 3 and ω is the fundamental frequency. N is the largest harmonic
order of which the frequency is smaller than the current loop bandwidth. The relationship between the harmonic
components in the dc rail currents ip, in and the ac line current will be developed below. This relationship will be
applied to quantify the bandwidth effect for compensation performance on dc link APF.
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Assume the line voltage has symmetrical sinusoidal waveform.
T is the line period. Then, the line current can be expressed in terms of the dc rail currents and the switch
function
Under symmetrical conditions, the dc rail currents have the following relationship:
Define a new switch function
Substituting (20) and (21) into (18) yields
The line current harmonic components can be calculated via the frequency components of ip(t) and S(t)
by the convolution methods.
Ideally, ip(t) is periodic with period T/3. Thus, in one period, ip(t) has the following expression
Its Fourier series expansion is
Where
and values of n are multiples of 3. The switch function S(t) can be expressed with harmonic decomposition
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Values of n that are multiples of 3 cause Sn to become zero. Thus, no multiples of a third harmonic may exist in
S(t). From the property of Fourier expansion for periodic functions, we have
Substituting (23)–(28) into (22) yields the line current
The coefficient Ch is
where values of l are multiples of 3, h is odd and h ≠ l. l is the harmonic order of ip(t). When the current loop
bandwidth is infinite, both l and h extend to infinity. Suppose that the current loop bandwidth is limited to N
times of the fundamental line frequency, the lower bound and upper bound in the summation of (31) becomes
−N and N, respectively. It follows from (30) that we obtain the relationship between the harmonic components
of the line current and that of the dc rail currents. Next, we evaluate the line current performance under specific
current loop bandwidth using the relationship (30) and (31).
Ideally, the line current can be compensated by the dc link APF to harmonic free with infinite
switching frequency. However, this is not the case in reality. Suppose that the current loop bandwidth is limited
to the N times of the fundamental line frequency. Since the harmonic standard only considers the harmonics up
to the 50th order, the line current THDdc by the dc link APF can be calculated as
IV.
SIMULATION RESULTS
A. Simulation Studies
Simulation results of the steady-state response with inductive load are shown in Fig. 6. Fig. 10(a) and (b)
show the source current waveforms and the load voltage and current waveforms when the dc link APF is OFF
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and ON, respectively. Fig. 6(c) shows the current of the positive part boost converter. The dc bus voltage
waveforms are shown in Fig. 6(d). THD of the source current was 30.84% without compensation and was
reduced to 3.34% with compensation of the proposed dc link APF. It is observed from Fig. 6(a) and (b) that both
the load voltage waveform and current waveform are nearly the same with or without the dc link APF. This is in
agreement with the performance of the shunt ac APF; that is, APF does not affect the performance of load
voltage and load current. The dc component of the load current is 25.66 A, and the peak-peak 300 Hz current
ripple is about 0.3 A. This dc value is very close to the dc component of the load, 25.72 A, of an ideal three
phase diode rectifier loaded by a pure resistor. It is observed from Fig. 6(c) that the dc component of ip is 23.40
A, which is also the same as the calculated value. The dc voltage sum of the split capacitors is 1100 V, which is
equal to the reference voltage. The peak-peak voltage ripple of each capacitor is about 7 V with 150 Hz
frequency, but the peak-peak ripple of the sum of these two capacitors is reduced to about 3 V and the frequency
is 300 Hz. This is due to the nearly 180◦ phase shift between vcp and vcn, which leads to harmonic cancellation.
Hence, we select (vcp + vcn) as the feedback signal in the voltage loop of Fig. 6 because of the low ripple factor.
The transient response under dc load resistor change and source voltage change is shown in Fig. 11. Fig.
11(a) displays the response when the dc load resistor changes from 20 Ω to 40 Ω at the time instance of 0.4 s
and changed back to 20 Ω at0.5 s. Fig. 11(b) displays the response under the circumstance that source voltage
has a 30% voltage drop at 0.4 s and return to the rated value at 0.5 s. These results of load change and source
voltage change examine the transient performance of the control design discussed in Section III.
Fig.6. Simulated transient responses with inductive load. (a) Load change from 20 Ω to 40 Ω at 0.4s and changed back to 20 Ω at 0.5 s. (b)
Source voltage drop 30% at 0.4 s and return to the rated value at 0.5 s.
The voltage loop bandwidth affects the dynamic performance. The transient response can be improved
by setting the voltage loop bandwidth higher, as illustrated in Fig. 12. In the simulations, the dc load resistor
changes from 20 Ω to 40 Ω at the time instance of 0.3 s and changes back to 20 Ω at 0.5 s. The results shown in
Fig. 12(a) and (b) are for the 15 Hz and the 60 Hz voltage loop bandwidth, respectively. It is observed from Fig.
12(a) that the overshoot of dc voltage is about 90 V and the settling time is about 150ms. On the other hand, the
overshoot is about 20 V, and the settling time is about 20 ms for the 60 Hz voltage loop bandwidth. This
demonstrates that the dynamical performance can be improved with higher voltage loop bandwidth.
The diode rectifier with a capacitive load was also investigated. The results are presented in Fig. 13.
The line current after compensation is 8.1%, which is much higher than that in the inductive condition. The
reason is that the shunt APF is more suitable for compensating inductive load and current type harmonic source,
but not for the capacitive load or voltage type harmonic source [39].
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VII Simulation model and Results
Fig.7.Simulation model for proposed circuit
Fig. 8. Steadystate response of active power filter- Source voltage(Vsa), source current (Isa, Isb, Isc), Load voltage (Vload), and Load current
(Iload)
Fig. 9. Transient response with inductive load- Source voltage (Vsabc), load current (Iload) and source current (Isabc)
VIII.
CONCLUSION
A novel harmonic reduction method, which uses the dc link APF for three-phase diode rectifier, has been
presented. Average current control with input voltage feedforward is applied to the control of this circuit.
Voltage loop and current loop models have been developed for control design. Evaluation on the relationship
between compensation performance and current loop bandwidth has also been presented. The results show that,
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under the same current loop bandwidth, the dc link APF performs better than the ac side APF. Even though the
compensation performance of the dc link APF is inferior to that of the three-phase PFC, it is still well above the
requirements set by the IEC 61000-3-2 Class A standard [40]. Results of switching stress comparison reveal that
the dc link APF has the potential of high efficiency and better silicon cost reduction ability than the six-switch
PFC. Therefore, the dc link APF and the developed control scheme offer a high performance low cost
alternative for the harmonic elimination of three-phase diode rectifier. A major limitation of the proposed circuit
is that, if the galvanic isolation is required, the isolation transformer is expensive and bulky due to the dc
component in voltage and current processed by the dc link APF.
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AUTHORS
Ms.P.Laxmi pursuing his M.Tech in Power Electronics at SVS Engineering College and B.Tech in Electrical
& Electronics Engineering. His research interest includes Power Systems, power electronics and Drives.
(E-mail: laxminov26@gmail.com)
Ms.M.Prashanthi is with the department of Electrical and Electronics Engineering working as Assistant.Prof
at SVS Engineering College, Warangal, Telengana State. India.
His research interest includes Power Electronics and power system.
(E-mail: shanthi_matoori@yahoo.com )
Mr. D.Kumaraswamy is with the department of Electrical and Electronics Engineering working as Assoc.Prof
& Head at SVS Engineering College, Warangal, Telengana State. India.
His research interest includes Power Electronics, Distributed Generation and Renewable Energy Sources.
(E-mail: dkswamy1213@gmail.com )
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