Allegro DFI
Design Flow Integration
“Bringing EM and Signal
Integrity simulation technology
to the PCB designer.”
Allegro Design Flow Integration (DFI)
June 27,2007
Cadence Allegro – need for circuit and EM
verification
• Allegro is the Cadence platform for silicon-
package-board co-design:
– Widely adopted for board design
– Enterprise tool capable of handling complex pcb’s
• PCB’s are becoming increasingly complex:
–
–
–
–
–
High speed digital traces at gigahertz speed (routers)
Integration of digital and analog RF (wireless devices)
Complex board and via stackups
Decreasing board size
Signal Integrity problems
• EM and circuit analysis and verification of
specific parts of the layout is needed
Allegro Design Flow Integration (DFI)
June 27,2007
-1-
Why Digital Designer needs Electromagnetic
Simulator?
• Convenient and inexpensive way to evaluate arbitrary structure
performance.
• What if analysis is possible with inexpensive iterations
• Expands varieties and range of analytical models
• Overcome limitation of analytical models
• Solve design issues which are not discovered with current PCB SI tools.
Two personas:
Signal integrity gurus (who creates design rule)
• Requires simulation tool flexibility and power
• Accurate EM simulation
• Requirement to model electrically small structures
Post layout design verification engineer
• Requires higher capacity EM solver like Momentum RF
• Approximate EM solutions in some cases
Allegro Design Flow Integration (DFI)
June 27,2007
Allegro DFI, access to circuit and EM simulation
• Allegro DFI introduced in ADS2006 Update 1
• Add-on to Cadence Allegro
• Allegro pcb designer can select one or more
layout nets and its essential graphics and physical
characteristics, and package them for import in
ADS.
• Seamless transfer dramatically reduces the
time to transfer parts of the Allegro layout to the
ADS simulation environment.
• In ADS users have access to:
– Class-leading frequency- and time-domain
simulation engines, and EM engines
– Complete set of tools and models to analyze
extensively their circuit.
• In this way, Signal Integrity problems can be
detected and solved early in the design phase.
• The Allegro Design Flow Integration is free of
charge to all users of Momentum in ADS 2006
Update 1.
Allegro Design Flow Integration (DFI)
June 27,2007
-2-
Process before Allegro DFI
• Before the introduction of Allegro DFI, the pcb
designer had to export the complete layout in
gerber file format.
Allegro PCB Design Environment
• On the ADS side, a gerber import was needed
together with a manual process to delete all the
unwanted traces, vias, other objects, remove
unnecessary layers, setup momentum substrate
information, reduce layout complexity,…
Advanced Design System
• This manual process could easily take up to a few
hours before a momentum simulation could be set
up. When the Allegro layout was modified the
iterative process had to be done all over again.
• Allegro DFI reduces dramatically the time to
transfer the Allegro nets of interest in a matter
of minutes.
Gerber export
Gerber import
Delete unwanted objects, layers
Reduce layout complexity
Customer quote:
“Using Allegro DFI we were able
to reduce the export and setup
time from 18h to 15 min. !”
Setup momentum substrate
Run EM simulation
Allegro Design Flow Integration (DFI)
June 27,2007
Design Flow concept Allegro DFI - ADS
Advanced Design System design
and simulation environment
Allegro PCB Design Environment
Selected parts
(traces and vias)
of the layout
including the
physical board
characteristics
are packaged and
are ready for
import in ADS.
Allegro Design Flow Integration (DFI)
June 27,2007
-3-
Allegro DFI installation
• Allegro DFI works with the Allegro PCB editor is part of the installation package
ADS2006 Update 1. This integration link comes free of charge!
• When installed the user has a new menu called “[Export to ADS]” in the Allegro PCB
design environment.
Allegro Design Flow Integration (DFI)
June 27,2007
Allegro PCI adaptor card example - Layout
• PCI adaptor card designed in Cadence Allegro.
- 6 layer FR4 board.
- Positive layers for signal layers.
Negative ground plane layers.
- Through hole and blind vias
Allegro Layout Cross-Section
Allegro Layout Design
Environment
High density board with high
speed digital traces like clock
signals and differential traces
Allegro Design Flow Integration (DFI)
June 27,2007
-4-
Allegro PCI adaptor card example - Schematic
• Differential pair
traces requiring
special SI attention
Allegro Schematic
Design Environment
Allegro Design Flow Integration (DFI)
June 27,2007
Design Flow overview Allegro DFI - EXPORT
Allegro Design
Environment
Identify traces for further SI analysis
•The designer identifies traces in the
Allegro PCB editor he wants to
transfer to the ADS environment for
further simulation and modeling.
1. Setup
•A number of predefined of Export
Settings are selectable. This enables
geometry conversion of via and pads.
E.g. round to square. In this way
more complex via and trace
structures can simulated in the ADS
EM simulator. Users can easily
create their own conversion rules.
Selected traces, nets for
export
2.1Select Traces > Trace Select tab
•Traces can be selected by either
selecting them from the Selectable
Net Pool or by picking, clicking on the
traces directly in the layout.
Traffic lights turn green
when tabs are “Ready”…
•In this way the designer can select
the traces, signal nets he wants to
export as signal traces or as ground
traces during the next export step.
Allegro Design Flow Integration (DFI)
June 27,2007
-5-
Design Flow overview Allegro DFI – EXPORT, cont.
2.2 Select Traces > Layer Select tab
•The selections in this tab enables
which layers will be exported to ADS.
•By default all layers on which the
selected objects are placed on will be
selected for export.
Traces in the layout get
highlighted when selecting
them from the Signal Nets pool
Infinite Ground Top/Bottom layer
Infinite groundplane top
•To limit the board stack by adding
infinite ground planes, choose the
layer from the list in the infinite
ground top or bottom dropdown
boxes. The metallization patterns on
those layers will be replaced by a
solid metal layer. The layers above
Top or below Bottom infinite ground
selections will not be exported to
ADS.
Not selected
layer
Infinite groundplane bottom
Through hole via
Blind and buried vias through
infinite grounds follow same rule:
If on ground net, connect; if not
stop on previous layer
Allegro Design Flow Integration (DFI)
June 27,2007
Design Flow overview Allegro DFI – EXPORT, cont.
2.3 Select Traces > Cookie cutter tab
•The cookie cutter limits the exported
area by using an expansion region
around the selected traces. This
expansion region can be modified.
The cookie cutter only cuts metal on
the RF ground nets. It does not cut
metal on the signal nets.
Cookie cutter selection
area is visible. Vertices and
sides of it can be modified.
3.1 Export > Export All / Selected
Exported files in Allegro project directory:
•The final step in Allegro is to save
the selected design in EGS Archive
format for export. Either the selected
traces can be exported or still the
complete board.
<boardname>.ads
[log file]
<boardname>_a
[exported EGS file]
<boardname>.slm
[Mom .slm substrate file]
<boardname>_a.explog
[log file]
Allegro Design Flow Integration (DFI)
June 27,2007
-6-
Design Flow overview Allegro DFI – IMPORT
ADS Design
and Simulation
Environment
New Allegro Tools
menu available by
installing the
Allegro import
design kit .
1. Import Allegro layout
•The traces exported through the
Allegro DFI interface can now be
imported in ADS layout. Use either :
- the Allegro import design kit
available on the Knowledge Center
(example ID 270512, version ≥ 1.4)
(preferred) or
- the standard EGS Archive file
import and momentum substrate
import.
•By importing the <boardname>.ads
file following actions are done
automatically:
•
Layers and selected traces are
automatically added to the ADS
layer list during EGS import.
• The momentum substrate file is
automatically loaded.
•Note the pad and via geometry
conversion to squares because of
the selected Allegro DFI export
setting.
•Allegro positive etch layers mapped
as strip layer, negative etch layers
mapped as slot layer.
Dielectric layer stackup and layers mapping (incl.
via’s) automatically defined saving time and avoiding
translation errors !
Allegro Design Flow Integration (DFI)
June 27,2007
Design Flow overview Allegro DFI – IMPORT, cont.
2. Setup Momentum Ports
•Place the ports in layout on the
different connection points to run an
EM simulation on. Use the port editor
to define the ports all as internal
ports.
•When not placing ground reference
ports, Momentum will place the
internal ground ports automatically
during the simulation process.
3. Momentum > Mesh
•Setup the Momentum Mesh
frequency (highest simulation
frequency of interest)
Allegro Design Flow Integration (DFI)
June 27,2007
-7-
Design Flow overview Allegro DFI – IMPORT, cont.
4. Momentum > Simulation
•Setup the Momentum Simulation
parameters like Adaptive Frequency
Start and Stop Simulation Frequency.
•Click on the Simulate button to start
the Momentum EM simulation.
•In some specific cases the slot layer
mapping for Allegro negative layers
may lead to incorrect simulation
results. In this case, convert the
infinite slot layer to a finite strip layer
using the boolean operation and
adjust the momentum substrate
definition.
Allegro Design Flow Integration (DFI)
June 27,2007
Design Flow overview Allegro DFI – IMPORT, cont.
6. Create EM-cosimulation
component
•By creating an EM-cosimulation
component and placing this
component in the ADS schematic
simulation environment, SI simulation
can be created using the ADS classleading time –and frequency domain
simulators and models.
From this point, different circuit EMco-simulation simulations can be
setup
Allegro Design Flow Integration (DFI)
June 27,2007
-8-
Allegro DFI : NEW functionality in ADS2006 Update 2
1. Automatic port placement
•An extra ports tab is added to
enable automatic port placement
on the Allegro signal traces. On
the ADS side the ports will be
imported and placed
appropriately together with the
selected traces .
•Saves significant time. No need
anymore to place ports manually
once the selected traces are
imported in ADS !
Port symbol in Allegro
layout
Overview of ports placed on
the Allegro signal nets.
Allegro Design Flow Integration (DFI)
June 27,2007
Allegro DFI : NEW functionality in ADS2006 Update 2
1. Autoport placement –
ADS import
When importing the
<board>.ads file name
through the Allegro import
menu the ports are now
automatically placed on the
ADS layout.
Momentum Ports
Allegro Design Flow Integration (DFI)
June 27,2007
-9-
Allegro DFI : upcoming functionality in ADS2006 Update 2
2. More flexible export of files
•Export/Export Selected menu
pick creates output files in same
directory as board file
•Export/Export Selected As
creates the output files under
the name and directory the
users wants
Allegro Design Flow Integration (DFI)
June 27,2007
Allegro DFI:
“Bringing EM and Signal Integrity simulation
technology to the PCB designer.”
In Minutes, not Hours…
Allegro PCB Design Environment
Advanced Design System
Gerber export
Gerber import
…..
Available now, at no extra cost,
in ADS2006 Update 1!
Allegro Design Flow Integration (DFI)
June 27,2007
-10-
Differential impedance simulation example
An S-parameter simulation, optimization is setup
to simulate the differential impedance of a single
differential trace including the through hole via’s
6 Layer Multilayer Substrate equivalent
to the momentum substrate setup
Differential impedance
1GHz
2GHz
3GHz
4GHz
5GHz
83Ω
83Ω
83Ω
83Ω
83Ω
Sheet conductor EM 105Ω
simulation
110Ω
123Ω
165Ω
200Ω
Thick conductor
EM simulation
88Ω
95Ω
124Ω
199Ω
Multilayer Coupled
line
85Ω
TLINES-Multilayer
Coupled line
At low frequencies (1-2 GHz) the differential impedance
of the thick conductor EM simulation matches the
multilayer coupled line whereby the sheet conductor EM
simulation is more off.
¾ Thick conductor modeling is needed
¾ Differential trace was routed to be a 100Ω trace
whereby in reality it’s approx. a 85 Ohm trace. This
mismatch could have effect on the differential trace
behavior.
•At higher frequencies (3-5GHz) the differential
impedance of both the thick and sheet conductor EM
simulation are way higher than the Multilayer coupled line
Single differential trace
including through hole vias
¾ Influence of through hole via ?
Allegro Design Flow Integration (DFI)
June 27,2007
Single differential trace without via
An S-parameter simulation is setup to simulate
the transmission of the multilayer coupled line
and the momentum LC coupled line. The
through hole via is not present in the momentum
LC.
ML2CTL_C
MOM LC
ML2CTL_C
MOM LC
The transmission result of the multilayer coupled
line is close to the momentum LC component.
¾ Through hole via is most likely responsible for
the discrepancy in differential impedance.
¾ Multilayer library gives very good match with
EM simulation based models.
Allegro Design Flow Integration (DFI)
June 27,2007
-11-
Single differential trace including via’s
A S-parameter simulation is setup to simulate
the transmission of the momentum LC coupled
line. The through hole via is present in the
momentum LC.
No through
hole via (see
previous slide)
Including
through hole
vias
Through hole via’s shorting
gnd plane layers
Through hole vias
Simulated with ADS2006 Update1
The combination of through hole vias and the
differential trace is introducing a resonance in the
transmission.
Allegro Design Flow Integration (DFI)
June 27,2007
Single via
A S-parameter simulation is setup to simulate
the transmission of an individual through hole
via.
The individual via simulation does not show any
particular resonance.
Simulated with ADS2006 Update1
Allegro Design Flow Integration (DFI)
June 27,2007
-12-
Single differential trace with individual via LC’s
Via equivalent circuit model
The combination is made
between the individual via LC’s
and the differential trace LC.
Note that the coupling between
the via LC and differential trace
LC will not be taken in account.
Individual via LC’s
•The combination of through hole vias and the differential trace is introducing a resonance in the
transmission.
•The resonance frequency is different than the integrated via&differential trace LC model. This is because
the latter takes the coupling between via and differential trace in account.
•The resonance is causing the differential impedance to be much higher than expected. Using this
via&differential trace combination at high data rates will cause signal degradation
Allegro Design Flow Integration (DFI)
June 27,2007
Allegro DFI:
“Bringing EM and Signal Integrity simulation
technology to the PCB designer.”
In Minutes, not Hours…
Allegro PCB Design Environment
Advanced Design System
Gerber export
Gerber import
…..
Available now, at no extra cost,
in ADS2006 Update 1!
Allegro Design Flow Integration (DFI)
June 27,2007
-13-
‫ڕ‬۶ലֆࣨऱPA (Power Amplifier)๻ૠ‫إ‬ᒔ
ऱฝཬࠩߓอሽሁࣨ
Agilent Taiwan EEsof Application Engineer
Lin Ming Chih
Page 1
QUESTION: Why do the amplifiers
require external matching?
• ANSWER: External matching optimizes the overall device
performance. Support components (capacitors and inductors)
Q-values are much higher in off-chip form and thereby provide
low loss, highly tuned matching circuits. External matching also
provides the user with flexibility. Tradeoffs between output
power, power-added efficiency (PAE), frequency response, and
gain can be made via an external matching network to support
the critical requirements of your application.
Page 2
-1-
ߓอՠ࿓ஃࢬሖࠩऱംᠲ
• ๺‫ߓڍ‬อՠ࿓ஃ‫ڇ‬๻ૠTx (Transmitter)ऱழଢൄൄᄎሖࠩ
ԫଡംᠲΔցٙᐗࢬ༼ࠎऱPA‫ڇ‬ֆࣨऱ।෼ຟฤ‫ٽ‬๵௑
஼ऱ૞‫ޣ‬Δ‫܀‬ਢԫ‫؟‬ലPAฝཬࠩ۞ա๻ૠऱऱߓอሽሁ
ࣨՂ૿հ৵Δ૞լਢᏺ墿᧢஁Δ༉ਢய෷૾‫܅‬Ζࣔࣔࠌ
‫ش‬ऱሿٙຟऎ‫ش‬ֆࣨऱ๻ૠΔ੡չᏖࢤ౨ᄎ஁ຍᏖ‫?ڍ‬
• ࣍ਢ੡Աലࢤ౨ᓳ‫ړ‬Δՠ࿓ஃլឰऱང֐಻ցٙΔլឰ
ऱቫᇢᙑᎄΔ၄Ա԰ׄԲॡհԺ‫ױ‬౨‫אױ‬ᓳࠩԫଡঠൎ
‫אױ‬൷࠹ऱࢤ౨ΖՀԫ‫ڻ‬ऱ๻ૠԾ‫ؘ‬ႊૹᄅࠐመ
Page 3
Part1:ᄗ࢚տฯ
• PAऱ।෼ፖPAऱᙁ‫נ‬ጤࢬ઎ࠩऱ૤ሉ
‫ڶ‬ઌᅝՕऱᣂএΖPAऱᏺ墿Εய෷Ε
ᒵࢤ৫ຟᄎᙟ૤ሉ‫᧢ޏ‬Ζԫ౳PAࠎᚨ
೸Ζ‫ࠎ༼ڇ‬PAऱழଢຟᄎ༼ࠎ່ࠋऱ
૤ሉՕ՛Δ૤ሉॴ‫ݼ‬ຏൄᑑ‫ق‬੡X+jY
Ohm(ᓤᑇ) Δࠏ‫ڕ‬47.665-46.410j
Ohm@1850MHz (ᖙ‫܂‬᙮෷)
૤ሉ
• ‫ߓڼڂ‬อՠ࿓ஃ‫ڇ‬ฝཬPAࠩ۞աऱठ
՗ऱழଢΔ່ૹ૞ऱঁਢૹ෼૤ሉΔ
• ່ࠋ૤ሉຏൄਢຘመloadpull meterၦྒྷ
൓ࠩΔᑑ‫ڇق‬Smith ChartՂ૿
Page 4
-2-
Loadpull meter+ၦྒྷߓอ
Page 5
૤ሉՕ՛ኙPAࢤ౨ऱᐙ᥼
‫࣠ڕ‬૤ሉ~47.601-j16.487 Ohm
ᙁ‫ໍנ‬Հ31.15dbm
‫࢓ޢ‬؆ԫഎᙁ‫נ‬ൾ~0.5dB
່ࠋ૤ሉ~47.665-j46.410 Ohm
ᙁ‫נ‬31.585dbm
Page 6
-3-
‫ڕ‬۶ૹ෼૤ሉ
• ߓอՠ࿓ஃ‫܉ڇ‬ᒵழৰᣄቝֆࣨԫᑌঅఎຍᏖՕऱ़ၴ࿯PAΔۖ‫׊‬
ࠌ‫ش‬ऱࣨ՗ഔᦤՈլᄎᇿֆࣨઌ‫ٵ‬Δ‫ڕڼڂ‬۶ૹ෼૤ሉঁ᧢‫ګ‬ԫଡ
ཟ֫ऱംᠲ
• ৰ‫ߓڍ‬อՠ࿓ஃ‫א‬੡ਊᅃֆठऱցٙឭ࣋‫ڇ‬PAऱᙁ‫נ‬ጤঁਢૹ෼ֆ
ࣨऱ૤ሉΔࠡኔࠀլ‫إ‬ᒔΔ‫ړڶ‬༓ଡ଺‫ڂ‬ຟᄎᐙ᥼ࠩ૤ሉ:
• Հԫ్ሽሁऱᙁԵॴ‫ݼ‬
• ຑ൷PAፖՀԫ్ሽሁऱႚᙁᒵ
• ֐಻ሽሁፖpadऱ‫܉‬ᒵ
• ൷Հࠐ‫ݺ‬ଚലᄎ։ܑಘᓵຍԿႈ଺‫ڂ‬ኙ૤ሉऱᐙ᥼
Page 7
ࠢীऱPAֆࣨ๻ૠ
‫װ‬ᓀ‫ٽ‬ሽ୲ᕣ‫ױ‬౨լ
ፖ֐಻ሽሁ٥‫ش‬
Ground island
ႚᙁᒵ࿨ዌ
50Ohm௽ࢤॴ‫ݼ‬
PAऱ૤ሉ
֐಻ሽሁΔല50Ohm
᠏ฝ່ࠩࠋ૤ሉ
Հԫ్ሽሁ
50OhmᙁԵॴ‫ݼ‬
Page 8
-4-
ߓอሽሁࣨᅝխऱ‫ݝ‬ຝPA‫܉‬ᒵ
Page 9
Հԫ్ցٙऱᙁԵॴ‫ݼ‬
• ֆࣨԫ౳੡Աֱঁຑ൷Ꮪᕴ‫ྒྷ܂‬ᇢ֗᧭ᢞΔPAऱՀԫ్ցٙຏൄਢ
ࡳᆠ੡50OhmΖፖᏚᕴऱᙁԵॴ‫ݼ‬ઌ‫ٵ‬
• ‫܀‬ਢߓอࣨ՗ՂPAऱՀԫ్ሽሁ‫ױ‬౨ਢswitchΕduplexerࢨਢ֚ᒵΔ
Հԫ్ցٙऱॴ‫ڂݼ‬੡፹࿓ᎄ஁‫ױ‬౨ࠀլਢ壄ᒔऱ50Ohm
?50Ohm
Matching
Circuit
Page 10
-5-
ຑ൷PAፖՀԫ్ሽሁऱႚᙁᒵ
• ႚᙁᒵऱ‫܉‬ᒵਢ૞ᨃAរࠩ
Bរऱॴ‫ݼ‬ፂ਍‫ڇ‬50OhmΔ
‫ڼڂ‬ᣤ௑ऱ൳ࠫႚᙁᒵॴ‫ݼ‬
ॺൄૹ૞
• ຍ㠪ֆࣨࠌ‫ش‬ऱਢCPWG
(coplanar waveguide with
ground)ਮዌΔႚᙁᒵऱؐ‫׳‬
ࠟೡፖՀֱຟਢGNDΔࠟೡ
८᥆യႃऱviaᒔঅؐ‫ࠟ׳‬ೡ
ፖՀֱ८᥆ሽ‫ۯ‬੡ሿΖ
A
B
– signal
via
via
– ground
Page 11
֐಻ሽሁ
• ֐಻ሽሁऱ‫ؾ‬ऱਢຘመਢᅝሽ୲ፖሽტऱิ‫ٽ‬ല
50Ohm᠏ฝ່ࠩࠋ૤ሉΖ
• პं෻ᓵ‫ݺ္ܫ‬ଚ֐಻ሽሁᅝխሽ୲ଖࢨሽტଖ
ऱՕ՛֗‫ۯ‬ᆜຟᄎᐙ᥼ࠩॴ‫಻֐ݼ‬Ζ
• ֐಻ሽሁऱpad๻ૠፖ൷‫چ‬๻ૠข‫س‬ऱബ‫س‬யᚨ
Ոᄎᐙ᥼່ࠩึऱॴ‫಻֐ݼ‬
Page 12
-6-
ֆࣨ֐಻ሽሁ,PIী֐಻
@849MHz,@1.85GHz
Matching Network
Antenna
Page 13
PAऱPout Contour;
દ‫ۥ‬ऱਢ849MHzΔ៴‫ۥ‬ऱਢ1850MHz
Page 14
-7-
ലֆࣨऱሿٙฝࠩߓอࣨՂ૿
Page 15
PCBബ‫س‬யᚨࣔ᧩ᐙ᥼૤ሉॴ‫ݼ‬
viaऱബ‫س‬ሽტፖpadऱബ‫س‬ሽ୲ທ‫ݼॴګ‬ೣฝ
଺ࡨ๻ૠ֐಻
PCBທ‫ګ‬ऱബ‫س‬யᚨ
Δ᙮෷။೏။ࣔ᧩
Page 16
-8-
෻უሽ୲ፖటኔሽ୲௽ࢤֺለ
• Կឍຟਢᑑ‫ق‬੡0.5pFऱሽ୲
• દ‫ۥ‬:෻უሽ୲,
C@5GHz=0.5p
imag(Y(3,3))/(2*PI*freq)
imag(Y(2,2))/(2*PI*freq)
imag(Y(1,1))/(2*PI*freq)
• ෻უሽ୲ऱ୲ଖլᙟ᙮෷ۖ᧢Δట
ኔሽ୲୲ଖᙟ᙮෷ᏺ‫ۖף‬ᏺ‫ף‬Ζ‫ٵ‬
ԫଡ୲ଖլ‫ࠎٵ‬ᚨ೸ࢬ༼ࠎऱሽ୲
᧢֏‫ڴ‬ᒵՈլጐઌ‫ٵ‬Ζԫ౳ֆࣨຟ
ᄎ৬ᤜࠌ‫ش‬ਬԫଡᐗྨऱሽ୲༉ਢ
ຍଡ଺‫ڂ‬Ζ‫ߓ࣠ڕ‬อՠ࿓ஃუ૞‫ޓ‬
ང‫ה‬ᐗऱ๯೯ցٙΔ‫ؘ‬ႊ૞՛֨
• ៴‫ۥ‬:Murata GRH708 C@5GHs=1.252p
• ృ‫ۥ‬:Microelectronics MPR3,
C@5GHz=0.7378p
2.50E-12
m1
freq=5.000GHz
imag(Y(2,2))/(2*PI*freq)=1.252E-12
m2
freq=5.000GHz
imag(Y(3,3))/(2*PI*freq)=7.378E-13
m3
freq=5.000GHz
imag(Y(1,1))/(2*PI*freq)=5.000E-13
2.25E-12
2.00E-12
1.75E-12
1.50E-12
1.25E-12
m1
m2
m3
1.00E-12
7.50E-13
5.00E-13
2.50E-13
0.00
0
2
4
6
8
10
freq, GHz
Page 17
‫ٵ‬ԫឍሽ୲࣋‫ڇ‬լ‫ٵ‬দ৫ऱࣨ՗
• ༉ጩਢ‫ٵ‬ԫឍሽ୲(ࢨࠡ‫ה‬๯
೯ցٙ)࣋‫ڇ‬լ‫ٵ‬দ৫/տሽ
ൄᑇऱࣨ՗Ղ௽ࢤຟᄎ‫ޏ‬
᧢Δ‫ڼڂ‬ցٙ೸ࢬ༼ࠎऱց
ٙᑓীՈլԫࡳ‫إ‬ᒔΖ৬ᤜ
ࠌ‫ش‬ፖߓอሽሁԫᑌऱࣨ
‫ޗ‬Δ‫ܶץ‬দ৫ፖտሽൄᑇ‫܂‬
DUT BoardΔ۞۩ၦྒྷS೶
ᑇΖ
Modelithics Inc. ADVANCED MICROWAVE CHIP CAPACITOR
MODELS, MICROWAVE JOURNAL® from the January 2002
issue.
Page 18
-9-
๠෻ੌ࿓տฯ
• ‫׽‬૞ૹᄅ‫܉‬ᒵΔ৬ᤜ։࣫‫܉‬ᒵऱബ‫س‬யᚨࠀૹᄅ
პᓳ֐಻ሽሁ
• ႪԵ‫܉‬ᒵࠀሽ጖ᑓᚵ‫܉‬ᒵऱS೶ᑇ
• ലֆࣨ৬ᤜऱցٙS೶ᑇፖ‫܉‬ᒵऱS೶ᑇ൷‫ڇ‬ԫದૠጩ
૤ሉऱS೶ᑇ
• ‫࣠ڕ‬૤ሉऱS೶ᑇೣᠦֆࣨऱ৬ᤜଖΔૹᄅᓳᖞցٙ
ଖΔ‫ڕ‬ᝫྤऄ൓ࠩജ‫ړ‬ऱ֐಻ঞᏁ‫ە‬ᐞ‫ޓ‬ང֐಻ਮዌ
ࢨਢૹᄅ‫܉‬ᒵ
Page 19
ADS (Advanced Design System)
• ‫ڜ‬൸଩೏᙮ሽሁᑓᚵຌ᧯ADS‫אױ‬࿨‫ٽ‬PCB‫܉‬ᒵ‫֗א‬ցٙS
೶ᑇࠐᑓᚵኔᎾऱॴ‫ݼ‬Ζ
• ࠌ‫ृش‬Ꮑ༼ࠎΚ
• ࣨ՗ऱ‫܉‬ᒵ(Gerberࢨ.DXF)
• ࣨ՗ऱᦤᐋᇷற(‫ޢ‬ԫᐋऱদ৫֗տሽൄᑇΔ८᥆দ৫֗ᖄሽএᑇ)
• ሽ୲Δሽტ࿛๯೯ցٙऱS೶ᑇ
• ‫פ‬෷࣋Օᕴऱloadpullᚾூ(MauryࢨFocusऱᚾூ௑‫)ڤ‬
Page 20
-10-
‫܉‬ᒵႪԵࠀឯ࠷RF‫ݝ‬ຝ‫܉‬ᒵ
• (ؐቹ)ൕCadence Allegroࢨ
ຘመgerber/dxfႪԵ‫܉‬ᒵቹ
ીADSᅝխ
• (‫׳‬ቹ)ኲ࠷‫ݝ‬ຝ‫܉‬ᒵࠀ๻ᆜ
඿։࣫հ൷ᆬ(port)
Page 21
๻ࡳPCBࣨ‫ޗ‬೶ᑇࠀച۩ሽ጖ᑓᚵ
• (ؐቹ)๻ᆜࣨ՗‫ޢ‬ԫᐋऱদ
৫֗տሽൄᑇΔ८᥆ᐋऱ
দ৫֗ᖄሽএᑇ
• (‫׳‬ቹ)ച۩ሽ጖ᑓᚵΔࠀ൓
ࠩठ՗ऱ‫ڍ‬ጤՑS೶ᑇ
Page 22
-11-
ലloadpullᇷறႪԵADS
ᢄ‫נ‬Pout Contour/Idc Contour
Step2
build_subrange(SP1.SP.S(1,1),1850M,1850M)
f1850..ZPoutdBm
f1850..ZIoutmA
Step1
Step3
m5
IndexIoutmA (1.000 to 38.000)
IndexPoutdBm (1.000 to 42.000)
freq (1.850GHz to 1.850GHz)
m5
IndexIoutmA= 7.000
f1850..ZIoutmA=0.376 / -61.665
IoutmA=1257.487333
impedance = Z0 * (1.094 - j0.845)
Step4
Page 23
࿨‫ٽ‬ሽ጖ᑓᚵS೶ᑇፖሽሁS೶ᑇ
ૠጩ૤ሉॴ‫ݼ‬
SP1.SP.S(1,1)
SP2.SP.S(1,1)
m6
m5
m4
m3
m2
m1
• (ؐቹ)ലठ՗ऱ‫ڍ‬ጤՑS೶ᑇፖց
ٙS೶ᑇ൷ದࠐ೚ߓอS೶ᑇ։࣫
ࠀ൓ࠩ૤ሉհઌᣂᇷற
• (‫׳‬ቹ)ֺለߓอ૤ሉፖPAᐗ೸৬
ᤜհ່ࠋ૤ሉଖऱೣฝၦΔ‫஁ڕ‬
၏መՕΔૹᄅਗᙇ֐಻ጻሁऱց
ٙ
-12-
IndexIoutmA (17.000 to 17.000)
IndexIoutmA (12.000 to 12.000)
IndexIoutmA (15.000 to 15.000)
IndexIoutmA (13.000 to 13.000)
IndexIoutmA (7.000 to 7.000)
IndexIoutmA (14.000 to 14.000)
freq (849.0MHz to 1.850GHz)
freq (0.0000Hz to 2.000GHz)
Page 24
‫شܓ‬loadpullፖߓอሽሁࣨᑓী
‫່נބ‬ᔞ‫ٽ‬ऱ֐಻ሽሁΔ‫ٵ‬ழքଡ᙮෷រ
– Lower Band
824M/849M/915M
– Higher Band
1710M/1850M/1910M
Page 25
‫ە‬ၦցٙଖऱ᧢೯ၦ(5%)
೚MonteCarloૠጩ
Page 26
-13-
፹࿓ࢬທ‫ګ‬հ᧢ฆၦ
Page 27
࿨ᓵ
• ೈॺߓอՠ࿓ஃ‫༽ނڶ‬Հԫ్ऱॴ‫ݼ‬ਢ50OhmΔ
ࠌ‫ش‬ऱࣨ՗দ৫ࡉտሽൄᑇፖֆࣨԫીΔ‫܉‬ᒵՈ
ԫᑌΔࠀࠌ‫ٵش‬ԫิীᇆऱሽ୲ሽტΖ‫׽࣠ڕ‬ਢ
ࠌ‫ش‬ઌ‫ٵ‬ऱցٙଖ‫܀‬լ‫ەװ‬ᐞࠡ‫ה‬ᐙ᥼ΔPAऱ௽
ࢤྤ‫ױ‬ᝩ‫܍‬ᄎ‫֏٭‬Ζ
• ኔᎾऱ‫܂‬ऄঞਢല‫ٺ‬ႈ‫౏ైڂ‬Ե๻ૠᅝխΔല‫܉‬
ᒵՈီ੡ॴ‫಻֐ݼ‬ऱԫຝٝΖ‫شܓ‬ADSৰ‫ݶ‬ऱ‫ބ‬
‫إנ‬ᒔऱ֐಻
Page 28
-14-
RF SiP/Module Design
Verification Flow in ADS
2007 EEsof Design Forun
Agilent EEsof EDA
HeeSoo LEE
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Objectives
Provides an overview of RF SiP technology and market
Provides an overview of RF SiP design flows in ADS
Demonstrates a bottoms-up ADS SiP design verification flow
with a quadrupled LO down-converter SiP example in a radar
system
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-1-
Agenda
1.
2.
3.
4.
5.
6.
What is RF SiP/Module?
RF SiP/Module Design Considerations and Design Flow
What Is TOPS Package?
A Quadrupled LO Down-Converter SiP
Co-Simulation of SiP in Radar System
Three Values ADS delivers for RF SiP/Module
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
1. What is RF SiP/Module?
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-2-
SiP Market Size
50% of worldwide packaged ICs will be SiP and 80% of them with embedded
passives by 2007 (Gartner)
In 2004, 1.89 Billion SiPs were assembled. By 2008, expected to reach 3.25
Billion, growing at an average rate of about 12% per year. (iNEMI)
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
RF SiP/Module Technology Overview
Integrates multiple chips w/ or w/o
embedded passive components
Technologies used in RF SiP:
Allows mix-and-match and use of
best in class technologies
• Substrates – Laminate, LTCC, Flex, Micro
Leadframe
Provides more integration flexibility,
faster time to market, lower R&D
cost, and lower product cost (for
some applications) than SoC
• Interconnects – Wirebond, Flip Chip
• IC’s – Silicon CMOS/BiCMOS, GaAs, InP
• Passives – SMD, Integrated (MCM-D),
Embedded (MCM-C MCM-L)
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-3-
RF SiP/Module Philosophy
Use the best technology for
each block
Quad-band Transceiver Module
SiGe BiCMOS, Silicon CMOS
Quad-band Transmitter Module
GaAs HBT, Silicon CMOS
Source: RFMD
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
How is RF SiP Market Evolved and
Evolving?
Semiconductor vendors’ competitive differentiators: cost, size, performance,
functionality
All are moving towards more integration on-chip (SoC) or in-package (SiP)
Silicon RFIC
SoC
Silicon, single die
Past
GaAs MMIC
??
SiP
Multiple Dies and
Passives (EP,IPD)
Future
??
IC Vendors Becoming
SoC or SiP Vendors
Comp
Mfg
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-4-
Where Will It Be Going?
- The Vision for RF System-in-Package (SiP)
Source: Rao Tummala, Georgia Tech
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
2. RF SiP/Module Design
Considerations and Design Flow
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-5-
Typical RF SiP/Module Design Considerations
3D Package Design
Substrate Stackup Design/Modeling
Die-to Die/Package Interconnects
•Wirebonds, FlipChip, Solder Ball
•PWB interconnects
•Via hole (IC-to- IC&Substrate)
SI/PI
•Simultaneous Switching Noise
•Crosstalk
•Delay
•IBIS models
Routing
Accurate Passive Models
•Embedded Passives (EP)
•Integrated Passive Devices (IPD)
Transistor Level Models
Vendor Components Library
•SMT components
•Transistor Level Device Models
System Level Design
Multiple Technologies
Multiple PDK Support
Behavior Models
•Verilog-A
Manufacturing data output
Measured Data
Test Methodology
Thermal Analysis
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
RF SiP/Module Market Segments
Segmented by
• System Contents
– Analog RF, Mixed Signal, and
Digital
• System Complexity or Scale
– Small, Medium, and Large
3 Market Segments
• Analog RF Small Scale SiP
• Mixed Signal Medium Scale SiP
• Digital Large Scale SiP
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-6-
Typical Applications For Each Market Segment
EEsof’s Focus Area
Analog RF Small Scale
• Typical RF Module applications
• Power Amplifier Module (PAM)
• ASM (Antenna Switch Module)
Mixed Signal Medium Scale
• Radio Module
• Transceiver Module
Digital Large Scale SiP
• MCP, PoP, PiP, Stacked Die
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
EEsof’s Current Design Flow Strategy
Analog RF Small Scale SiP
• Front-to-Back ADS Design Flow
• Dynamic Link for Si RFIC designs
Mixed Signal Medium Scale SiP
• Simulation Focused Integrated Design Flow
– Golden Gate/RFDE with Cadence Based SiP Flow
– Allegro/APD Design Flow Integration for EM simulations of packages,
interconnects, and embedded passives
• ADS Based Flow
– ADS Front-to-Back Design Flow
– Dynamic Link for Si RFIC designs
Large Scale Digital SiP
• Plug-in EM simulation technologies
Graphic Source: NXP W-LAN Transceiver
(Mixed Signal Medium Scale)
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-7-
ADS Driven Design Flow
– RF Module, Small Scale SiP
Model Development
System Level,
Algorithm Level
Design & Verification
Manufacturing Output
Fabrication
CVL*
Device
Modeling
IC-CAP
AMC
Models
Spec
SystemVue
SpectraSys
ADS
Schematic
Design &
Simulation
Ptolemy
Momentum
Physical
Component
Design
ADS
Layout
Physical
Design
GDS-II,
DXF,
Gerber
Layout
Translation
CST
3D EM
Momentum
& EMDS
DRC &
Physical
Verification
EM
Verification
Packaging, Interconnects, SMT, Embedded Passive
System
Flow
Electrical/Physical Design
Design
Tools
Design /
Application
Guides
SI/PI
Analysis
Synthesis Tools
CS / STW
Hardware
Validation
MMIC
Design Flow
PDK
DUT
* Component
Vendor
Library
Hardware Validation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
ADS Linked Design Flow
– Medium Scale SiP
System Level,
Algorithm Level
Design & Verification
Model Development
Device
Modeling
IC-CAP
Vendor
Library
AMC
SystemVue
SpectraSys
ADS
Schematic
Design &
Simulation
Ptolemy
CST
3D EM
Electrical/Physical
Design
Models
Spec
System
Flow
* Component
CVL*
Momentum
Physical
Component
Design
ADS
Layout
Physical
Design
Momentum
& EMDS
Packaging, Interconnects, SMT, Embedded Passive
Design
Tools
SI/PI
Analysis
EM
Verification
Tape-out
Fabrication
GDS-II
DXF
Gerber
IFF
Design /
Application
Guides
3rd Party
Schematic
3rd Party
Layout
Synthesis Tools
MMIC
Design Flow
w/ PDK
Gerber
rd
3 Party DRC
& Physical
Verification
DUT
Manufacturing
Data
Output
RFIC
Design Flow
w/ PDK
CS / STW
Hardware
Validation
Multi-Technologies
Hardware Validation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-8-
Multiple Environment Design Flow
– Large Scale SiP
System Level,
Algorithm Level
Design & Verification
Spec
Ptolemy
System
Flow
Multiple Chips Design
Composer
IC Schematic
.
.
.
.
Composer
IC Schematic
RFIC
Design
Flow
Virtuoso
RFIC Layout
Multi Technology Simulation
SystemVue
SpectraSys
Tape-out
Fabrication
D.I.E
Data
APD
SiP Physical
Design
.
.
.
.
APE
SpectraQuest
Package
Analysis
Manufacturing
Data
Output
Virtuoso
RFIC Layout
Momentum
& EMDS
SI/PI
Analysis
EM Verification
DUT
PDK
PDK
Device
Modeling
IC-CAP
CS / STW
Hardware Validation
Hardware
Validation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
3. What Is TOPS Package?
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-9-
Motivation and Features of TOPS Package
Motivation
•
•
•
•
•
Need to develop fast turn, SIP subsystem capability
SMT is the low cost assembly technique
Micro-circuit performance to 50 GHz and 40Gb/s at SMT prices
excellent heat dissipation even for high power devices
Replace slow, complex probe calibrations on mixed substrates with fast, coax, ECal calibration.
• Low cost high volume capable assembly/test process (44 part arrays of 10mm by
10mm)
Features
• Small form factor: 10mm X 10mm
• Lid: Non-hermetic, air-cavity with molded liquid crystal polymer
• Substrate: Rogers 4350 material with metal backing
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Structure of TOPS Package
BondWire
MMIC
BondWire
RT4350
Via
PC Board
Cavity Metal Slug
Test Board
Top Side
Bottom Side
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-10-
Measured Performance of TOPS Package
(PCB – Package – BondWire – ThinFilm Load)
Proven excellent performance up to
50GHz
-10
Cal PCB data used to correct for
PCB and connector losses
S11 (dB)
-15
-20
Less than 20dB
-25
Trace edge
to ckt edge
-30
-35
-40
0
10
20
30
40
freq, GHz
50
60
67
0.1 mm
Nominal
Pkg edge to
ckt edge
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
4. A Quadrupled LO Down-Converter SiP
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-11-
A Down-Converter SiP with Quadruple LO
A SIP based down-converter subsystem
Fast system implementation by utilizing existing MMICs and
thin-film circuits
• 7 MMICs (AMP, Multiplier, Mixer)
• 3 Thin-film circuits
• 5 Thin-film interconnects
Quadrupled LO
Frequency characteristic
• 22-24GHz RF input
• 1950MHz Fixed IF output
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
System Block Diagram
RF Path
Monitor Out
IF
LO
Divider
13 ~ 15dB Gain
Attenuator
LO Path
RF
Multiplier
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-12-
System Behavior Model Parameters
ADS System
Behavioral Models
1
2
3
Data Sheet
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Enhanced Validity of Simulation By Using
Measured Data with DAC Component
DAC is general purpose file reader for ADS
• Reads in measured data, component model parameters
• Generally supports two categories of formats
– MDIF (Measurement Data Interchange Format) based
– Simple form, Discrete based
Syntax: Use square bracket to access Sparameters from Touchstone file format
Measured Data
Syntax for DAC
• S-parameter - Use square bracket
• MDIF – use quote
• Discrete file sweep – no quote
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-13-
An Example of DAC Component With Measured
S-Parameter Data
Improved frequency characteristic of models
Fast and easy to setup
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Another Example of DAC Component With
Sweeping Model Files
Swept 5 different model files for P-HEMT transistors
Provides simple and quick first level statistical analysis
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-14-
Five MMICs Used in Quadrupled LO DownConverter SiP
MMICs represented with circuit level models with a design kit
• TC906 20~40GHz MMIC amplifier
• TC743 40GHz MMIC double balanced mixer
• TC745 10~26.5GHz MMIC frequency doubler
MMICs represented with system behavior models
• TC905 6~20GHz MMIC medium power amplifier
• TC904 23GHz (21.2~26.5GHz) MMIC LNA
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
20~40GHz Amplifier MMIC
Broadband (20-40GHz) MMIC amplifier
4 stage amplifier with an output match for power
Schematic Entry with Sub-circuits
Layout Component Representation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-15-
Circuit- and Behavioral- Level Comparison of
20~40GHz MMIC Amplifier
Very reasonable agreement for 20~40GHz
frequency range
S11
S21
S22
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Quadrupled LO Down-Converter SiP Simulation
With System Behavior Models
HB 2 Tone Freq Sweep
HB 2 Tone Simulation
HB 3 Tone Simulation
Conversion Gain = 13.373 dB
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-16-
Agilent EEsof’s Broad Range EM Solutions for
Modeling Passives/EP/IPD/Package
Momentum - 3D Planar EM simulator
EMDS - 3D Full Wave EM simulator
Link solution to CST Microwave Studio
AMDS (FDTD)
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
The New EMDS 3D Full Wave EM Solver
EMDS is an EM design & verification tool that simulates:
• Arbitrarily shaped structures
• Conductors, resistors, isotropic & anisotropic dielectrics, isotropic & anisotropic
linear magnetic materials
• Unlimited number of ports and/or circuit sources
• Frequencies greater than zero
• Absorbing boundary condition (free space)
To compute:
•
•
•
•
Network parameters (S, Y, Z)
Electric and Magnetic Fields
Multi-Mode impedance & propagation constants
Antenna parameters (gain, directivity, polarization …)
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-17-
Accurate EMDS Simulations of Passive Thin-Film
Circuits and Transitions
EMDS simulated passive circuits and transition
• BondWire
• Microstrip Bends
• 3dB and 10dB Attenuators
• Wilkinson Power Divider
• TOPS Package Transition
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Layout Components and EM/Circuit Co-Simulation
Visualizes electrical connections of layout in a schematic design
Simplifies Chip-Package-Board co-design process
• Allows easy optimization of de-coupling capacitor for SI/PI applications
• Reduces or eliminates potential design mistakes
Schematic
Representation
of Layout
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-18-
Circuit/System Mixed Level Quadrupled LO DownConverter SiP With Layout Components
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Harmonic Balance 2 Tone Simulation
Behavioral
Provides more complete level insights on harmonics
and spurious frequency contents than system behavior
models
Compare
Conversion Gain = 14.233 dB
Harmonic Balance 2 Tone Simulation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-19-
Optimized BondWire Interconnect For SiP
25um
1mil (26um)
Diameter
Wedgebonds
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Lumped Passive Equivalent Model for BondWire
L
L18
L=0.125 nH
R=
TLIN
TL11
Z=50.0 Ohm
E=47
F=40 GHz
Term
Term1
Num=1
Z=50 Ohm
TLIN
TL10
Z=50.0 Ohm
E=47
F=40 GHz
C
C26
C=0.0295 pF
C
C25
C=0.0295 pF
ADS Model
EMDS Model
-20
0
ADS Model (red trace)
Comp25um_Phase
phase(S(2,1))
Compensated25um
dB(S(1,1))
-10
Term
Term2
Num=2
Z=50 Ohm
-30
-40
-50
EMDS Model (blue trace)
ADS Model (red trace)
-50
-100
-150
EMDS Model (blue trace)
-200
-60
0
10
20
30
40
0
50
10
20
30
40
50
freq, GHz
freq, GHz
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-20-
Measurement Configuration For BondWire
Set Gating
On this Region
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Measured vs. Modeled Performance of Optimized
BondWire
Use Network Analyzer Gating to Isolate Bondwire Reflections
Correct for Up and Back Path Loss to Gated Region
dB(Modeled_S11)
dB_of_Measured_S11
0
-10
-20
-30
-40
-50
0
10
20
30
40
50
freq, GHz
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-21-
Complete Circuit/System Mixed Level Quadrupled
LO Down-Converter SiP With BondWires Added
Added
BondWires
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Complete Harmonic Balance 2 Tone
Simulation With BondWires Included
W/O BondWires
A complete level 2 tone HB simulation of the quadrupled
LO down-converter SiP including bondwires
Compare
Conversion Gain = 14.643 dB
Harmonic Balance 2 Tone Simulation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-22-
ADS Layout of Quadrupled LO Down-Converter SiP
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Other Interesting Simulation Tip
– “PathSelect2” Component
Different simulation path can be chosen by the value of “ModelSelect”
variable
• Uses “PathSelect2” component in ADS
• Good to analyze effects with or without certain components, for example
bondwires
Path 0
Path 1
2 Paths
Schematic
Representation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-23-
5. Co-Simulation of SiP in Radar System
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
Co-Simulation Made System Design Simple
• System design is critical to the overall success of
developing a SiP solution
• Co-simulation at all abstraction levels!
System Concept – Block
Diagram
Top Level System Using ADS Ptolemy
Transmitter RF System Using ADS Circuit
Envelope
Baseband Float/Fixed Point
HDL(Verilog & VHDL), MatLab®
C++.System-C
Power Amp Circuit Using ADS EM-Circuit Co-simulation
Behavior RF/Analog Subsystem,
Circuit, Transistor Level Models
Connected
Solution
Physical, EM Models, Circuit Models
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-24-
Behavior Models Speed Up Complex Simulations
Matlab, VHDL, C++, Verilog-A
PHD model for Amplifiers
Over 100x speed improvement with Automatic Verification Modeling (AVM)
Simulation Time
• Makes simulation of large circuits possible
• Makes accurate BER/PER simulations practical
Modulated Analysis
Using Transistor-Level Design
Modulated Analysis Using
Automatic Verification Modeling
Port
P1
Num=1
BJT_NPN
BJT3
BJT_NPN
BJT1 BJT_NPN
Port
BJT4
P2
Num=2
BJT_NPN
Transistor model
BJT2
Vout = F(|Vin+Nin|)*exp(j*H*Ph(Vin+Nin))
Mag
1
PortV_Noise
P1 SRC1
Design Complexity
_FIR
Xopt
_NL
X1
Ph 2
Port
P2
AVM
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
A Radar System Using Agilent Ptolemy Models and
Simulation Technology
Target Distance & RCS
Top Level Radar System Using ADS Ptolemy
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-25-
Transmitter and Receiver Designs in Radar System
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
A Demonstration
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-26-
6. Three Values ADS delivers for RF
SiP/Module
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
The Best Way to Design RF SiP With Confidence
Best industry leading and proven RF SiP simulation
Technologies
• Higher design win/success ratio
#1
• Easier and faster design evaluation
• Lower product development costs
• Linear
• HB
• CE
• Ptolemy
• EM
•…
Accuracy
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-27-
The Fastest Way To Achieve First Pass Design
Success
#2
Best and complete chip/package/board co-design
simulation flow
• Easier and faster optimization of a system at all level
• Less data and model compatibility and translation issues
(design overhead)
• Faster cycle time
• DSP
• System
• ICs
• Board
• Layout
•…
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
The Best Way To Reduce Risks of Last Minute
Design Failure
#3
Best integrated and full range EM solutions for accurate
passive modeling
• Reduced last minute design failures due to
interconnects/parastics (Marginal design)
• Faster and easier on/off chip passive component designs
(no data translation)
• Faster and accurate scalable passive model generation
and easier DK generation
Bottoms-Up SiP Design Verification in ADS
Aug, 2006 Version 1.1
-28-
WiMAX Wave2 Design Using ADS
Agilent Restricted
Page 1
Agenda
Overview
ADS Mobile WiMAX MIMO
Simulation Case Studies
Summary
Agilent Restricted
Page 2
-1-
802.xx A Family of Wireless Standards
Agilent Restricted
Page 3
The OFDMA Frame
In OFDMA, (user) data bursts overlap in time. This
maximizes data flow in a complex environment
DL Burst 3
DL Burst 4
DL Burst
7
DL Burst 6
Symbol #
TTG
Frame 1 (5 ms)
DL-MAP
Preamble
DL Burst 2
DL Burst 5
DL Burst 9
DL Burst 1
UL Zone 1
(PUSC)
Ranging , ACK, CQICH Fast
Feedback (when used)
DL Zone 3
FCH
(PUSC)
DL Zone 2
DL Burst 8
UL-MAP
FCH
DL-MAP
Preamble
Logical Subchannels
1st DL
DL Zone 1
zone only
UL Burst
1
RTG
time
Frame 2
Agilent Restricted
Page 4
-2-
Multipath Propagation
Receiver
Multipath
– Degrade SNR
Tu
– Introduce ISI
Transmitter
Combat Fading with
Diversity:
Delay Spread
– In Space
– In Frequency
– In Time
Agilent Restricted
Page 5
The Terminology Refers to the Channel
Single-In Single-Out
Single-In Multi-Out
Multi-In Single-Out
Multi-In Multi-Out
Today’s topics
It is simultaneous use of the
channel paths that gives the
greater benefits (but with
increased complexity)
Agilent Restricted
Page 6
-3-
Multiple Antenna Technologies
Diversity
– Mitigate fading
Transmit
Antennas
Receive
Antenna
– Space-time coding
MISO
Spatial Multiplexing
– Multiply data rates
Receive
Antennas
Transmit
Antennas
– Spatial diversity
MIMO
Agilent Restricted
Page 7
Motivation for MIMO OFDM
Challenges for Wireless Systems:
• The available bandwidth (Hz) is limited
• The environment is hostile (fading and multipath)
Addressing the Challenges:
• MIMO techniques increase system capacity (bits/sec/Hz)
• Combat fading through diversity (reduces BER)
Agilent Restricted
Page 8
-4-
Practical Challenges for MIMO OFDM
MIMO-OFDM systems faces some challenges:
• Implementation impairments: degrade performance.
• Multi-antenna (MIMO) architectures: increase complexity.
Agilent Restricted
Page 9
Agenda
Overview
ADS Mobile WiMAX MIMO
Simulation Case Studies
Summary
Agilent Restricted
Page 10
-5-
ADS Overview
Wireless Libraries
Fully coded signal source
DUT
`
Receiver
Measurement
System-Level
Circuit-Level
TransistorLevel
Hardware-Level
Agilent Restricted
Page 11
ADS Mobile WiMAX Wireless Library
User 0
FEC Encoding
Interleaving
User 1 FEC Encoding
Interleaving
Subcarrier Bit Allocation
And mapping
Multiplexer
OFDM Modulation
(IFFT, insert CP)
RF
Up-converter
Timing and frequency
synchronization
RF
Down-converter
…
User
K-1
Subcarrier Bit Allocation
And mapping
FEC Encoding
Interleaving
FEC Decoding
DeInterleaving
Subcarrier Bit Allocation
And mapping
Equalization and
Demapping
OFDM Demodulation
(FFT, remove CP )
Channel
Estimation
Agilent Restricted
Page 12
-6-
Benefits: ADS WiMAX Wireless Library
Benefits of using the ADS Mobile WiMAX Library:
• Pre-configured coded signal sources and receivers
• Coding/decoding algorithm test vector references
• MIMO and MISO support
• ITU and MIMO channel models
• RF design & verification; RF impairments
• EVM and BER/PER measurements
• Connected Solutions with Agilent test equipment
Agilent Restricted
Page 13
ADS Mobile WiMAX Downlink Source
Transmit
Antennas
Matrix A
STC
Receive
Antenna
MISO
Receive
Antennas
Transmit
Antennas
Matrix B
SM (MIMO)
MIMO
Agilent Restricted
Page 14
-7-
Adding Downlink Source Impairments
Specify Phase Noise vs.
Frequency Offset
Specify IQ Imbalance
Agilent Restricted
Page 15
Detailed Structure of Downlink Source
Agilent Restricted
Page 16
-8-
ADS Mobile WiMAX Downlink Receiver
Downlink RF MIMO Receiver
–
–
–
–
Transmit
Antennas
2x1 MISO and 2x2 MIMO
Time & Frequency Synchronization
Channel Estimation
Soft Decision Decoding
Receive
Antenna
MISO
Receive
Antennas
Transmit
Antennas
MIMO
Agilent Restricted
Page 17
Detailed Structure of Downlink Receiver
Agilent Restricted
Page 18
-9-
2x2 MIMO Channel Model with ITU
ITU Channel Models
Receive
Antennas
Transmit
Antennas
MIMO
Agilent Restricted
Page 19
2x2 MIMO Channel Model
Receive
Antennas
Transmit
Antennas
MIMO
Agilent Restricted
Page 20
-10-
Agenda
Overview
ADS Mobile WiMax MIMO
Simulation Case Studies
Summary
Agilent Restricted
Page 21
Simulation Case Studies
The following case studies will evaluate MIMO performance with
ADS simulation:
• Constellation and/or EVM versus the following impairments:
– DC offset
– RF channel isolation
– Gain/phase imbalance
– Phase noise
– PA non-linearity
• PER vs. Eb/No (2x2 MIMO, STC, and SISO)
Agilent Restricted
Page 22
-11-
Case Study Configuration
The following configuration was used for the first five case
studies:
• 2 x 2 MIMO
• 10 MHz bandwidth
• 5 ms frame duration,
• Cyclic prefix 1/8
• 16 QAM
• Rate ¾ Convolution Encoding
• 1024 point FFT size
• 10 dBm peak power preamble
Agilent Restricted
Page 23
DC Offset Schematic
PulseRF Results in DC Offset
Agilent Restricted
Page 24
-12-
Simulation Results: Constellations
0 dBm
5 dBm
10 dBm
15 dBm
Agilent Restricted
Page 25
Simulation Results: EVM vs. Subcarriers
Average EVM versus Subcarriers
Agilent Restricted
Page 26
-13-
MIMO RF Isolation Schematic
Vout1= Vin1+ Isolation1-2 x Vin2 [3]
Isolation1-2
Isolation2-1
Agilent Restricted
Page 27
Simulation Results: Constellations
-30 dB
-25 dB
-20 dB
-15 dB
Agilent Restricted
Page 28
-14-
Results: EVM vs. RF Interference
Average EVM versus Subcarriers
Agilent Restricted
Page 29
MIMO IQ Imbalance Schematic
Specify the Gain and Phase
Imbalance of IQ Modulators
Agilent Restricted
Page 30
-15-
Simulation Results: Constellations
0.1 dB of gain
1’ of phase
0.2 dB of gain
2’ of phase
0.3 dB of gain
3’ of phase
0.4 dB of gain
4’ of phase
Agilent Restricted
Page 31
Simulation Results: EVM vs. Imbalance
Phase Imbalance = 0 deg.
Agilent Restricted
Page 32
-16-
MIMO Phase Noise Schematic
Specify the Phase Noise vs.
Frequency Offset
Agilent Restricted
Page 33
Simulation Results: Constellations
-95 dBc @
100kHz
-90 dBc @
100kHz
-85 dBc @
100kHz
-80 dBc @
100kHz
Agilent Restricted
Page 34
-17-
EVM vs. Phase Noise
Subcarrier Spacing = 11.2 MHz/1024= 10.935 kHz
Agilent Restricted
Page 35
Power Amplifier Nonlinearities
Agilent Restricted
Page 36
-18-
Simulation Results: EVM vs. PA Backoff
Agilent Restricted
Page 37
MIMO PER Schematic
Agilent Restricted
Page 38
-19-
Simulation Results: PER
Agilent Restricted
Page 39
Summary of Case Studies
Various impairments can be evaluated such as DC offset, IQ
gain and phase imbalance, phase noise, and PA backoff using
the ADS WiMAX library and EVM as a metric
These impairments can be combined together or evaluated
individually
STC PER showed performance improvement over SISO PER
2x2 MIMO MMSE PER showed performance improvement over
ZF PER for low Eb/No
Agilent Restricted
Page 40
-20-
Summary
MIMO techniques increase system capacity (bits/sec/Hz) and
combats fading through diversity
ADS offers simulation sources, receivers, and channel models
for WiMAX MIMO design and verification
Constellation and EVM were examined with various simulation
impairments
Packet Error Rate (PER) was examined under various
simulation conditions
www.agilent.com/find/wimax
www.agilent.com/find/mimo
Agilent Restricted
Page 41
Thank You!
Agilent Restricted
Page 42
-21-
Software Defined Radio Design
featuring
Agilent SystemVue
Authored by:
Robert G. Davenport
MC2 Technology Group, LLC
Hemlock, NY
MC2 Technology Group, LLC
About MC2 Technology Group
2007/9/17
MC2 Technology Group, LLC
-1-
Agenda
„
„
„
„
Overview of SDR
Overview of Agilent SystemVue
Example FPGA-based FSK Transceiver.
Example DSP-based FM Receiver
Designed Exclusively in SystemVue
2007/9/17
MC2 Technology Group, LLC
SDR Terminology
„
„
„
„
„
„
„
„
SDR – Software Defined Radio
DSP – Digital Signal Processor
GPP – General Purpose
Processor
FPGA – Field Programmable
Gate Array
FIR – Fixed Impulse Response
Filter
FFT – Fast Fourier Transform
IIR – Infinite Impulse Response
Filter
I/Q – In-phase and Quadrature
(Complex )
2007/9/17
„
„
„
„
„
„
„
JTRS – Joint Tactical Radio
System
Waveform – SDR software
Application
Waveform Library
SCA – Software Communication
Architecture
CORBA – Common Object
Request Broker Architecture
IDL – Interface Description
Language
RTDX – Real-Time Data
Exchange
MC2 Technology Group, LLC
-2-
TYPICAL SDR Comm Radio
2007/9/17
MC2 Technology Group, LLC
SDR SOFTWARE ALLOCATION
2007/9/17
MC2 Technology Group, LLC
-3-
Software Communication
Architecture (SCA)
2007/9/17
MC2 Technology Group, LLC
SystemVue
„
„
„
„
„
Drag and Drop Block oriented
simulation tool similar to Simulink
Intuitive user interface (No “SystemVue
for Dummies” req’d)
Ideally Suited for SDR development and
simulation
Pioneered use of TI “RTDX” interface
My “Engineering Notebook”
2007/9/17
MC2 Technology Group, LLC
-4-
Simple FM Radio Example
2007/9/17
MC2 Technology Group, LLC
Simple FM Graphic Display
2007/9/17
MC2 Technology Group, LLC
-5-
FPGA-based 4FSK Receiver
„
TASK:
„
2007/9/17
Double the information bandwidth by
converting a legacy 2 frequency FSK
receiver into a 4 frequency FSK signal
(each tone represents a symbol that
translates to two bits of data)
MC2 Technology Group, LLC
FPGA-based 4FSK Receiver v.1
2007/9/17
MC2 Technology Group, LLC
-6-
4FSK Bit True Demod Simulation
2007/9/17
MC2 Technology Group, LLC
Bit-true FIR Low-pass Filter
2007/9/17
MC2 Technology Group, LLC
-7-
TI DSP-based FM Receiver
„
„
„
„
„
1. Use SystemVue Comm Library to simulate
desired receiver performance
2. Create bit-true simulation using SystemVue
DSP token library.
3. Capture block diagram and generate code
for desired processor.
Test and debug algorithm using RTDA token
Modify program I/O for real-time operation.
2007/9/17
MC2 Technology Group, LLC
DSP Based FM Receiver
2007/9/17
MC2 Technology Group, LLC
-8-
Cross Modulation in a
Full Duplex Transceiver
Cause, Effects,
and Simulation
Agilent - EEsof EDA
WeiWei-li Tsai
Senior Applications Engineer
September 2007
Cross Modulation Simulation in GoldenGate
September, 2007
Page 1
Cross Modulation: Outline
Cross modulation distortion in a full-duplex transceiver
• source, effects, mitigation
Cross modulation simulation requirements
Introduction to GoldenGate’s Envelope Transient engine
Simulating cross modulation in GoldenGate
Example simulation results
Conclusion
Further references
Cross Modulation Simulation in GoldenGate
July, 2007
Page 2
-1-
Cross Modulation: Definition
Cross modulation distortion (XMD) is the transfer of modulation
from one signal to another due to nonlinearities in a mutual
processing block (such as an amplifier).
• Signals can be wide or narrow band
• Usually the first stage/LNA is the critical block for linearity
• Transfer of modulation due to nonlinearity
Cross Modulation Simulation in GoldenGate
July, 2007
Page 3
Cross Modulation: Cause
• Transmitter and receiver operate simultaneously
• Duplexer has finite isolation between TX and RX
• “TX leakage” signal present at input of receiver
Antenna
LNA
TX Leakage
PA
Duplexer
Cross Modulation Simulation in GoldenGate
July, 2007
Page 4
-2-
Cross Modulation: Cause
• TX leakage cross modulates with adjacent channel jammer
• Neither TX leakage nor jammer are in RX band,
but cross modulation products do fall in band
Cross Modulation
TX
Leakage
Jammer
TX
Leakage
Desired
Signal
Jammer
Desired
Signal
Cross Modulation Simulation in GoldenGate
July, 2007
Page 5
Cross Modulation: Effect
• XMD raises the noise floor in the band of interest
• XMD lowers the sensitivity of the receiver
RX Band
Cross Modulation Simulation in GoldenGate
July, 2007
Page 6
-3-
Cross Modulation: Mitigation
• XMD can be reduced by increasing the linearity of the block
• Usually linearity requires more current, design trade offs
Gain
Noise Figure
Power Consumption
Linearity
Sensitivity
Cross Modulation Simulation in GoldenGate
July, 2007
Page 7
Cross Modulation: Mitigation
• Also can reduce the TX leakage at the input to the receiver
• Decrease the TX power, or increase the duplexer rejection
Antenna
LNA
TX Leakage
PA
Duplexer
Cross Modulation Simulation in GoldenGate
July, 2007
Page 8
-4-
Cross Modulation: Mitigation
How to decide which XMD reduction method is best?
Some options:
Tape out a chip
Wait for it to come back
Measure it in the lab
Repeat until right (or money runs out)
Or…
Accurate simulation!
Cross Modulation Simulation in GoldenGate
July, 2007
Page 9
Cross Modulation: Simulation Requirements
• RFICs carry complex digitally-modulated signals
• XMD depends on statistical properties of modulated signals
• Single tone approximations do not capture this behavior
• Approximations usually require arbitrary correction terms
The best practice is to simulate with the exact modulated
data which will be present in the real system.
Cross Modulation Simulation in GoldenGate
July, 2007
Page 10
-5-
Cross Modulation: Simulation Requirements
• RFICs are composed of transistor level devices
• XMD is caused by nonlinearities inherent in these devices
• High level models of device level phenomena are difficult
• Further abstraction from the problem brings more uncertainty
The best practice is to simulate at the transistor level where
the relevant distortions originate.
Cross Modulation Simulation in GoldenGate
July, 2007
Page 11
Cross Modulation: Simulation Requirements
Cross modulation distortion is a product of:
• complex modulated signals
• device level nonlinearities
Accurate simulation of XMD must include both of these effects
Using approximations for one or both will:
•
•
•
•
reduce the accuracy of the simulations
yield results with higher uncertainty
require larger error margins/tighter specs
result in over design
Over design usually leads to greater power consumption
Cross Modulation Simulation in GoldenGate
July, 2007
Page 12
-6-
GoldenGate’s Envelope Transient Engine
“Transistor level simulation with complex modulated signals”
Envelope Transient:
• Hybrid simulation approach (spice + harmonic balance)
• Combines time and frequency domain analysis methods
• Treats signals as modulation about a carrier and its harmonics
• Enables simulations not possible or practical with other tools
“Real waveforms, real devices, reasonable simulation times”
Cross Modulation Simulation in GoldenGate
July, 2007
Page 13
GoldenGate’s Envelope Transient Engine
Voltage (dBV)
NearlyNearly-Periodic Constraint
General Case
Analyzes signals in bands
about a central carrier,
similar to a radio spectrum
Frequency (GHz)
Cross Modulation Simulation in GoldenGate
July, 2007
Page 14
-7-
GoldenGate’s Envelope Transient Engine
The best application areas for Envelope Transient are analog
circuits with narrowband modulation around carriers and
baseband.
• Regular ET can be too slow for some mixer applications
• “Fast Envelope”
Envelope” is ET analysis with simplifying assumptions
• Performance improvements of Fast ET are significant
• Simplifying assumptions are not significant in many cases
• Validity of assumptions can be easily verified by running both
Cross Modulation Simulation in GoldenGate
July, 2007
Page 15
GoldenGate’s Envelope Transient Engine
Three levels of accuracy/speed tradeoffs are available:
• Fast ET Level 1 – fastest, but neglects filtering in the passband
• Fast ET Level 2 – includes filtering/slewing/memory effects,
but has some restrictions on sources
• Regular ET/ “none” – full Envelope Transient analysis,
slowest but most accurate
Cross Modulation Simulation in GoldenGate
July, 2007
Page 16
-8-
Cross Modulation: Simulation Examples
WCDMA modulation signal used for TX (blue)
TX and RX band are 3.84MHz wide, TX is 80MHz below RX
single tone jammer is 3.6MHz below RX, at -30dBm (red)
Cross Modulation Simulation in GoldenGate
July, 2007
Page 17
Cross Modulation: Simulation Examples
ET Simulator settings:
Tone (1,0,0) is the center of the RX band
Tone (0,1,0) is the center of the TX band
Cross Modulation Simulation in GoldenGate
July, 2007
Page 18
-9-
Cross Modulation: Simulation Examples
Performance setup:
Use the MBP function (Modulated Band Power) to measure the
XMD power in RX band (returns power in watts).
w2dbm(Probe_name.mbp(m, n, p, lower offset, upper offset))
Cross Modulation Simulation in GoldenGate
July, 2007
Page 19
Cross Modulation: Simulation Examples
Using performance equations enables easy data analysis for
sweeps, monte carlo, corners, etc.
Cross Modulation Simulation in GoldenGate
July, 2007
Page 20
-10-
Cross Modulation: Simulation Examples
Summing the TX Leakage and Jammer sources at the input
Cross Modulation Simulation in GoldenGate
July, 2007
Page 21
Cross Modulation: Simulation Examples
Creating a sinusoidal signal with the QPSKPS2 source:
(from goldenGateLib)
Jammer is on tone (1,0,0), TX leakage is on (0,1,0).
Cross Modulation Simulation in GoldenGate
July, 2007
Page 22
-11-
Cross Modulation: Simulation Examples
Creating a sinusoidal signal with the QPSKPS2 source:
Multiple sinusoids can be generated using this syntax:
[-3M, -450k, 30k, 2.546M, etc…]
Available mean power is distributed across all sinusoids
Cross Modulation Simulation in GoldenGate
July, 2007
Page 23
Cross Modulation: Simulation Examples
WCDMA modulation signal used for TX (blue)
TX and RX band are 3.84MHz wide, TX is 80MHz below RX
single tone jammer is 3.6MHz below RX, at -30dBm (red)
Cross Modulation Simulation in GoldenGate
July, 2007
Page 24
-12-
Cross Modulation: Simulation Examples
LNA: 500 linear, 40 nonlinear devices
Single point (TX leakage @ -20 dBm)
Regular ET:
4 minutes, RX band power:
-74.82 dBm
Fast Level 2:
1.5 minutes, RX band power: -74.81 dBm
Fast Level 1:
10 seconds, RX band power: -74.81 dBm
Cross Modulation Simulation in GoldenGate
July, 2007
Page 25
Cross Modulation: Simulation Examples
LNA: 500 linear, 40 nonlinear devices
Sweep 7 points (TX leakage from -50 to -20 dBm)
Regular ET:
35 minutes, 112 Mb ram
Fast Level 2:
9.5 minutes, 656 Mb ram
Fast Level 1:
1 minute, 141 Mb ram
Cross Modulation Simulation in GoldenGate
July, 2007
Page 26
-13-
Cross Modulation: Simulation Examples
LNA: 500 linear, 40 nonlinear devices
Sweep 7 points (TX leakage from -50 to -20 dBm)
Results from Fast Level 1, 2, and Regular ET agree quite well!
Cross Modulation Simulation in GoldenGate
July, 2007
Page 27
Cross Modulation: Simulation Examples
LNA + Mixer: 1300 linear, 120 nonlinear devices
Single point (TX leakage @ -20 dBm)
Regular ET: 26 minutes, 93 Mb
RX power: -71.65 dBm, BB power: -53.44 dBm
Fast Level 2: incompatible - 2 sources on same frequency
(Jammer and LO sources)
Fast Level 1: 3.5 minutes, 204Mb
RX power: -71.66 dBm, BB power: -53.07 dBm
Cross Modulation Simulation in GoldenGate
July, 2007
Page 28
-14-
Cross Modulation: Simulation Examples
LNA + Mixer: 1300 linear, 120 nonlinear devices
Sweep 7 points (TX leakage from -50 to -20 dBm)
Regular ET: 4 hr 45 minutes, 142 Mb
Fast Level 1: 29 minutes, 977 Mb
Cross Modulation Simulation in GoldenGate
July, 2007
Page 29
Cross Modulation: Simulation Examples
LNA + Mixer #2: 2000 linear, 170 nonlinear devices
Single point (TX Leakage @ -20dBm)
Schematic view
Regular ET: 6 hrs 10 minutes, 105 Mb
RX Power: -48.57 dBm, BB Power: -34.29 dBm
Fast Level 1: 12 minutes, 169 Mb
RX Power: -49.27 dBm, BB Power: -34.27 dBm
Cross Modulation Simulation in GoldenGate
July, 2007
Page 30
-15-
Cross Modulation: Simulation Examples
LNA + Mixer #2: 53000 linear, 220 nonlinear devices
Single point (TX Leakage @ -20dBm)
RC Extracted view
Regular ET: 24 hours, 485Mb
RX Power: -72.65 dBm, BB Power: -48.84 dBm
Fast Level 1: 1hr 10 minutes, 356Mb
RX Power: -73.23 dBm, BB Power: -48.71 dBm
Cross Modulation Simulation in GoldenGate
July, 2007
Page 31
Cross Modulation: Simulation Examples
Summary of results:
• Level 1 Fast ET usually has sufficient accuracy
• Block level simulations can be completed in minutes
• Larger chain and extracted simulations in a few hours
• Full verification possible in a weekend (regular ET, extracted)
• Parasitic extraction is significant and required for accurate data
Cross Modulation Simulation in GoldenGate
July, 2007
Page 32
-16-
Cross Modulation: Review
XMD is the transfer of modulation due to nonlinearity
XMD is a product of modulated signals and device nonlinearities
Accurate simulation of XMD must include both
• Exact complex modulated signals
• Transistor level nonlinearity models
GoldenGate’s ET simulator provides transistor level simulation
with complex modulated signals in a reasonable time
Cross Modulation Simulation in GoldenGate
July, 2007
Page 33
Cross Modulation: Conclusion
Modern radios do not carry sinusoids, but instead carry complex
digitally-modulated carriers. In order to properly characterize
RFIC circuits it is necessary to simulate them with the actual
signals which will be used in their radio applications.
Any verification technique that does not use exact waveforms
with device level models necessitates more margin in the design
process to account for greater errors incurred by over
simplification. This usually results in greater device power
consumption than would be required if accurate analyses had
been used.
Cross Modulation Simulation in GoldenGate
July, 2007
Page 34
-17-
Cross Modulation: FFT Windowing
FFT Windowing method:
Under ET Options
• Rectangular is more ideal/easier to use for sinusoids (red)
• Hanning more realistic/accurate for complex modulation (blue)
Cross Modulation Simulation in GoldenGate
July, 2007
Page 35
Cross Modulation: Full QPSKPS2 setup
Cross Modulation Simulation in GoldenGate
July, 2007
Page 36
-18-
Cross Modulation: Further Documentation
Documentation Location: $XPEDION/doc
gg_dm.pdf
gg_ug.pdf
- GoldenGate device manual
- GoldenGate users guide
For more info on:
QPSKPS2
USRIQPWS
ET Performance functions
FFT windowing
- gg_dm.pdf, section 3.1.1.6
- gg_dm.pdf, section 3.1.1.21
- gg_ug.pdf, section 14.2.1.2
- gg_ug.pdf, section 14.3.1.5
Cross Modulation Simulation in GoldenGate
July, 2007
Page 37
-19-
RF Silicon Tuner for DVB-T
ֆࡘ፣
πࣴଣ඲ТύЈ
09/13/2007
E_mail: stanleywu@itri.org.tw.
1
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
ITRI/STC
‫س‬಍඲Т‫ೌמ‬ว৖ύЈ
B
ౢ
཰
‫מ‬
ೌ
ܺ
୍
ಔ
E
‫س‬
಍
඲
Т
᏾
ӝ
‫מ‬
ೌ
ಔ
M:RF, Analog
and Mixed-signal
‫ೌמ‬ಔ
ଯᓎᑈᡏႝၡ೛
ी೽
ష‫ک‬Ԅᑈᡏႝ
ၡ೛ी೽
2
-1-
P
Ҿ
Ⴤ
ᆶ
ౢ
཰
ӝ
բ
ಔ
U
I
P
‫מ‬
ೌ
Ϸ
೛
ी
Ծ
୏
ϯ
ಔ
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Agenda
Ǹ Tuner Architecture Analysis
Ǹ ITRI/STC Silicon Tuner Design.
ȉ
ȉ
ȉ
ȉ
System Analysis.
Topology Selection.
Circuit Simulation.
Measurement and Result.
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
3
ፓᒋᏔ(Tuner)‫ޑ‬фૈ
•
ፓᒋᏔ‫ޑ‬фૈӧ‫ܭ‬ᒧ᏷ᓎ౗аௗԏኧՏႝຎૻဦ
Back End
Front End
໺಍ԄፓᒋᏔኳಔ
‫ޖ‬඲ፓᒋᏔኳಔ
Satellite
MPEG2
Decoder
AV Decoder
Terrestrial
Cable
ᐒ΢౯
໺಍ԄፓᒋᏔΰკТၗ਑ٰྍΚComtechα
‫ޖ‬඲ፓᒋᏔ ΰკТၗ਑ٰྍΚHimaxα
ኧՏႝຎᐒ
4
-2-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Tuner Architecture Analysis
•
•
•
•
•
SC-IFO (Single Conversion IF Output)
DuC-IFO (Dual Conversion IF Output)
SC-LIFO (Single Conversion Low IF Output)
DuC-ZIFO (Dual Conversion Zero IF Output)
SC-ZIFO (Single Conversion Zero IF Output)
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
5
Single Conversion IF Output
Chip
SC-IFO
LNA
Tracking
Filter
Mixer
SAW
LO
IF
IF
IF
Low
Channel
Wanted Signal
High
Channel
Image Signal
LO
IF
IF
IF
• TV Band: 50 ~ 860 MHz
6
-3-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Performance
CAN Tuner
Cost
Size
Manufacture
Complexity
Power
Consumption
CAN Tuner
V
DT r
e
Tun
Silicon Tuner
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
7
Dual Conversion IF Output
DuC-IFO
Chip
LNA
Mixer1
SAW1
Wanted Signal
IF1
LO1
Microtune’s Patent
Image1 Signal
SAW2
LO2
LO1
IF1
Mixer2
IF2
IF2
LO2
Image2 Signal
8
-4-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Single Conversion Low IF Output
SC-LIFO
Complex
Mixer
LNA
RF Poly-phase
Filter
IF Poly-phase
Filter
IRF
IIF
QRF
QIF
ILO
Low IF
Channel Select
Filter
QLO
Ί2
Divider-by-2
LO
Philips’s Patent
9
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Dual Conversion Zero IF Output
DuC-ZIFO
Mixer2
Channel Select
Filter
I Path
LNA
Mixer1
090
LO2
Q Path
LO1
Mixer2
10
-5-
Channel Select
Filter
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Single Conversion Zero IF Output
SC-ZIFO
Mixer
Channel Select
Filter
I Path
LNA
LO
090
Q Path
Mixer
•
Channel Select
Filter
Reference: “ᑇ‫ۯ‬ሽီᓳᘫᕴਮዌ‫ݾ‬๬։࣫”, STC Journal 003ය, ֆࡘ፣
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
11
Comparison
Architecture
SC-IFO
Tracking
Filter
Yes
IF SAW
Filter
Yes
2nd PLL and
VCO
DuC-IFO
SC-LIFO
Yse
Yes
Yes
BB Filter
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DC Offset
Fully
Integrated
Yes
SC-ZIFO
Yes
Accuracy PP
Filter.
Support
DVB-T
DuC-ZIFO
Yes
Support
DVB-H
12
-6-
Yes
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
RF IC Design Flow
Block spec.
definition and
Topology selection
System spec.
definition and
simulation
Circuit
Design
No
Design
Rule
Check
Yes
OK
IC Layout
Simulation
No
Simulation
with
Extraction
Parasitic
Extraction
Yes
OK
IC Tape-Out
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
13
Phase Noise System Simulation
DTV_DVBT_Rx_Sensitivity_Option1.dsn
Receiver minimum input level sensitivity measurement for DVB-T
Var
Eqn
VAR
Signal_Generation_VARs
FCarrier=474MHz
FIf=36.167MHz
SignalPower_dBm=Pin
Bandwidth=(2048/224) MHz
Mode=1
OversamplingOption=1
MappingMode=2
Guard=1/8
CodeRate=1
Var
Eqn
VAR
VAR
Delay
IntT oBits
D18
N=CodedBlockSize*DelayBlocks I5
nBits=8
Var
Eqn
Mode
0 ---------> 2K mode
1 ---------> 8K mode
MappingMode
0 ----------->QPSK
1 ----------->16-QAM
2 ----------->64-QAM
CodeRate
0 ----------> 1/2
1 ----------> 2/3
2 ----------> 3/4
3 ----------> 5/6
4 ----------> 7/8
OversamplingOption
0 ---------> 1 Ratio
1 ---------> 2 Ratio
2 ---------> 4 Ratio
3 ---------> 8 Ratio
4 ---------> 16 Ratio
5 ---------> 32 Ratio
VAR
Measurement_VARs
T runLen=10
MeasuredBlocks=1000
NumericSink
RxQAM
Signal
DVB-T
Source
DT V
Bandwidth=Bandwidth
Mode=Mode
OversamplingOption=OversamplingOption
GuardInterval=Guard
CodeRate=CodeRate
MappingMode=MappingMode
DataT ype=PN9
Push in to read
local information
HDTV
123
DVB-T
DT V_DVBT SignalSrc_RF
RxAntT empK
SignalSource
R1
FCarrier=FCarrier
Power=dbmtow(SignalPower_dBm)T empK=293.15
DT V_DVBT _Rx_Sensitivity_Info
Information
DT V_BER
D12
Length=CodedBlockSize
Delay=2*DelayBlocks
BER
Numeric
RF
DVB-T Rx T est
Benches Information
DF
DF1
DefaultNumericStart=0.0
DefaultNumericStop=100.0
DefaultT imeStart=0.0 usec
DefaultT imeStop=T Stop
RF
NumericSink
BER
Plot=None
Start=MeasuredBlocks
Stop=MeasuredBlocks
ControlSimulation=YES
Var
VAR
Rec eiv er
Eqn
VAR1
DT V_DVBT Receiver_RF
IntT oBits
Pin=-66
Receiver
I3
NF=0
MixerRF
FCarrier=FIf
nBits=8
T Stop=1 msec
Rx
Mode=Mode
NoiseFigure=NF
OversamplingOption=OversamplingOption
T ype=RF minus LO
GuardInterval=Guard
RfRej=-200
CodeRate=CodeRate
PARAMETER SWEEP
ImRej=-200
MappingMode=MappingMode
LoRej=-200
SoftDecision=Hard
ParamSweep
LComp=" 0 0 0"
T runLen=T runLen
Sweep1
SweepVar="Pin"
SimInstanceName[1]="DF1"
N_T ones
SimInstanceName[2]=
N1
SimInstanceName[3]=
T Step=T imeStep
SimInstanceName[4]=
Frequency1=FCarrier-FIf
SimInstanceName[5]=
Power1=.010 W
SimInstanceName[6]=
Phase1=0.0
Start=5
AdditionalT ones=""
Stop=16
RandomPhase=No
Step=1
PhaseNoiseData=
PN_T ype=Random PN
Phase Noise Setting
14
-7-
123
Numeric
SWEEP PLAN
SWEEP PLAN
SweepPlan
SweepPlan
SwpPlan2
SwpPlan1
Start=-79 Stop=-75 Step=0.2 Lin=
Start=-85 Stop=-80 Step=1 Lin=
UseSweepPlan=yes
UseSweepPlan=yes
SweepPlan="SwpPlan3"
SweepPlan="SwpPlan2"
Reverse=no
Reverse=no
SWEEP PLAN
SweepPlan
SwpPlan3
Start=-74 Stop=-70 Step=1 Lin=
UseSweepPlan=
SweepPlan=
Reverse=no
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Phase Noise System Simulation
BER
BER_PN2
BER_PN3
BER_PN4
BER_PN5
BER_PN6a
-> No Set Phase Noise.
-> PN={1e3 -82 1e4 -86 1e5
-> PN={1e3 -76 1e4 -76 1e5
-> PN={1e3 -60 1e4 -60 1e5
-> PN={1e3 -70 1e4 -70 1e5
-> PN={1e3 -60 1e4 -60 1e5
-106 1e6 -126},
-102 1e6 -122},
-90 1e6 -110},
-98 1e6 -118},
-98 1e6 -118},
Integtated PN=0.7 Deg
Integrated PN=1.6 Deg
Integrated PN=9.7 Deg
Integrated PN=2.7 Deg
Integrated PN=9.2 Deg
BER
DVBT_8K16QAMCR23GU18_RxPN2_Sensitivity..BER
DVBT_8K16QAMCR23GU18_RxPN3_Sensitivity..BER
DVBT_8K16QAMCR23GU18_RxPN4_Sensitivity..BER
DVBT_8K16QAMCR23GU18_RxPN5_Sensitivity..BER
DVBT_8K16QAMCR23GU18_RxPN6a_Sensitivity..BER
6E-1
1E-1
1E-2
1E-3
1E-4
1E-5
-90
-89
-88
-87
-86
-85
-84
-83
-82
-81
-80
-79
-78
-77
-76
-75
DVBT_8K16QAMCR23GU18_RxPN6a_Sensitivity..BER.DF.Pin
DVBT_8K16QAMCR23GU18_RxPN5_Sensitivity..BER.DF.Pin
DVBT_8K16QAMCR23GU18_RxPN4_Sensitivity..BER.DF.Pin
DVBT_8K16QAMCR23GU18_RxPN3_Sensitivity..BER.DF.Pin
DVBT_8K16QAMCR23GU18_RxPN2_Sensitivity..BER.DF.Pin
BER.DF.Pin
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
15
Phase Noise System Simulation
BER
BER_PN2
BER_PN3
BER_PN4
BER_PN5
BER_PN6a
-> No Set Phase Noise.
-> PN={1e3 -82 1e4 -86 1e5
-> PN={1e3 -76 1e4 -76 1e5
-> PN={1e3 -60 1e4 -60 1e5
-> PN={1e3 -70 1e4 -70 1e5
-> PN={1e3 -60 1e4 -60 1e5
-106 1e6 -126},
-102 1e6 -122},
-90 1e6 -110},
-98 1e6 -118},
-98 1e6 -118},
Integtated PN=0.7 Deg
Integrated PN=1.6 Deg
Integrated PN=9.7 Deg
Integrated PN=2.7 Deg
Integrated PN=9.2 Deg
BER
DVBT_8K64QAMCR23GU18_RxPN2_Sensitivity..BER
DVBT_8K64QAMCR23GU18_RxPN3_Sensitivity..BER
DVBT_8K64QAMCR23GU18_RxPN4_Sensitivity..BER
DVBT_8K64QAMCR23GU18_RxPN5_Sensitivity..BER
DVBT_8K64QAMCR23GU18_RxPN6a_Sensitivity..BER
6E-1
1E-1
1E-2
1E-3
1E-4
1E-5
-85
-84
-83
-82
-81
-80
-79
-78
-77
-76
-75
-74
-73
-72
DVBT_8K64QAMCR23GU18_RxPN6a_Sensitivity..BER.DF.Pin
DVBT_8K64QAMCR23GU18_RxPN5_Sensitivity..BER.DF.Pin
DVBT_8K64QAMCR23GU18_RxPN4_Sensitivity..BER.DF.Pin
DVBT_8K64QAMCR23GU18_RxPN3_Sensitivity..BER.DF.Pin
DVBT_8K64QAMCR23GU18_RxPN2_Sensitivity..BER.DF.Pin
BER.DF.Pin
16
-8-
-71
-70
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
RF IC Design Flow
Block spec.
definition and
Topology selection
System spec.
definition and
simulation
Circuit
Design
No
Design
Rule
Check
Yes
OK
IC Layout
Simulation
No
Simulation
with
Extraction
Parasitic
Extraction
Yes
OK
IC Tape-Out
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
17
Silicon Tuner Block Diagram of
ITRI/STC
CSF **
LNA
IF VGA
RF
IRM
RF AGC VCO1
Control
VCO2
Synthesizer
Synthesizer
Loop Filter
IF AGC
Control
Control
Interface
Loop Filter
* Don’t need external components except IF filter.
** The cost of SAW filter is about US$0.5.
18
-9-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Silicon Tuner Comparison
Architecture
Dual Conversion
( IF )
Single Conversion
( Low-IF )
Modified Dual Conversion
( IF or Low-IF )
Chip Design
Microtune, Maxim
Philips
STC
Advantage
No Tracking Filter
Full Integrated
Include Both Advantage of Dual and
Single Conversion.
No Tuning Voltage (30V)
Not need External Filter
Better Selectivity
No Zero-IF Problem
Flat IF Response
Image Reject depend on 1st
SAW Filter.
Need accuracy IF Polyphase
Filter.
Need 2nd IF SAW Filter
Need design Switchable BPF
Patent
Microtune Patent.
Philips Patent.
STC Patent.
Power
Consumption
High
Middle
Low
Process
SiGe
BiCMOS
RFCMOS 0.18um
Cost
High
Low
Low
Disadvantage
Need accuracy IF Polyphase Filter.
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
19
Yield Analysis
Yield Analysis(+/- Std. Dev 3deg)
mcTrial
0
1
2
3
4
5
6
7
8
9
10
11
12
13
PhaseBal
0.000
-0.828
3.645
2.455
-1.324
-0.872
-0.317
-2.842
5.263
5.390
-2.211
1.706
-2.215
0.405
NumPass
496.000
NumFail
504.000
IMRR>=35 dB
(a),(b)
Yield Analysis( +/- Std. Dev 3deg)
mcTrial
0
1
2
3
4
5
6
7
8
9
10
11
12
13
...4.PhaseBal
0.000
0.696
0.898
1.835
1.373
-1.424
0.480
-0.659
2.518
0.004
1.452
0.740
3.455
3.020
...5.PhaseBal
0.000
-3.113
3.277
2.739
-4.111
-1.130
4.320
-0.603
0.967
1.670
-2.913
0.325
1.201
6.606
NumPass
994.000
NumFail
6.000
IMRR>=60 dB
(c)
20
-10-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
RF IC Design Flow
Block spec.
definition and
Topology selection
System spec.
definition and
simulation
Circuit
Design
No
Design
Rule
Check
Yes
OK
IC Layout
Simulation
No
Simulation
with
Extraction
Parasitic
Extraction
Yes
OK
IC Tape-Out
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
21
Simulation Result
•
Image Reject (Sweep Frequency)
•
IR v.s IF_Gain
IR v.s. RFfreq
70.7
71.0
70.5
70.6
70.0
70.5
IR
IR
Image Reject (Sweep IF Gain)
69.5
70.4
69.0
70.3
68.5
70.2
68.0
70.1
900.0M
800.0M
700.0M
600.0M
500.0M
400.0M
300.0M
200.0M
100.0M
0.0000
1.000
1.500
3.000
3.500
4.000
IR v.s IF_Gain
IR
IFvalue=1.000
830.0M
668.0M
518.0M
355.0M
230.0M
93.00M
2.500
IFvalue
RFfreq[0]
RFfreq[0]
2.000
IR
Svalue=0.000
IFvalue
70.20
70.22
70.33
70.75
70.41
68.19
1.000
2.000
3.000
4.000
22
-11-
70.172
70.655
70.399
70.118
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Simulation Result
Noise Figure (Sweep Frequency) •
•
1.24
64.0
1.23
1.40
63.5
1.35
63.0
1.30
62.5
1.25
NFssb
NFdsb
1.25
64.5
66
64
62
1.22
1.21
60
1.20
58
1.19
1.20
62.0
1.15
61.5
56
1.18
1.17
0.0000 100.0M 200.0M 300.0M 400.0M 500.0M 600.0M 700.0M 800.0M 900.0M
54
1.000
1.500
2.000
2.500
RFfreq
NFssb[0]
IFvalue=1.000
1.176
1.197
1.337
1.195
1.230
1.523
RFfreq
8.300E8
6.680E8
5.180E8
3.550E8
2.300E8
9.300E7
ConversionGain
65.0
1.50
ConversionGain
1.55
1.45
NFdsb[0]
NFssb[0]
Noise Figure (Sweep IF Gain)
3.000
3.500
4.000
HB.IFvalue
NFdsb[0]
IFvalue=1.000
1.176
1.197
1.337
1.195
1.229
1.522
ConversionGain
IFvalue=1.000
64.913
63.796
62.910
63.346
63.067
61.551
HB.IFvalue
1.000
2.000
3.000
4.000
NFdsb
1.176
1.182
1.195
1.240
NFssb
1.176
1.183
1.196
1.240
HB.IFvalue
1.000
2.000
3.000
4.000
...versionGain
64.695
60.610
57.871
54.184
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
23
Simulation Result
•
•
Frequency Response
(Sweep Frequency)
Frequency Response
(Sweep IF Gain)
VGain vs. IF2freq
VGain vs. IF2freq
75
75
70
70
m14
m13
m15
65
m6
m15
m14
m13
65
ConversionGain
ConversionGain
60
60
55
50
55
50
45
45
40
40
35
35
30
30
25
90.00M
80.00M
70.00M
60.00M
50.00M
40.00M
30.00M
20.00M
10.00M
0.0000
-10.00M
-20.00M
90.00M
80.00M
70.00M
60.00M
50.00M
40.00M
30.00M
20.00M
10.00M
0.0000
-10.00M
-20.00M
IF2
IF2
m13
indep(m13)=36.00M
m13=63.76
IFvalue=1.000000, Svalue=0.000000
m13
indep(m13)=36.00M
m13=53.44
IFvalue=4.000000, Svalue=0.000000
m14
indep(m14)=36.00M
m14=57.11
IFvalue=3.000000, Svalue=0.000000
m6
m15
indep(m6)=3.600E7
indep(m15)=3.600E7
m6=63.865
m15=59.828
IFvalue=2.000000, Svalue=0.000000 IFvalue=1.000000, Svalue=0.000000
m14
indep(m14)=31.00M
m14=64.33
IFvalue=1.000000, Svalue=0.000000
m15
indep(m15)=3.600E7
m15=63.764
IFvalue=1.000000, Svalue=0.000000
24
-12-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Simulation Result
P1dB (Sweep Frequency)
m3
P_RF= -50.000
m3=52.424
IFvalue=4.000000, Svalue=0.000000
10
64
62
0
60
-5
58
-10
56
-15
54
-20
0
-70
-65
-60
-55
60
Gain
-10
m3
m4
55
-20
50
-30
52
-75
65
OP1dB
45
-80
-50
-75
-70
-65
-60
-55
-50
-45
P_RF
P_RF
m4
ind Delta= -21.000
dep Delta=1.036
IFvalue=1.000000, Svalue=0.000000delta mode ON
m4
ind Delta= -30.000
dep Delta=1.020
IFvalue=4.000000, Svalue=0.000000delta mode ON
25
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Measurement
Item
STC
Microtune (MT2060)
TSMC CMOS0.18um
SiGe/BiCMOS
1.8(V)
3.3 (V)
Frequency Range
50~ 860(MHz)
48~ 860(MHz)
Input Resistance
75 (Ohm)
75 (Ohm)
Min. Input power
-85 (dBm) @ 16 QAM, CR=2/3
Max. Input Power
-8 (dBm) @ 16 QAM, CR=2/3
Phase Noise
-102 dBc/Hz @ 100kHz offset
-108 dBc/Hz @ 100kHz offset
Total Noise Figure
< 5.5 (dB)
< 8 (dB)
Input Return Loss
10 (dB)
8 (dB)
> 50 (dBc)
60 (dBc)
250 mW
1W
Process
Supply Voltage
Image Rejection
Power Consumption
Die Size
ConversionGain
5
-80
P1dB (Sweep IF Gain)
Gain
P_RF= -80.000
Gain=53.444
IFvalue=4.000000, Svalue=0.000000
OP1dB
P_RF= -50.000
OP1dB=4.394
IFvalue=4.000000, Svalue=0.000000
ConversionGain
Pout_dbm
Gain
P_RF= -80.000
Gain=63.764
IFvalue=1.000000, Svalue=0.000000
OP1dB
P_RF= -59.000
OP1dB=5.698
IFvalue=1.000000, Svalue=0.000000
m3
P_RF= -59.000
m3=62.728
IFvalue=1.000000, Svalue=0.000000
Gain
m3
10m4
OP1dB
•
Pout_dbm
•
3500um*4000um
26
-13-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Measurement Result & Die Photo
PCB ᡍ᛾‫ހ‬
ჴሞௗԏኧՏႝຎߞဦ௃‫׎‬
Die Photo
27
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Thank you Very Much!
28
-14-
Copyright 2007 ITRIՠᄐ‫ݾ‬๬ઔߒೃ
Dr. Roberto Tinti, Ph.D.
Device Modeling Specialist
EEsof EDA
Agilent Technologies
PSP
Device Modeling
Overview and
Experience Sharing
Toe-Naing Swe
Semiconductor Modeling Consultant
EEsof EDA
Agilent Technologies
Group/Presentation Title
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Page 1
Agenda
What is the PSP model?
Major features of the PSP Model
Key Advantages
Additional info and literature reference on PSP
Current PSP Model release
PSP Model Extraction
Where to find the latest information
Group/Presentation Title
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-1-
What is the PSP Model?
•
It is a compact MOSFET model for digital, analog and RF design
•
It is jointly developed by NXP (formerly part of Philips) and
Arizona State University, ASU (formerly at the Pennsylvania
State University)
•
It was originally derived by MOS Model 11 (developed by Philips
Research) and SP Model (developed by Penn State University).
•
PSP is a surface potential model developed for today’s and
upcoming deep-submicron bulk CMOS technologies
•
In December 2005, the Compact Modeling Council, CMC elected
PSP as the new industry standard model for compact MOSFET
modeling.
•
PSP development is influenced and supported by CMC
members.
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Page 3
Major effects and features included in PSP [1]
• Physical surface-potential-based formulation in both intrinsic and extrinsic
model modules
• Physical and accurate description of the accumulation region
• All relevant small geometries effects are included
• Modeling of the halo implant effects, including output conductance
degradation in long devices
• Non-singular velocity-field relation enabling the Modeling of RF distortions
including intermodulation effects (IM3)
• Complete Gummel symmetry
• Mid-point bias linearization enabling accurate modeling of the ratio-based
circuits (e.g. R2R circuits)
[1] “Introduction to PSP MOSFET Model”, G. Gildenblat et al., Invited Paper at Workshop on Compact
Modeling, Anaheim, CA May 2005
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-2-
Major effects and features included in PSP [1]
(cont.)
•
•
•
•
•
•
•
•
Quantum-mechanical corrections
Correction for the polysilicon depletion effects
Gate induced Drain/Source Leakage GIDL/GISL model
Surface-potential-based noise model including channel thermal noise,
flicker noise and channel-induced gate noise
Advanced junction model including trap-assisted tunneling, band-to-band
tunneling and avalanche breakdown
Spline-collocation-based NQS model including all terminal currents
Stress model
Support for local and global parameters
[1] “Introduction to PSP MOSFET Model”, G. Gildenblat et al., Invited Paper at Workshop on Compact
Modeling, Anaheim, CA May 2005
Group/Presentation Title
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Page 5
Key Advantages of PSP
• Surface-potential-based model, PSP includes all relevant device physics
and its accuracy is verified down to the 65 nm technology node.
• Use of symmetric linearization method provides the most accurate
description in the moderate inversion or subthreshold regions (essential for
reduced Vdd applications)
• Most accurate description of C-V and transconductance/conductance
curves
• Unlike BSIM4, PSP symmetry and C3 continuity results in accurate
prediction of IM3 and harmonic behavior in RF and mixed signal
applications
• PSP improves modeling of halo-doped devices
• PSP provides the most complete junction (JUNCAP2) and noise models
• NQS effects are now included
• The PSP model structure is flexible and easily allows future enhancements
for advanced CMOS modeling.
Group/Presentation Title
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Page 6
-3-
PSP current and future development*
• Well Proximity Effects (WPE)
• Intentionally asymmetric devices
• PD-SOI and DD-SOI
• Advanced models of non-uniformly doped devices
• FINFET model
• Statistical modeling with PSP
• PSP-based varactor model
Note that some of these efforts (e.g. WPE) are undergoing and planned for
the upcoming PSP102.2 (refer to CMC website for up-to-date information
about future releases)
*courtesy of Prof. Gennady Gildenblat
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Page 7
Additional info and literature reference on PSP
• A good introduction that covers all the major features can be found in [1]
• A more detailed description of PSP model can be found in [2]
• How well PSP performs in traditional and new benchmark tests can be
found in the recently presented paper [3]:
– Traditional tests (slope-ratio, tree-top, transcapacitances, drain current
derivatives)
– More advanced tests: subthreshold region behavior, symmetry test,
reciprocity and back-bias clamping, NQS and noise.
References:
[1] “Introduction to PSP MOSFET Model”, G. Gildenblat et al., Invited Paper at Workshop on Compact
Modeling, Anaheim, CA, May 2005.
[2] “PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation”, G. Gildenblat et al.,
IEEE Trans. On Electron Devices, Vol. 53, No. 9, September 2006.
[3] “Benchmarking the PSP Compact Model for MOS Transistors”, Xin Li et al., 2007 IEEE International
Conference on Microelectronics Test Structures, March 19-22, Tokyo, Japan.
Group/Presentation Title
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-4-
Current PSP Model Release
The current PSP release is version 102.1 (October 2006)
–
–
–
–
–
PSP 102.1 is part of NXP’s SiMKit 2.4 (available for download at NXP website)
includes JUNCAP 200.2
is backward compatible with PSP 102.0
includes preliminary implementation of PSP-NQS
Download complete PSP 102.1 documentation at:
http://pspmodel.asu.edu/documentation.htm
PSP 102.1 supported simulators:
–
–
–
–
Agilent ADS 2006A Update 1, includes binning support
All simulators which support linking to SimKit 2.4 (e.g. Cadence spectre)
See CMC’s website for up-to-date info on standard models simulations support
Verilog-A code available at NXP Website
Group/Presentation Title
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Page 9
Agenda
What is the PSP model?
Major features of the PSP Model
Key Advantages
Additional info and literature reference on PSP
Current PSP Model release
PSP Model Extraction
Agilent PSP Modeling Package Key Features
Overview of the IC-CAP Modeling Packages
Local and Global Parameters
The Extraction Flow
Examples of Step by Step Extraction
Supported simulators
Where to find the latest information
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-5-
Agilent PSP Modeling Package Key Features
•
Efficiency: the IC-CAP architecture is designed to support local and
global extraction steps (e.g. two days DC extraction)
•
Accuracy: Incorporates inputs and requirements from PSP model
developers and foundry modeling teams who have shared their PSP
experience.
•
Completeness: supports measurement and extraction of both DC-CV
and RF.
•
Allows reuse of BSIM3/4 measured data.
•
Proven on real foundry data: The extraction procedure was validated
with 45nm devices.
•
Customizable extraction flow allows tailoring the extraction to the
process.
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Page 11
Overview of the IC-CAP Modeling Packages (1)
MOS Measurement
Module
PSP Extraction
Module
DC Bias - CV
Local Extr
T Settings
Global Extr
Device Def
Project Files
Local/Global
Meas Control
Data Display
Consistency
check
Simulator Links
Data Display
Documentation
Group/Presentation Title
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-6-
Overview of Measurement Module
The measurement module is common
to BSIM3/4 and PSP.
• Device Definitions
• Bias, Temperature conditions
• Switch matrix configuration
Group/Presentation Title
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Page 13
Overview of Extraction Module
• Implements extraction flow through
direct/tuning/optimization steps
• Global and Local extractions
• Global scaling extractions
• Binning
• Advanced Display Features
• Supported Simulator Links
• Documentation
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Page 14
-7-
Local and Global Parameters (1)
In the BSIM4 model:
Netlist with circuit description:
Model parameter set:
M1 1 2 3 4 NMOS L=1u W=10u
.model NMOS level=14
+ toxe=3.5n vth0=0.54 ..
:
§
·
§
L·
Vth Vth0 DVT 0 ˜ ¨¨ exp¨¨ DVT 1 ˜ ¸¸ ˜ .....¸¸ .....
lt ¹
©
©
¹
W ....
I DS
˜
˜ Vgs Vth ....
L toxe
Calculation of the electrical behavior of the MOSFET in a complex set of
equations which contain both, device dimensions (L, W, NF, ..) and model
parameters (TOXE, DVT0, VTH0,..)
Group/Presentation Title
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Page 15
Local and Global Parameters (2)
In the PSP model:
Netlist with circuit description:
Model parameter set:
M1 1 2 3 4 NMOS L=1u W=10u
.model NMOS level=14
+ toxo=3.5n vfbo=-1.012
vfbl=-0.0012 vfbw=0.023
vfblw=2.34e-6 ..
:
L · §
W ·
§
VFB VFBO ˜ ¨1 VFBL ˜ EN ¸ ˜ ¨1 VFBW ˜ EN ¸
L ¹ ©
W ¹
©
In a first step, a scaling of
WEN ˜ LEN · parameters is performed.
§
˜ ¨1 VFBLW ˜
¸
W ˜ L ¹ From a so called Global Model which contains
©
both, device dimensions and model parameters,
an effective parameter is calculated which is
called Local parameter.
I DS
E ˜ f VFB ˜ .....
The effective transistor properties are calculated
from Local parameters only !
Group/Presentation Title
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Page 16
-8-
Local and Global Parameters (3)
Local parameter
Equation in the Global Model
No scaling at all:
TOX
TOXO
Scaling vs. L or W only:
W §
W ·
RS RSW 1 ˜ EN ˜ ¨1 RSW 2 ˜ EN ¸
W ©
W ¹
Complex scaling vs. L, W and combinations of L,W:
DPHIBLEXP
§
·
LEN º
¨
¸ §
ª
WEN ·
DPHIB ¨ DPHIBO DPHIBL ˜
¸
¸ ˜ ¨1 DPHIBW ˜
«
»
W
©
¹
¨
¸
¬ L ¼
©
¹
W ˜L ·
§
˜ ¨1 DPHIBW ˜ EN EN ¸
W ˜L ¹
©
Group/Presentation Title
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Page 17
PSP Parameter Extraction Flow
There are three different type of parameters in PSP:
ƒ
Parameters which do not scale and are identical in the local and in the
global model such as very fundamental parameters like TOXO.
ƒ
Parameters not affecting the „transistor“ part in the PSP model (junction
capacitance or the diode).
ƒ
Parameters which scale with the transistor dimensions (L, W). These
parameters are mostly describing the „transistor“ behavior and influence
the core of the PSP model. The following pages will highlight the
extraction methodology for these parameters.
Group/Presentation Title
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Page 18
-9-
Extraction Flow Overview
Extract Further Global
Effects
Flexible Extraction Strategy
Finetune Global
Model
for PSP Model
Adjust Local vs.
Global Parameters
Scale Global
Parameters
Local Model
Extraction
Basic Capacitance
Effects
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Page 19
Examples of Step by Step Extraction
Capacitance Extraction
The oxide capacitance as well
as the overlap capacitance
effects are derived from the
well known test structures.
For this purpose, the global
model of PSP is invoked
and the fitting is done on
multiple devices simultaneously.
This extraction must be performed prior to the generation
of local models of single transistor devices !
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Page 20
-10-
Overview of the Extraction:
Extract Further Global
Effects
IC-CAP architecture supports flexible
extraction strategy for PSP Model
Finetune Global
Model
Adjust Local vs.
Global Parameters
Scale Global
Parameters
Local Model
Extraction
Local Model
Basic Capacitance
Effects
Global Model
Group/Presentation Title
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Page 21
Local Extraction:
A set of local parameters
are extracted from one
device only without
considering the device
dimensions:
VFB, BETN, NEFF, ...
The result is a set of Local
model parameters, which is
valid for one dedicated
transistor
Group/Presentation Title
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Page 22
-11-
Set of local extractions:
Local extraction is repeated
for different W/L devices
VFB, NEFF, BETN,
...
VFB, NEFF, BETN,
...
VFB, NEFF, BETN,
...
Dev. 1
W/L=5/5
Dev. 2
W/L=5/0.13
Dev. n
W/L=5/0.04
Group/Presentation Title
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Page 23
Local Parameter scaling
The local parameter values are
plotted vs. device dimensions
Scaling w.
Default Par.
Scaling after
extraction
NEFF from
Device n
Determine the scaling
parameters from this curve
according to the built in scaling
equation (general format):
NEFF from
Device 1
Local parameters
Global parameters
PAR
L ·
§
PARO ˜ ¨1 PARL ˜ EN ¸
L ¹
©
Group/Presentation Title
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Page 24
-12-
Global Scaling
With a more complex
scaling equation,
parameters are plotted
vs. L @wide W, W @
wide L, and L,W
simultaneously
W[m]
Lscale
5u
Wscale
240n
LWscale
Local parameters
Global parameters
150n
90n
65n
45n 60n 90n 150n 240n
PAR
5u
L[m]
Example for a typical general scaling equation:
W ˜L ·
W · §
L · §
§
PARO ˜ ¨1 PARL ˜ EN ¸ ˜ ¨1 PARW ˜ EN ¸ ˜ ¨1 PARLW ˜ EN EN ¸
W ˜L ¹
W ¹ ©
L ¹ ©
©
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Page 25
A summary of Local and Global Extraction steps
W[m]
4
5
1
5u
8
The extraction procedure is
clearly defined by the model
definition itself.
10
6
7
Due to the different scaling
equations, the stepping
sequence (1..10) shown on the
left hand sketch must be
followed.
3
9
240n
2
150n
90n
65n
45n 60n 90n 150n 240n
A few typical steps are described
in the next slides.
5u L[m]
Color code:
• Extraction of Local parameter sets
• Adjustment of Global model parameters to a group of
extracted Local parameters
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Page 26
-13-
Example of local/global extraction flow (1)
W[m]
1
5u
240n
150n
90n
65n
45n 60n 90n 150n 240n
5u
L[m]
Step 1: Long-Wide
Determination of a basic set of Local
parameters (NEFF, BETN,..) which are
extracted for each device.
Extraction of some Local parameters,
which will be fixed for all other devices
(VP, THEMU, ..). These parameters are
immediately transformed into appropriate
global parameters (VPO, THEMUO,..)
W[m]
Step 2: Long-Width Dependence
Determination of a basic set of Local
parameters (NEFF, BETN,..) which
are extracted for each device.
Extraction of some Local parameters,
which will describe narrow channel
effects only (MUE,CS)
5u
240n
2
150n
90n
65n
45n 60n 90n 150n 240n
5u
L[m]
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Page 27
Example of local/global extraction flow (2)
W[m]
Step 3: Scaling of Width Dependence
In this step, some global parameters, which
are only width dependent are already
determined from the appropriate local
parameters.
5u
3
240n
150n
90n
65n
45n 60n 90n 150n 240n
5u
L[m]
In this case these are:
MUEO, MUEW from MUE from steps 1,2
CSO, CSW from CS from steps 1,2
Why is this procedure necessary ?
Group/Presentation Title
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Page 28
-14-
Example of local/global extraction flow (3)
Impact on further extraction steps
W[m]
When the local parameter set of the
highlighted device A is extracted,
some local parameters which are
extracted from long channel devices
only (see steps 1 and 2) must be set
before the extraction starts.
5u
A
240n
150n
90n
65n
B
In the case of device B, it would be
possible to take these local
parameter from the appropriate
device with long channel length
W ·
§
MUEO ˜ ¨1 MUEW ˜ EN ¸
W ¹
©
MUE
This is not applicable for device A
because the appropriate long
channel device is missing.
Therefore, these parameters must
be calculated from the already
available global parameters.
CS
W ·
§
CSO ˜ ¨1 CSW ˜ EN ¸
W ¹
©
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Page 29
Overview of the Extraction:
Extract Further Global
Effects
Based on users feedback, a new tool
allows simultaneous adjustment of
local and global parameters
Finetune Global
Model
Adjust Local vs.
Global Parameters
Scale Global
Parameters
Local Model
Extraction
Basic Capacitance
Effects
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Page 30
-15-
Adjust Local/Global parameters
Select
parameters to
display the global
scaling.
Select electrical
scaling diagrams
(e.g. Vtlin(L) etc.).
Use real time
tuning thanks to
ADS link, which
allows several
simulations
running in the
background
Group/Presentation Title
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Page 31
Overview of the Extraction:
Extract Further Global
Effects
The last part of the extraction
includes global fine tuning
and STI effects
Finetune Global
Model
Adjust Local vs.
Global Parameters
Scale Global
Parameters
Local Model
Extraction
Basic Capacitance
Effects
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Page 32
-16-
Global Fine Tuning Extraction Step
Allows Tuning of
different I-V or
scaling curves:
Corner Id-Vd shown
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Page 33
STI Extraction
The STI (Shallow
Trench Isolation)
stress parameters
must be extracted
when a well fitted
global model is
available.
This is the final step in
the extraction flow.
Group/Presentation Title
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Page 34
-17-
Summary
• High levels of accuracy and efficiency in the Agilent PSP
Extraction Package have been achieved through a dedicated
implementation of the PSP extraction flow based on global and
local extraction steps.
• Feedbacks from foundries already extracting PSP have been
incorporated into the package.
• The package allows the user to adapt and then reuse the
customized extraction flow.
• The fast link between ADS and IC-CAP maximizes
optimization and tuning speed.
Group/Presentation Title
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Page 35
Where to find latest information about PSP
Official PSP Model Website maintained by ASU/NXP (all
reference material is downloadable here):
http://pspmodel.asu.edu/
Agilent PSP Extraction Package Website:
http://eesof.tm.agilent.com/products/iccap_psp.html
CMC Website:
http://www.eigroup.org/cmc/
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Page 36
-18-
Acknowledgements
Agilent Technologies would like to thank Dr. Thomas Gneiting of
AdMOS GmbH Advanced Modeling Solutions for his
collaboration to this presentation.
http://www.admos.de
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Page 37
-19-
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Issued date : 09/2007
Updated data : 09/2007
Printed in Taiwan
09/2007
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