ECE 5745 Complex Digital ASIC Design
Topic 7: Packaging, Power Distribution,
Clocking, and I/O
Christopher Batten
School of Electrical and Computer Engineering
Cornell University
http://www.csl.cornell.edu/courses/ece5745
Packaging
Power Distribution
Clocking
I/O
Part 1: ASIC Design Overview
P P
M M
Topic 4
Full-Custom
Design
Methodology
Topic 6
Closing
the
Gap
Topic 1
Hardware
Description
Languages
Topic 5
Automated
Design
Methodologies
Topic 8
Testing and Verification
Topic 3
CMOS Circuits
Topic 2
CMOS Devices
ECE 5745
Topic 7
Clocking, Power Distribution,
Packaging, and I/O
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Packaging
Power Distribution
Clocking
I/O
Agenda
Packaging
Power Distribution
Clocking
I/O
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• Packaging •
Power Distribution
Clocking
I/O
Basic Approaches to Packaging
Ball Grid Array
(BGA)
Adapted from [Terman’02]
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• Packaging •
Power Distribution
Clocking
I/O
Basic Package Types
What makes a good package?
I Low cost
I Small size
I Good thermal performance
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I
I
I
I
Large number of pins
Low pin parasitics
Easy to test
Highly reliable
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Adapted from [Weste’11]
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• Packaging •
Power Distribution
Clocking
I/O
Basic Package Types
DIP
8–64
Two rows of through-hole pins. 100mil pitch. Low
cost. Long wires between chip and corner pins.
PGA
65-400
Array of through-hole pins. 100mil pitch. Low
thermal resistance and higher pin counts.
SOIC
8–28
Two rows of SMT pins. 50mil pitch. Low cost.
TSOP
28–86
Two rows of SMT pin. 0.5–0.8mil pitch in thin
package. Used in DRAMs.
QFP
44–240
SMT pins on 4 sides. 15–50mil pitch. High density.
BGA
49–2000+
Array of SMT solder balls on underside of package
on 15–50mil pitch. Very high density with low
parasitics. Costly assembly.
LGA
Many
Similar to BGA but with gold pads instead of solder
balls. Commonly used with sockets (processors).
Adapted from [Weste’11]
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• Packaging •
Power Distribution
Clocking
I/O
Wire-Bond Pad Ring
Adapted from [Weste’11]
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• Packaging •
Power Distribution
Clocking
I/O
Wire Bonding Process
Bond Wires
Wire bonding
machine
Usually ultrasonic welding
connects wire to package
and die pad
Bond wires can be
aluminum or gold
Different thicknesses of
bond wire tradeoff
parasitic inductance and
resistance versus density
Can wirebond to die pad
pitches of around 100 m
Adapted from [Terman’02]
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L17 – Packaging
6
• Packaging •
Power Distribution
Clocking
I/O
Pin-Grid Array Assembly Process
Pin-Grid Array Assembly Process
Die Attach
(glue to package)
Oven Cure Die Attach
Saw
Die
Tested
Wafer
Wire bond pads
on die to pads on
package
Final Test
Glue lid on
package
Screen
Printing
Oven Cure Lid Attach
6.371 – Fall 2002
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11/1/02
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Adapted from [Terman’02]
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• Packaging •
Power Distribution
Clocking
I/O
Summary of Package Parasitics
Adapted from [Weste’11]
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• Packaging •
Power Distribution
Clocking
I/O
Pin Parasitics
Pin Parasitics
Pad on die
Bond wire
Package trace
Package pin
Rbond
Cpad
Lbond
Rtrace
Cbond
Wire bond, Cbond=1pF, Lbond=1nH
bond wire L approx. 1nH/mm
Solder bump, Cbond=0.5pF, Lbond=0.1nH
6.371 – Fall 2002
ECE 5745
Ltrace
Rpin
Ctrace
Lpin
Cpin
68-pin DIP, Cpin=4pF, Lpin=35nH
256-pin PGA, Cpin=3-5pF, Lpin=5-15nH
BGA, Cpin=2-4pF, Lpin=1-8nH
11/1/02
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Adapted from [Terman’02]
L17 – Packaging
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• Packaging •
Power Distribution
Clocking
I/O
Challenge: Power Delivery Scaling
Power = Volts × Amps
I CPU power consumption is increasing
. 2x per technology generation
I Supply voltages are dropping
. have to control electric field strength as transistors shrink
. keep power from growing even faster
I Power is going up, voltage is going down = current rising fast
. 100W at 1V implies 100A of current
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• Packaging •
Power Distribution
Clocking
I/O
Challenge:
IR Droop
IRStatic
Drop
VDD
Isupply
VDD-(Isupply*Rsupply)
Rsupply
Chip
Want to keep voltage droop (V = IR) small
Example, for 100W@1V, I=100A
–
–
–
5% droop is 50mV
At 100A, need effective supply resistance < 0.0005
Dissipate 5W heat just in power supply leads
Use multiple parallel Vdd/GND pins
Need very short fat wires to board power regulator
Want very low resistance on-chip power network
6.371 – Fall 2002
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11/1/02
T07: Packaging, Power Distribution, Clocking, and I/O
Adapted from [Terman’02]
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11
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• Packaging •
Power Distribution
Clocking
I/O
Challenge:Output
Dynamic Switching
dI/dt Droop Noise
Simultaneous
VB
Lpackage
I
VDD
Lpackage
B
A
A’s switch
t
Lpackage
64
A large number of output drivers A switching
high try to pull current through the power
supply inductance, causing the internal power
rail connected to gate B to droop (V=LdI/dt)
Gates driven by B may switch incorrectly.
Adapted from [Terman’02]
ECE6.371
5745– Fall 2002
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Clocking, and I/O
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L17 – Packaging
• Packaging •
Power Distribution
Clocking
I/O
Challenge: HeatThermal
DissipationModel
One Dimensional
Airflow
Heatsink
Sample overall
ja:
DIP 38 C/W still air
Thermal Slug
(Tungsten)
DIP 25 C/W forced air
PGA 5-10 C/W forced air
Microproc.and fan <3 C/W
Die
Tjunction
Power
Cdie
Die Attach Glue
(silver filled)
glue
Tglue
Cglue
(fluid pumped through die
microchannels 0.02 C/W)
Tslug
Cslug
sink
Tsink
air
Tambient
Csink
Adapted from [Terman’02]
6.371 – Fall 2002
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Distribution, Clocking, and I/O
L17 – Packaging
18
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Packaging
• Power Distribution •
Clocking
I/O
Agenda
Packaging
Power Distribution
Clocking
I/O
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Power Distribution: The Issue
Possible IR drop across power network
• Power Distribution •
Packaging
Clocking
I/O
Power Distribution Network Parasitics
VDD
VDD
Reff
Cg
Reff
Reff
Cd
Cg
Reff
GND
Cd
GND
6.375 Spring 2006 • L06 Managing Physical Design Issues in ASIC Toolflows • 39
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Power Distribution: The Issue
IR drop can
be and
static
or dynamic
Static
Dynamic
IR Drop
• Power Distribution •
Packaging
Clocking
I/O
Are these parasitic
capacitances bad?
Static
IR Drop
Dynamic
IR Drop
VDD
VDD
Reff
Cg
Reff
Reff
Cd
Cg
Reff
GND
Cd
GND
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Packaging
• Power Distribution •
Clocking
I/O
Realistic Power Distribution Networks
Adapted from [Weste’11]
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Power Distribution: Custom Approach
Various tailor
Approaches
Power Distribution
Carefully
powertonetwork
• Power Distribution •
Packaging
G
G
B
V
V
G
V
G
V
V
G
G
V
V
G
G
V
G
V
G
V
G
V
G
V
V
G
G
V
V
G
G
V
G
V
I/O
Routed power distribution on two stacked layers of
metal (one for VDD, one for GND). OK for lowcost, low-power designs with few layers of metal.
A
V
Clocking
Power Grid. Interconnected vertical and horizontal
power bars. Common on most high-performance
designs. Often well over half of total metal on upper
thicker layers used for VDD/GND.
Dedicated VDD/GND planes. Very expensive. Only
used on Alpha 21264. Simplified circuit analysis.
Dropped on subsequent Alphas.
G
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Packaging
• Power Distribution •
Clocking
I/O
Power Distribution for Standard Cells
Adapted from [Weste’11]
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Power Distribution: ASIC Approach
Power Distribution
Networks
PowerModular
rings partition
the power
problem
Packaging
• Power Distribution •
Clocking
I/O
Early physical partitioning
and prototyping is
essential
Can use special filler cells to
help add decoupling cap
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Packaging
Fine-grain power distribution
Scale Power Distribution
over entireNetwork
chip reduces IR d
Example of power distribution netw
using commercial ASIC back-end to
• Power Distribution •
Clocking
I/O
ade
au
sma
Works
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Packaging
Power Distribution
• Clocking •
I/O
Agenda
Packaging
Power Distribution
Clocking
I/O
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Clock Distribution: The Issue
Goal of Clock
Distribution
Clock propagates
across
entire chip
Packaging
Power Distribution
• Clocking •
I/O
Clock
Cannot really distribute
clock instantaneously
with a perfectly regular
period
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Clock Distribution: The Issue
Clock Skew
Two forms of variability
Packaging
• Clocking •
Power Distribution
I/O
Clock Skew
Difference in clock
arrival time at two
spatially distinct points
B
A
A
B
Skew
ECE 5745
Usable
Clock
Period
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Clock Distribution: The Issue
Clock Jitter
Two forms of variability
Packaging
Power Distribution
• Clocking •
I/O
Period A != Period B
Clock Jitter
Difference in clock
period over time
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Clock Distribution: The Issue
Why is minimizing
skew
and
jitter
hard?
Sources of Clock Skew and Jitter
Packaging
Clock
Distribution
Network
Central Clock
Driver
Variations in local clock load,
local power supply, local gate
length and threshold, local
temperature
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• Clocking •
Power Distribution
I/O
Variations in trace length,
metal width and height,
coupling caps
Local
Clock
Buffers
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Spring
2006 • L06
Managing
Design Issues in ASIC Toolflows
T07: Packaging,
Power
Distribution,
Clocking,
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I/O
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39
Clock Distribution: Custom Approach
Clock Clock
gridsGrids:
lowerLow
skew
but
high
power
Skew but High Power
Packaging
Power Distribution
• Clocking •
I/O
Grid feeds flops
directly, no local
buffers
Clock driver tree spans height of chip
Internal levels shorted together
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Spring
2006 • L06
Managing
Design Issues in ASIC Toolflows • 32
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Power
Distribution,
Clocking,
and Physical
I/O
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Clock Distribution: Custom Approach
TreesClock
haveTrees:
more
skew
but
More
skew
butless
Less power
Power
Packaging
Power Distribution
I/O
RC-Tree
H-Tree
Recursive pattern to distribute
signals uniformly with equal
delay over area
ECE 5745
• Clocking •
Each branch is individually
routed to balance RC delay
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Packaging
Power Distribution
• Clocking •
I/O
xample of
clock tree synthesis
usingof clock
Example
tree synthesis
usin
ommercial ASIC back-end
commercial
ASIC back-end tools
Clocktools
Tree Synthesis
6.375 Spring 2006 • L06 Managing Physical Design Issues in ASIC Toolflows • 37
CAD tools generate
balanced RC trees
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6.375 Spring 2006 • L06 Managing Physical Design Issues in ASIC
Static analysis to measure
clock skew and factor
it into static timing analysis
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Packaging
Power Distribution
• Clocking •
I/O
Example Skew/Jitter Analysis
Adapted from [Xiu’08]
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Packaging
Power Distribution
• Clocking •
I/O
Example Skew/Jitter Analysis
Adapted from [Xiu’08]
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Clock Distribution: Custom Approach
Active
Deskewingcircuits
Circuitsin
inIntel
Intel Itanium
Active
deskewing
Itanium
Packaging
Power Distribution
• Clocking •
I/O
Active Deskew Circuits (cancels out systematic skew)
Phase Locked Loop (PLL)
Regional
Grid
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Packaging
Power Distribution
Clocking
• I/O •
Agenda
Packaging
Power Distribution
Clocking
I/O
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Packaging
Power Distribution
• I/O •
Clocking
Single-Ended I/O Standards
Adapted from [www.interfacebus.com]
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Packaging
Power Distribution
Clocking
• I/O •
I/O Pads
Adapted from [Weste’11]
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Packaging
Power Distribution
Clocking
• I/O •
High-Speed Serial I/Os
I Pins are an expensive part of a system
.
.
.
.
.
.
.
Physical cost of adding pin to package
Size of package increases with more pins and on-pkg routing to pin
Bonding cost per pin
Size of motherboard depends on package size
More pins complicates board-level routing
Board testing time grows with number of pins
Reliability is function of number of solder connections
I Trend towards high-speed serial I/O
. As computing performance grows, pins become system bottleneck
. Want maximum bandwidth from available pins
. Current SerDes run at 3–6 Gb/s per link at <200 mW
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Packaging
Power Distribution
Clocking
• I/O •
Acknowledgments
I [www.interface.com] “Chart of Low Voltage IC Switching.”
http://www.interfacebus.com/Chart-of-Low-Voltage-IC-Switching.png
I [Terman’02] C. Terman and K. Asanović, MIT 6.371 Introduction to VLSI
Systems, Lecture Slides, 2002.
I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits and
Systems Perspective,” 4th ed, Addison Wesley, 2011.
I [Xiu’08] L. Xiu, “VLSI Circuit Design Methodologies,” Wiley-IEEE Press, 2008.
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