E522.51 1/40 Features Applications Typical Application Circuit
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E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Features General Description A primary buck converter converts from high voltage down to a link voltage, a secondary buck converter converts from link voltage. LDOs provide ripple free supply lines. ÿÿ Primary buck converter Input voltage up to 40V Output voltage 4.0-6.0V Output current up to 800mA ÿÿ Secondary buck converter Input voltage up to 6.0V Output voltage 0.8V-5.1V Output current up to 800mA ÿÿ LDO 1 Input voltage up to 40V Output voltage 0.5V-5.0V Output current up to 320mA ÿÿ LDO 2; LDO3; LDO4 Input voltage up to 6.0V Output voltage 0.5-5.0V Output current up to 350mA ÿÿ Internal power sequencing ÿÿ Configurable window / timeout watchdog SMPS: Voltage mode buck converter system. Both buck converters can be activated via high voltage capable pins ON1 and/or ON2. LDO1: High voltage input LDO LDO2-4: Low voltage input LDOs Power Monitoring: PGOOD indicates undisturbed operation of all regulators. RSTN provides a reset for the controller in case of watchdog error or system undervoltage. FS_ON sends a failsafe signal if the watchdog is not triggered properly. Internal state registers can be read via SPI Ordering Information Ordering No.: Temp RangeAmb Package E52251A78B -40°C to +105°C QFN48L7 Applications ÿÿ Microcontroller Supply Typical Application Circuit LPBO UB CINP_FI3 CINP_FI1 CINP_FI2 VIN1A Internal Supply CVIN1_1 VIN1B SW1A Primary Buck Converter OCP1 CMP1 CCMP1 CVIN1_2 SW1B PGND1 VIN2A VIN2B Secondary Buck Converter OCP2 CCMP2 CPBO_2 FB1 RCMP1 CMP2 LPBO CPBO_1 SW2A SW2B PGND2 CVIN2_2 CVIN2_1 CSBO_2 LPBO CSBO_1 PGND3 RCMP2 Charge Pump FB2 VIN_LDO1 VDDA CVDDA VOUT_LDO1 LDO1 CHP CO_LDO1 CCHP VIN_LDO2 VOUT_LDO2 LDO2 SNS_LDO2 FS_ON HV Interface ON1 ON2 CLDO2_O VIN_LDO3 VOUT_LDO3 LDO3 SNS_LDO3 CLDO34_O VIN_LDO4 VOUT_LDO4 LDO4 Oscillator SDI SNS_LDO4 Supply Monitor SCK CSN FOSC TST VIO Digital Control LV Interface LV Interface SDO RSTN INTN PGOOD E522.51 GND Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 1/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Functional Diagram VIN1A Internal Supply VIN1B SW1A Primary Buck Converter OCP1 CMP1 SW1B PGND1 FB1 VIN2A VIN2B Secondary Buck Converter OCP2 CMP2 SW2A SW2B PGND2 PGND3 Charge Pump FB2 VIN_LDO1 VDDA VOUT_LDO1 LDO1 CHP VIN_LDO2 VOUT_LDO2 LDO2 SNS_LDO2 FS_ON HV Interface ON1 ON2 VIN_LDO3 VOUT_LDO3 LDO3 SNS_LDO3 VIN_LDO4 Oscillator SDI CSN FOSC SNS_LDO4 Supply Monitor VIO LV Interface SCK LV Interface SDO VOUT_LDO4 LDO4 Digital Control TST RSTN INTN PGOOD E522.51 GND Bottom Side FB2 VIN2A VIN2B SW2A SW2B PGND3 PGND2 FB1 SW1A SW1B n.c. Top View PGND1 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 VIN1A 37 24 CMP2 VIN1B 38 23 SNS_LDO2 n.c. 39 22 VOUT_LDO2 ON1 40 21 VIN_LDO2 ON2 41 20 SNS_LDO3 FS_ON 42 19 VOUT_LDO3 n.c. 43 18 VIN_LDO3 VIN_LDO1 44 17 SNS_LDO4 n.c. 45 16 VOUT_LDO4 VOUT_LDO1 46 15 VIN_LDO4 CHIP 47 14 RSTN PGOOD 48 13 INTN 9 10 11 12 CSN 8 SCK 7 SDI OCP2 6 SDO OCP1 5 VIO 4 FOSC 3 GND 2 VDDA 1 TST EP CMP1 Pin 1 E522.51 Note: Not to scale, EP Exposed die pad Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 2/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Pin Description Pin Name Type 1) Description 1 TST D_I internally connected; reserved for factory use; connect to GND in the application 2 CMP1 A_IO Primary buck converter loop compensation 3 OCP1 A_IO Primary buck converter over current setting 4 OCP2 A_IO Secondary buck converter over current setting 5 VDDA S Regulated supply output 6 GND S Ground 7 FOSC D_I Input for external buck converter frequency; connect to GND if not used in the application 8 VIO S Host interface supply 9 SDO D_O SPI serial data output 10 SDI D_I SPI serial data input 11 SCK D_I SPI clock, pull down 12 CSN D_I SPI chip select, low active, pull up 13 INTN D_O Interrupt output, low active, pull up 14 RSTN D_O Reset output, low active, open drain 15 VINLDO4 S input LDO4 16 VOUTLDO4 A_O Output LDO4 17 SNSLDO4 A_I Feedback input LDO4 18 VINLDO3 S Input LDO3 19 VOUTLDO3 A_I Output LDO3 20 SNSLDO3 A_I Feedback input LDO3 21 VINLDO2 S Input LDO2 22 VOUTLDO2 A_O Output LDO2 23 SNSLDO2 A_I Feedback input LDO2 24 CMP2 A_IO Secondary buck converter loop compensation 25 FB2 A_I Secondary buck converter feedback input 26 VIN2A S (connect to pin 27) Secondary buck converter input 1 27 VIN2B S (connect to pin 26) Secondary buck converter input 2 28 SW2A A_IO (connect to pin 29) Secondary buck converter output 1 29 SW2B A_IO (connect to pin 28) Secondary buck converter output2 30 PGND3 S (connect to pin 31 and to system ground plane) Power ground 3 31 PGND2 S (connect to pin 30 and to system ground plane) Power ground 2 32 PGND1 S (connect to system ground plane) Power ground 1 33 FB1 A_I Primary buck converter feedback input 34 SW1A HV_A_IO (connect to pin 35) Primary buck converter output pin 1 35 SW1B HV_A_IO (connect to pin 34) Primary buck converter output pin 2 36 n.c. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 3/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Pin Name Type 1) Description 37 VIN1A HV_S (connect to pin 38) Main supply pin1 38 VIN1B HV_S (connect to pin 37) Main supply pin2 39 n.c. 40 ON1 HV_A_I Primary buck converter control input 41 ON2 HV_A_I Secondary buck converter control input 42 FS_ON HV_D_O Fail safe output, open drain, high voltage 43 n.c. 44 VIN_LDO1 HV_S 45 n.c. 46 VOUT_ LDO1 A_O LDO1 output 47 CHP A_IO Auxiliary internal supply 48 PGOOD D_O Logical output for indication of proper regulator operation, internal pullup resistor - EP S Exposed Die Pad LDO1 input 1) A= Analog, D= Digital, HV= High Voltage, I/O= Input/Output, S= Supply Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 4/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 1Customer Specific Programming Customer: KOSTAL no no yes yes yes yes yes yes yes yes yes yes yes no no no no no no yes - Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 5/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 2Absolute Maximum Ratings Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages with respect to ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative. Description Condition Symbol Min Max Unit VEXP_PAD -0.15 +0.15 V 2.5 W 105 °C 125 °C Θstore 150 °C Junction temperature ΘJ 150 °C Voltage at pins VIN1A, VIN1B V VIN1A,B -0.3 40 V Voltage at pin GND VGND -0.15 +0.15 V Voltage at pin VIO V VIO -0.3 6.5 V -0.3 V VIO+0.3 V -5 +5 mA Exposed pad voltage Power dissipation EIA/JESD51 standard; test board according to JEDEC standard 51-7; maxi- PDevice mum exposed die pad temperature < 135 °C Θamb Ambient temperature Storage temperature unsoldered device Storage temperature soldered device Θstore VFOSC, SDO, SDI, Voltage at pin FOSC, SDO, SDI, SCK, CSN, PGOOD, INTN, TST SCK, CSN, PGOOD, INTN, TST IFOSC, SDO, SDI, Current at pin FOSC, SDO, SDI, SCK, CSN, PGOOD, INTN, TST SCK, CSN, PGOOD, INTN, TST Voltage at output pins SW1A and SW1B VSW1A,B -1 V VIN1A,B V Voltage at feedback pin FB1 VFB1 -0.3 6.5 V Voltage at pin ON1 VON1 -0.3 40 V Voltage at pin OCP1 VOCP1 -0.3 VDDA+0.3 V Voltage at pin CMP1 VCMP1 -0.3 VDDA+0.3 V Current at pin ON1 ION1 -5 5 mA Current at pin OCP1 IOCP1 -5 5 mA Current at pin CMP1 ICMP1 -5 5 mA Voltage at pin PGND1 VPGND1 -0.15 +0.15 V Voltage at input pins VIN2A and VIN2B VIN2A,B -0.3 6.5 V VSW2A,B -0.3 VIN2A,B V Voltage at feedback pin FB2 VFB2 -0.3 VIN2A,B V Voltage at pin ON2 VON2 -0.3 40 V Voltage at pin OCP2 VOCP2 -0.3 VDDA +0.3V V Voltage at output pins SW2A and SW2B static condition (V__SW2A,B may go down to -1V temporarily during operation) Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 6/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Description Condition Symbol Min Max Unit Voltage at pin CMP2 VCMP2 -0.3 VDDA +0.3V V Current at pin ON2 ION2 -5 5 mA Current at pin OCP2 IOCP2 -5 5 mA Current at pin CMP2 ICMP2 -5 5 mA Voltage at pin PGND2 VPGND2 -0.15 +0.15 V Voltage at pin PGND3 VPGND3 -0.15 +0.15 V Voltage at pin VIN_LDO1 V VIN_LDO1 -0.3 40 V Voltage at pin VOUT_LDO1 V VOUT_LDO1 -0.3 6.5 V Voltage at pins VIN_LDO2-4 V VIN_LDO2-4 -0.3 6.5 V Voltage at pins VOUT_LDO2-4 V VOUT_LDO2-4 -0.3 6.5 V V Voltage at pins SNS_LDO2-4 VSNS_LDO2-4 -0.3 VOUT_LDO2-4 +0.3 Current at pins SNS_LDO2-4 ISNS_LD2-4 -5 +5 mA Voltage at pin RSTN VRSTN -0.3 6.5 V IRSTN -5 Current at pin RSTN Current at pin RSTN in active state output low Voltage at pin FS_ON VFS_ON -0.3 Current at pin FS_ON IFS_ON -5 Current at pin FS_ON in active state mA IRSTN_act output low +5 mA 40 V mA IFS_ON_act +5 mA Min Max Unit 3ESD Protection Description Condition Symbol ESD HBM protection at pin VIN1A, VIN1B, VINLDO1, ON1, ON2 HBM 1) ±4 - kV ESD HBM, all other pins HBM 1) ±2 - kV ESD on IC Level CDM 2) ±0.5 - kV 1) According to AEC-Q 100-002, Human Body Model, 1.5kΩ resistance, 100pF capacitance. 2) According to AEC-Q 100-011, Charged Device Model, pulse rise time (10% to 90%) <400ps, 1Ω resistance. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 7/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 4Recommended Operating Conditions Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified. All voltages are referred to ground (0V). Currents flowing into the circuit have positive values. The first electrical potential connected to the IC must be GND. (If not specified specify timing sequence of electrical contacts.) Description Condition Supply voltage at pins VIN1A,B Symbol Min Typ Max Unit V VIN1A,B 6.5 12 30 V Junction temperature during operation < 1000 h ΘJ_150 150 °C Junction temperature during operation < 9000 h ΘJ_105 105 °C Input low level at pin TST operation in application; connect to GND V TST,INL 100 mV Blocking capacitor at Pin VDDA CVDDA 470 nF Blocking capacitor at Pin CHP CCHP 220 nF First external input capacitor for primary buck converter setup parameter CVIN1_1 40 Second external input capacitor for primary buck converter setup parameter CVIN1_2 100 External output inductance for primary buck converter μF 1000 nF setup parameter (typical input voltage 12V; outputvoltage 5.5V) LPBO 22 μH First external output capacitor for primary buck converter setup parameter (typical input voltage 12V; outputvoltage 5.5V) CPBO_1 47 μF Second external output capacitor for primary buck converter setup parameter (typical input voltage 12V; outputvoltage 5.5V) CPBO_2 Equivalent serial resistance of external output capacitor for primary buck converter 1) setup parameter RESR_C_PBO Compensation network for primary buck converter consisting of CCMP1 and RCMP1 in series setup parameter CCMP1 470 nF Compensation network for primary buck converter consisting of CCMP1 and RCMP1 in series setup parameter RCMP1 2200 Ω First external input filter capacitor setup parameter CINP_FI1 100 μF Second external input filter capacitor setup parameter CINP_FI2 100 μF Third external input filter capacitor setup parameter CINP_FI3 100 nF External input filter inductor setup parameter LINP_FI 15 μH First external input capacitor for secondary buck converter setup parameter CVIN2_1 40 Second external input capacitor for secondary buck converter 2) setup parameter CVIN2_2 100 External output inductance for secondary buck converter setup parameter (typical input voltage 5.5V; outputvoltage 1.7V) LSBO 5.6 50 µF mΩ μF 1000 nF 10 μH 1) Smaller ESR may cause very low phase margins. 2) can be omitted if the input of the secondary buck converter is connected to the output of the primary buck converter and CPBO_2 is applied Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 8/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Description Condition Symbol First external output capacitor for secondary buck converter setup parameter (typical input voltage 5.5V; outputvoltage 1.7V) CSBO_1 Second external output capacitor for secondary buck converter setup parameter (typical input voltage 5.5V; outputvoltage 1.7V) CSBO_2 Min Typ Max 22 Unit μF 5.6 μF Equivalent serial resistance of exter- setup parameter nal output capacitor for secondary (typical input voltage 5.5V; outbuck converter 1) putvoltage 1.7V) RESR_C_SBO Compensation network consisting of CCMP2 and RCMP2 in series setup parameter CCMP2 100 nF Compensation network consisting of CCMP2 and RCMP2 in series setup parameter RCMP2 4700 Ω 50 mΩ 1) Smaller ESR may cause very low phase margins. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 9/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 5Electrical Characteristics (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol Min Typ Max Unit Supply voltage at pins VIN1A,B for validity of specified parameters setting parameter V VIN1A,B 5.2 14 30 V Supply current at pins VIN1A,B in active mode Sum of currents at pins VIN1A, VIN1B, VIN_LDO1; V VIN1A,B=14V IVIN_act 18 Supply current in sleep mode with all regulators off (LDO1 disabled via SPI) Sum of currents at pins VIN1A, VIN1B, VIN_LDO1; 7V ≤ V VIN1A,B≤15V; no pull- up/down current at pins 2) IVIN_slp 10 25 μA Supply current in sleep mode with all regulators off except LDO1 on (ao); no output current out of pin VOUT_ LDO1 Sum of currents at pins VIN1A, VIN1B, VIN_LDO1; V VIN1A,B ≤ 15V; 7V ≤ V VIN_LDO1≤ 15V; LDO1 on (ao); no pull- up/down current at pins 2) IVIN_slp_ao 30 60 μA Power Supply I(VIN1A)+I(VIN1B)+ Supply current sleep mode with all I(VIN_LDO1)I(VOUT_LDO1); regulators off except LDO1 proV VIN1A,B ≤ 15V; grammed to be always on (ao) 7V ≤ V VIN_LDO1≤ 15V; IVIN_slp_ao_imax measured with maximum output = -25mA VOUT_LDO1_MAX current at pin VOUT_LDO1, not pro- ILDO1 on (ao); duction tested no pull- up/down current at pins 2) 3) mA 75 μA Low voltage supply output in active active mode, no exmode ternal DC load V VDDA 3.2 3.35 3.5 V Low voltage supply output in sleep mode sleep mode, no external DC load V VDDA_slp 3.1 3.3 3.5 V Power low threshold supply falling V VDDA_UV 2.45 2.75 V Difference of rising and falling threshold 1) V VDDA_UVhys 0.4 V external blocking capacitor at pin VDDA CVDDA 220 470 1000 nF auxiliary supply voltage at pin CHP VCHP 7 7.5 8 V external blocking capacitor at pin CHP CCHP Supply voltage at pad VIO setting parameter V VIO 220 3 nF 5.5 V 1) Defined by design. Not subject to production test. 2) Θamb ≤ 35 deg. C 3) Information Parameter. Not subject to production test. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 10/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Electrical Characteristics (continued) (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol Min Typ Max Unit Operation States Delay Time Parameters Minimum time step for power sequencing tPWRS Multiplier for power sequencing time step mPWRS 2 2 2 TJ,warn 120 140 155 °C Frequency of internal oscillator for derivation of buck converter switching clock according to frequency divider settings fCLK 7.3 8 8.5 MHz Input high level for application of external clock VFOSC_IH 0.75 Input low level for application of external clock VFOSC_IL Pull down resistor at Pin FOSC RFOSC_PD 100 Frequency of externally applied clock; divided by 2 internally in order to obtain an appropriate duty cycle fOSC_ext 0.4 DCLK_ext 30 512 μs Over Temperature Junction temperature for over temperature warning Buck Converter Oscillator Duty cycle of externally applied clock setting parameter Filter time for external clock tFOSC_filt V VIO 0.25 V VIO 200 kΩ 1.6 MHz 50 70 % 50 100 μs 14 30 V 150 Primary Buck Converter Main supply and primary buck converter input voltage range setting parameter VRPB_I Factory programmed output voltage 5.5V < V VIN1A,B < 30V VPB_O Output voltage deviation from programmed value 5.5V < V VIN1A,B < 30V; pin FB1 connected VOTOL_PB to output capacitor -3 Average output current range overall power dissipation within limit IPB_O -0.8 Output voltage at pin OCP1 IOCP1=-175 μA VOCP1 1.20 1.26 1.32 V Custom over current limitation setting by current from pin OCP1 to ground IPB_OC 7000 10000 13000 IOCP1 Default over current limitation pin OCP1 open IPB_OC_def -3 -2.5 -2 A 0.3 0.65 Ω 2.0 2.5 mS Switch on resistance high side switch of primary buck converter Voltage regulation loop transconductance 1) 6.5 5.5 RDS_ONPB_ V 3 % A HS I(CMP1)=0 V(CMP1)=0.3 ... 2.2 V Gm 1.5 1) Internal sawtooth voltage is between 0.3 V and 2.2 V. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 11/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Electrical Characteristics (continued) (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol Converter operating frequency setup parameter fOP_PB 400 kHz Soft start slew rate SRPB_SOS 4 V/ms Control input high voltage VIH_ON1 Control input low voltage VIL_ON1 Control input pull down current VI_ON1=28 V IPD_ON1 Control input resistance VI_ON1<3V; Information Parameter RI_ON1 Discharge current in Sleep mode V(FB1) > 1V IPD_SLEEP Min Typ Max 2.4 V 15 15 Unit 0.95 V 40 μA 130 kΩ 30 mA 100 µs Debounce time for pin ON1 tON1,deb Minimum Capacitance at the compensation network to pass internal start up self test CCMP1MIN 300 600 1000 pF Minimum pulse width without overcurrent tMinimum Pulse 100 150 200 ns 4 5 6 V Width Secondary Buck Converter Secondary buck converter input voltage range (pins VIN2A,B) setting parameter VSB_I Factory programmed output voltage 4V < VSB_I < 6V VSB_O Output voltage deviation from programmed value 4V < VSB_I < 6V; pin FB2 connected to output capacitor VOTOL_SB -90 Average output current overall power dissipation within limit ISB_O -0.8 Output voltage at pin OCP2 IOCP2= -125μA VOCP2 1.20 1.26 1.32 V Custom over current limitation setting by current from pin OCP2 to ground ISB_OC 7000 10000 13000 IOCP2 Magnitude of default over current limitation pin OCP2 open ISB_OC_def -2.3 -1.8 -1.3 A 0.36 0.65 Ω 0.18 0.3 Ω 2.0 2.5 mS Switch on resistance high side switch of secondary buck converter RDS_ONSB_ Switch on resistance low side switch of secondary buck converter RDS_ONSB_ 1.7 V 90 mV A HS LS Voltage regulation loop transconductance 1) I(CMP2)=0 V(CMP2)=0.3 ... 2.2 V Gm Converter operating frequency information parameter fOP_SB 400 kHz Soft start slew rate SRSB_SOS 4 V/ms Control input high voltage VIH_ON2 Control input low voltage VIL_ON2 Pull down current at pin ON2 VI_ON2=28V IPD_ON2 1.5 2.4 15 V 0.95 V 40 μA 1) Internal sawtooth voltage is between 0.3 V and 2.2 V Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 12/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Electrical Characteristics (continued) (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol Control input input resistance VI_ON2<3V; Information Parameter RI_ON2 130 kΩ tON2,deb 100 µs mA Debounce time for pin ON2 Discharge current in Sleep mode V(FB2) > 1V Min Typ Max Unit IPD_SLEEP 15 30 Minimum Capacitance at the compensation network to pass internal start up self test CCMP2MIN 300 600 1000 pF Minimum pulse width without overcurrent 1) tMinimum Pulse 100 150 200 ns 30 V Width LDO1 Input voltage information param- V VIN_LDO1 eter Factory programmed output voltage V VIN_LDO1 ≥ V VOUT_LDO1 + VDropLDO1 V VOUT_LDO1 Output voltage deviation from programmed value 4V < V VIN_LDO1 < 20V VOTOL_LDO1 Output voltage drop IOUT_LDO1=-320mA VDropLDO1 Output current information parameter; power dissipa- IOUT_LDO1 tion within limit -320 -250 Over current threshold V VIN_LDO1 ≥ V VOUT_LDO1 + VDropLDO1 IOC_LDO1 -700 -450 Output voltage deviation from programmed value in low power mode 4V < V VIN_LDO1 < 20V; IOUT_LDO1 ≥ -20mA VOTOL_lp_LDO1 -3 Output current in low power state information parameter; power dissipa- IOUT_lp_LDO1 tion within limit 5 V -3 -25 -20 3 % 1 V mA -340 mA 3 % mA Over current threshold in low power V VIN_LDO1 ≥ V VOUT_LDO1 state + VDropLDO1 IOC_lp_LDO1 -90 -50 Regulator output discharge current in off state Idisc_LDO1 15 30 Output voltage threshold for indica- output voltage ristion of regulator on ing VLDO1VOUT_ 0.3 1 V Output voltage threshold for indica- output voltage falltion of regulator off ing VLDO1VOUT_ 0.1 0.5 V Output blocking capacitor CO_LDO1 10 120 μF ESR of output blocking capacitor RESR_C_O 500 mΩ 6 V V VOUT_LDO1 > 1V -30 mA mA off_r off_f LDO2-4 Input voltage information param- V VIN_LDO2-4 eter Factory programmed output voltage of LDO2 V VIN_LDO2 ≥ V VOUT_LDO2 + VDropLDO2 LDO2 output voltage deviation from programmed value 1.2 V VOUT_LDO2 VOTOL_LDO2 5 -3 V 3 % 1) not production tested Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 13/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Electrical Characteristics (continued) (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol Factory programmed output voltage of LDO3/4 V VIN_LDO3/4 ≥ V VOUT_ + VDropLDO3/4 LDO3/4 V VOUT_LDO3/4 LDO3/4 output voltage deviation from programmed value VOTOL_LDO3/4 Output current of a single LDO information parameter; power dissipa- IOUT_LDO2-4 tion within limit Output voltag drop IOUT_LDO2-4= -350mA VDropLDO2-4 Over current threshold and limitation of a single LDO V VIN_LDO2-4 - V VOUT_ ≥ 1V LDO2-4 IOC_LDO2-4 Over current threshold and limitation of LDO3 and LDO4 in parallel Regulator output discharge current in off state Min Typ Max 1.2 V -50 -450 Unit 50 -250 mV mA 0.35 V -700 -600 -500 mA V VIN_LDO34 - V VOUT_LDO34 I OC_LDO34 ≥ 1V -1800 -1250 -1000 mA V VOUT_LDO2-4 > 1V Idisc_LDO2-4 15 30 Output voltage threshold for indica- output voltage ristion of regulator on ing VLDO24VOUT_off_r 0.3 1 V Output voltage threshold for indica- output voltage falltion of regulator off ing VLDO24VOUT_off_f 0.1 0.5 V Output blocking capacitor for each single output (in parallel mode also) CLDO2-4_O 2 ESR of output blocking capacitor ESRC_LDO2-4 0.01 mA μF 10 Ω Monitoring Over voltage primary buck converter refered to measured value of VPB_O; voltage rising VPB_O_OV 1.05 1.08 1.11 VPB_O Under voltage primary buck converter refered to measured value of VPB_O; voltage falling VPB_O_UV 0.89 0.92 0.95 VPB_O Primary buck converter filter time for over and under voltage recognition (bidirectional) 1) Over voltage secondary buck converter refered to measured value of VSB_O; voltage rising VSB_O_OV 1.05 1.08 1.11 VSB_O Under voltage secondary buck converter refered to measured value of VSB_O; voltage falling VSB_O_UV 0.89 0.92 0.95 VSB_O Secondary buck converter filter time for over and under voltage recognition (bidirectional) 1) Over voltage LDO1 refered to measured value of V VOUT_ ; voltage rising LDO1 VLDO1_O_OV 1.05 refered to measured value of V VOUT_ ; voltage falling LDO1 VLDO1_O_UV 0.89 Under voltage LDO1 tPB_OVUV_filt 300 tSB_OVUV_filt μs 300 μs 1.08 1.11 V VOUT _LDO1 0.92 0.95 V VOUT _LDO1 1) Defined by design. Not subject to production test. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 14/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Electrical Characteristics (continued) (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol LDO1 filter time for over and under voltage recognition (bidirectional) 1) tLDO1_OVUV_filt Over voltage LDO2-4 refered to measured value of V VOUT_ ; voltage rising LDO2-4 Under voltage LDO2-4 Min 1.05 refered to measured value of V VOUT_ VLDO2-4_O_UV ; voltage falling LDO2-4 0.89 1) Under voltage threshold at pins VIN1A,B, voltage falling voltage falling Max 100 VLDO2-4_O_OV LDO2-4 filter time for over and under voltage recognition (bidirectional) Typ Unit μs 1.08 1.11 V VOUT _LDO2-4 0.92 0.95 V VOUT _LDO2-4 tLDO2-4_OVUV_ 100 μs filt V VIN1A,B_UV_vf 3.4 3.6 3.8 V Under voltage recovery threshold at voltage rising pins VIN1A,B, voltage rising V VIN1A,B_UV_vr 4.25 4.5 4.7 V Under voltage threshold at pins VIN2A,B, voltage falling V VIN2A,B_UV_vf 3.15 3.35 3.65 V Under voltage recovery threshold at voltage rising pins VIN2A,B, voltage rising V VIN2A,B_UV_vr 3.35 3.55 3.85 V Under voltage at pin VIO V VIO_UV 1.9 2.0 2.1 V voltage falling Debounce time for under voltage at pin VIO (bidirectional) 1) tVIO_deb 100 µs Timeout for under voltage at pin VIO 1) tVIO_tout 500 ms Supply voltage threshold for activation of internal charge pump voltage falling Supply voltage threshold for de- activation of internal charge pump voltage rising 7.8 8.4 8.9 V 8.6 9.1 9.7 V 5.9 6.2 6.6 V 0.4 V 75 kΩ CHP_on V VIN1A,B_CHP_ off Under voltage at pin CHP Low Level Output Voltage V VIN1A,B_ VCHP_UV IPGOOD=2mA VPGOOD,OUTL Internal pull up resistor RPGOOD_PU 25 Minimum watchdog time base important for safe trigger area tWD,PER,MIN 0.85 Maximum watchdog time base important for safe trigger area tWD,PER,MAX 50 Watchdog; pin RSTN AC Characteristics tWD,PER 1.15 tWD,PER First open window open window after RSTN is released tWD,FOW 230 290 ms Watchdog reset time supplier programmed tWD,RSTN 4 6 ms Disable time for LDOs supplier programmed tWD,LDO,OFF 100 ms 1) Defined by design. Not subject to production test. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 15/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Electrical Characteristics (continued) (V VIN1A,B = +5.2V to +30V, TAMB = -40°C to +105°C, unless otherwise noted. Typical values are at V VIN1A,B = +14V and TAMB = +25°C. Positive currents flow into the device pins.) Description Condition Symbol IRSTN = 2mA VRSTN,OUTL Min Typ Max Unit 0.4 V DC Characteristics Low level output voltage at pin RSTN SPI communication; pins SCK, SDI, SDO, CSN DC Characteristics High level input voltage at pin CSN VCSN,INH Low level input voltage at pin CSN VCSN,INL 0.7 V VIO 0 0.3 V VIO 1 μA 180 kΩ High level input current at pin CSN VCSN = VVIO ICSN,LEAK -1 Pull up resistor at pin CSN active mode RCSN,PU 70 High level input voltage at pin SCK VSCK,INH 0.7 Low level input voltage at pin SCK VSCK,INL Pull down resistor at pin SCK RSCK,PD 70 High level input voltage at pin SDI VSDI,INH 0.7 Low level input voltage at pin SDI VSDI,INL 0.3 V VIO Low level output voltage at pin SDO ISDO = 2mA VSDO,OUTL 0.4 V High level output voltage at pin SDO ISDO = -2mA VSDO,OUTH V VIO - 0.4 V V VIO 0.3 V VIO 180 kΩ V VIO AC Characteristics Serial clock cycle SCK, V VIO ≥ 3V 1) tSCYC 500 ns SCK "H" pulse width SCK 1) tSHW 250 ns SCK "L" pulse width SCK 1) Data setup time (WR) tSLW 250 ns SDI 1) tSDS 50 ns Data hold time SDI 1) tSDH 50 ns Access time SDO 1) tACC 100 ns Output enable time SDO 1) tOE 250 ns Output disable time SDO 1) tOD 250 ns SCK-CSN CSN tSCC 250 ns CSN "H" pulse Minimum time between two consecutive SPI accesses CSN 1) tCHW 5 us CSN-SCK time CSN 1) tCSS 125 ns IINTN = 2mA V VIO ≥ 3V VINTN,OUTL 1) Interrupt; pin INTN DC Characteristics Output low level at pin INTN Pull up resistor at pin INTN RINTN,PU 70 125 0.4 V 180 kΩ 0.4 V Fail Safe; pin FS_ON Low level output voltage at pin FS_ ON IFS_ON = 2mA VFS_ON,OUTL 1) not production tested Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 16/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6Functional Description 6.1 Power Supply Main supply (VIN1A, VIN1B) Pins VIN1A and VIN1B provide the main supply voltage of the IC. It feeds an internal voltage regulator in order to supply the internal building blocks. For V VIN1A,B_UV_vf < V VIN1A,B < V VIN1A,B_UV_vr the IC is operable, however, parameter specifications may not be fully met. Both pins are connected internally and must be connected together externally also. The supply at pins VIN1A and VIN1B must be reverse polarity protected externally. Supply the IC with an external filter in order to avoid startup failures due to properties of the external rectifier diode or even IC destruction due to a too fast rising input voltage. Regulated Supply (VDDA) The IC has an internal voltage regulator based on a bandgap reference voltage which feeds the low voltage supply for internal blocks. Pin VDDA is the regulator output. It must be buffered with an external blocking capacitor at pin VDDA. No additional external components must be connected to this supply pin. Host Interface Supply (VIO) The host interface pins have to be supplied via pin VIO, in order to ensure the correct logic signal levels. Pin VIO shall be connected to the regulator output that feeds the contoller interface. Auxiliary Internal Supply (pin CHP) A charge pump circuit provides an auxiliary supply voltage for the LDOs 2-4 in case the supply voltage is lower than the typical automotive supply case (see V VIN1A,B_CHP_ ). Otherwise the charge pump is inactive and the auxon iliary supply is derived from supply VIN1A, VIN1B. This auxiliary supply needs an external blocking capacitor at pin CHP. No additional external components must be connected to this pin. 6.2 Supplier Settings The following paragraphs describe the functionality and parameters that have been set by the supplier. Parallelization of LDOs LDO3 and 4 operate in parallel and are thus able to deliver twice the output current of a single regulator. LDO1 Always On LDO1 is programmed to be always on. It has a reduced current drive capabilitiy in power down mode. Power Up Sequence The sequence of regulator startup and the time steps between regulator starts are set by the supplier „Table 2. Parallelization and Power Up Sequencing“. LDO Discharge The LDOs are programmed to be discharged in off state (power down mode with inputs ON1/2 low or SPI command). RSTN Low The reset output RSTN remains inactive if an under voltage occurs at the output of LDO1 and in case of under voltage at the interface supply VIO. Watchdog Off for LDOs The LDOs remain active in case of a watchdog trigger reset. Over Temperature Shut Off The IC does not perform any over temperature shut off. An over temperature warning threshold is monitored and can be read from a register. Buck Converter Frequency Primary and secondary buck converters operate at the same frequency. ON1/2 Transition A low level at the ON1/2 pins is regarded active high after power on, as long as these pins have not changed to a high level yet, i.e. the IC is forced to start in active mode. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 17/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.3 Operation States Supply Application If the main supply at pins VIN1A and VIN1B is applied, an internal regulator starts to deliver a 3.3V supply, which is blocked externally at pin VDDA. The control circuitry is reset by a power on reset signal and all supplier settings are activated. Pins ON1 and ON2 determine the subsequent IC states. state with minimum current consumption from pins VIN1A,B. LDO1 remains active all the time. The main supply voltage at VIN1A,B must be higher than 7V in order to maintain the power down current consumption. If the main supply is lower, additional internal circuitry will be activated in order to report the failure with increased current consumption. Power Down If neither of the regulators is requested to be active (pins ON1 and ON2 low), the IC is in power down Digital Interface in Power Down The subsequent table lists the functionality of the digital interface in power down state. Table 1. Digital Interface in Power Down Output RSTN INTN PGOOD FS_ON CSN SCK SDI SDO FOSC TST ON1/2 Functionality No active low level No active output level; internal pull up to VIO supply No active low level; internal pull up to VIO supply No active low level except in case of under voltage at the main supply VIN1A/B Pull up and SPI interface de- activated in sleep mode an in case of under voltage at interface supply VIO Pull down; SPI interface de- activated in case of under voltage at interface supply VIO SPI interface de- activated in case of under voltage at interface supply VIO No active output level Pull down Pull down Pull down System Activation If inputs ON1 or ON2 are in on-state, the respective buck converter starts operation immediately after activation of all auxiliary blocks in the IC. If inputs ON1 and ON2 are set to on-state at the same instant, the secondary buck converter starts operation immediately after the primary buck converter has reached its nominal output voltage. After power on the ON1 and ON2 pin values are assumed to have high level as long as no actual high level is applied to the pin. For a transition to the power down state the pins need a voltage change from high to low level. If the buck converters which are requested to operate have reached their nominal output voltage with all under voltage flags inactive, the LDO section is enabled. LDO2 starts after LDO3/4 have reached their nominal output voltage. An eventually occurring over voltage condition will have no impact on the startup sequence. A delay of tPWRS * mPWRS is inserted between full operation of each regulator and the activation of the subsequent one see „Delay Time Parameters“. Output PGOOD is set to high level, if all requested buck converters and voltage regulators operate with all overand undervoltage flags inactive. Regulator LDO1 is active all the time with different output current capability in active and in low power mode. Activation of the buck converters is not necessary for its operation. Power Sequencing The subsequent table lists the power sequencing steps. If only one of the buck converters is activated, only this one is prerequisite for activation of the LDO section. The activation of LDOs 3 and 4 in the same step is performed in an own sub- sequence with LDO3 first, LDO4 afterwards in a time step of tPWRS. For power down sequencing the power up sequencing described in „Table 2. Parallelization and Power Up Sequencing“ is used in reverse direction. If the normal delay time is not sufficient to guarantee that the previous regulator output voltage is close to zero, switching off the next regulator is further delayed until this condition is met. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 18/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 2. Parallelization and Power Up Sequencing Configuration LDO 2 separate, LDOs 3 and 4 in parallel Step0 Step1 bucks on; LDO 1 on; buck converters indicate normal LDOs 3 & 4 operation Delay Time The delay time between all power sequencing steps is set with a factor of mPWRS of the minimum delay time tPWRS. For the parallel operation of LDOs 3 and 4 there is the minimum delay time tPWRS between switching on the LDOs. All regulators will continue to operate in case of a watchdog reset. Regulators may be de- and re- activated via SPI. The power up sequencing (see „Table 2. Parallelization and Power Up Sequencing“) is not valid in this case. On re- activation of regulators pin PGOOD will be set to low level temporarily for the startup time of the re- activated regulator in order to indicate a successful state change. All other active regulators maintain their operation status. Step2 LDO 2 Buck Converter Clock The buck converters are controlled by the same internal oscillator clock. Both converters operate phase synchronously. Converters can be controlled via an external clock signal at pin FOSC. Over Current Limitation All buck converters and LDOs limit their output current by default. The buck converter over current limits can be set to a different value by resistors between pins OCP1, OCP2 and ground. Temperature Surveillance The junction temperature of the IC is monitored in active mode. If the temperature reaches the over temperature warn threshold TJ,warn a warning is signaled via interrupt pin INTN and can be read via SPI. The IC will not perform any over temperature shut off. 6.4 Buck Converter Oscillator An internal oscillator provides the clock for the whole IC. The switching clock for the buck converters is derived from it by frequency division. The buck converter operating frequency is set to 400 kHz. Alternatively an external clock can be applied at pin FOSC. In order to guarantee a 50% duty cycle, the ex- 8 MHz F CLK ternally applied clock is divided by two internally. Pin FOSC should be connected to GND if not used in the application. The two buck converters operate at the same clock frequency. N [10..40] 1 FOP_PB N Monitor FOSC 1 FOP_SB 2 Figure 1. Selection of buck converter frequency Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 19/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.5 Primary Buck Converter Figure 2. Block Schematic of Primary Buck Converter Topology The primary buck converter is supplied by the externally reverse polarity protected main supply voltage at pins VIN1A and VIN1B. Both pins are connected internally and must be connected together externally also. An internal high side switch delivers current to an external inductor and an external diode provides a current path between ground and converter outputs SW1A and SW1B. Both pins are connected internally and must also be connected together externally. The feedback pin FB1 must be connected to the regulator output capacitor. The ground pin PGND1 must be connected to the system ground plane. The converter is activated with a high level at pin ON1. An external resistor between pin OCP1 and ground sets the over current limit. Pin CMP1 is the interface for external components for loop compensation. The output voltage is factory programmed. Output over and under voltage and over current are monitored and stored in a register. A fast external freewheeling diode with a reverse recovery time of <50ns is necessary. A Schottky type is recommended. Soft start is implemented for a typical startup slope. The converter is typically driven by an internally generated clock. Alternatively an external clock can be applied to pin FOSC. Since loss of the feedback connection and loss of the compensation network may cause damage not only to the IC but also to other circuitry two safety functions are implemented. During startup an internal self test is performed to ensure that the compensation network is connected. The start up is cancelled if the CMP1 pin has a short to VDDA or the connected capacitance is smaller than the threshold value. Additionally, the buck converter does not switch if the FB1 pin is ripped off. A small current forces FB1 to VIN1A/B until FB1 reaches approximately 103% of the expected output voltage. The buck converter will continue operation even if there is no diode connected between ground and converter outputs SW1A and SW1B. This operation mode, however, bears the risk of damaging the IC. Thus the customer must measure a sufficiently low voltage drop across the external diode in an end of line test on the final board. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 20/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 3. Primary Buck Registers Register Name PB Status PB Control PB INT Address 0x01 0x02 0x31 Description Primary Buck Converter Status Register Primary Buck Converter Control Register Primary Buck Interrupt register Table 4. Primary Buck Converter Status Register PB Status (0x01) MSB Content Reset Value Access OC OV UV ON 1 0 0 0 0 0 0 0 R/W R R R R R R R OC : This Bit is set to '1' when the converter is switched on and an overcurrent is detected. OV : This Bit is set to '1' when the converter is switched on and an overvoltage is detected. UV : This Bit is set to '1' when the converter is switched on and an undervoltage is detected. ON : This bit represents the state of the pin ON1. Bit is set to '1' when pin ON1 is high and '0' when pin ON1 is low. Bit Description LSB Table 5. Primary Buck Converter Control Register PB Control (0x02) MSB Content Reset Value Access EN_INT2 EN_INT1 EN_OC 1 0 1 1 1 R/W R/W R/W R/W R/W EN_INT2 : interrupt enable for INT2 0..disabled 1..enabled EN_INT1 : interrupt enable for INT1 0..disabled 1..enabled EN_OC : interrupt enable for overcurrent 0..disabled 1..enabled EN_OV : interrupt enable for overvoltage 0..disabled 1..enabled EN_UV : interrupt enable for undervoltage 0..disabled 1..enabled Bit Description LSB EN_OV 1 R/W EN_UV 1 R/W 0 R Table 6. Primary Buck Interrupt Register PB INT (0x31) MSB Content Reset Value Access INT2 INT1 OC OV UV 0 0 0 0 0 0 0 0 R R R/W R/W R/W R/W R/W R INT2 : This bit indicates an internal buck start failure. INT1 : This bit indicates an internal buck start failure. OC : This Bit is set to '1' when a overcurrent condition occured and cleared by writing a '1' to the bit. OV : This Bit is set to '1' when a overvoltage condition occured and cleared by writing a '1' to the bit. UV : This Bit is set to '1' when a undervoltage condition occured and cleared by writing a '1' to the bit. Bit Description LSB Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 21/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.6 Secondary Buck Converter Figure 3. Block Schematic of Secondary Buck Converter Topology The secondary buck converter is typically supplied by the primary buck converter output voltage at pins VIN2A and VIN2B. Both pins are connected internally and must be connected externally. An internal high side switch delivers current to an external inductor and an internal low side switch provides a current path between ground and converter outputs SW2A and SW2B. Both pins are connected internally and must be connected together externally also. The feedback pin FB2 shall be connected to the regulator's output capacitor. The ground pins PGND2 and PGND3 must be connected to the system ground plane. An external resistor between pin OCP2 and ground sets the over current limit. Pin CMP2 is the interface for external components for loop compensation. The output voltage is factory programmed. Output over and under voltage and over current are monitored and stored in a register. Soft start is implemented for a typical startup slope. In a typical configuration the secondary buck converter is supplied by the primary buck converter and starts op- eration after the primary buck converter has reached its nominal output voltage. If the primary buck converter is not used and the secondary buck converter is activated with a high level at pin ON2 alone, a separate input source is expected and operation starts, if the input voltage is higher than the input under voltage threshold. The converter is driven by the same internally generated clock which is used for the primary buck converter. Since loss of the feedback connection and loss of the compensation network may cause damage not only to the IC but also to other circuitry two safety functions are implemented. During startup an internal self test is performed to ensure that the compensation network is connected. The start up is cancelled if the CMP2 pin has a short to VDDA or the connected capacitance is smaller than the threshold value. Additionally, the buck converter does not switch if the FB2 pin is ripped off. A small current forces FB2 to the VIN2A/B input until FB2 reaches the over voltage threshold. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 22/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 7. Secondary Buck Registers Register Name PB Status PB Control PB INT Address 0x03 0x04 0x32 Description Secondary Buck Converter Status Register Secondary Buck Converter Control Register Secondary buck interrupt register Table 8. Secondary Buck Converter Status Register SB Status (0x03) MSB Content Reset Value Access OC OV UV ON 0 0 0 0 0 0 0 0 R R R R R R R R OC : This Bit is set to '1' when the converter is switched on and an overcurrent is detected. OV : This Bit is set to '1' when the converter is switched on and an overvoltage is detected. UV : This Bit is set to '1' when the converter is switched on and an undervoltage is detected. ON : status pin ON2 This bit represents the status of pin ON2. Bit is set to '1' when pin ON2 is high and '0' when pin ON2 is low. Bit Description LSB Table 9. Secondary Buck Converter Control Register SB Control (0x04) MSB Content Reset Value Access EN_CDIR EN_INT2 EN_INT1 EN_OC 1 0 1 1 1 R/W R/W R/W R/W R/W EN_CDIR : enable current direction detection 0..disabled 1..enabled EN_INT2 : interrupt enable for INT2 0..disabled 1..enabled EN_INT1 : interrupt enable for INT1 0..disabled 1..enabled EN_OC : interrupt enable for overcurrent 0..disabled 1..enabled EN_OV : interrupt enable for overvoltage 0..disabled 1..enabled EN_UV : interrupt enable for undervoltage 0..disabled 1..enabled Bit Description LSB EN_OV 1 R/W EN_UV 1 R/W 0 R Table 10. Secondary Buck Interrupt Register SB INT (0x32) MSB Content Reset Value Access INT2 INT1 OC OV UV 0 0 0 0 0 0 0 0 R R R R R/W R/W R/W R INT2 : This bit indicates an internal buck start failure. INT1 : This bit indicates an internal buck start failure. OC : This Bit is set to '1' when a overcurrent condition occured and cleared by writing a '1' to the bit. OV : This Bit is set to '1' when a overvoltage condition occured and cleared by writing a '1' to the bit. UV : This Bit is set to '1' when a undervoltage condition occured and cleared by writing a '1' to the bit. Bit Description LSB Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 23/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.7 LDO1 Topology LDO1 is a linear low drop regulator with output current limitation. The regulator is activated as described in chapter „6.3 Operation States“. The output voltage is factory programmed. The regulator output is discharged in its off state. LDO1 can be operated during power down with a reduced internal supply current consumption. The maximum available output current is decreased and the response times in case of line and load fluctuations are increased in this state. Table 11. LDO1 Register Table Register Name LDO1 STAT LDO1 Config LDO1 INT Address 0x10 0x11 0x33 Description Status Register of LDO1 Config Register of LDO1 LDO1 interrupt register Table 12. Status Register of LDO1 LDO1 STAT (0x10) MSB Content Reset Value Access CHP_UV OC OV UV ON 0 0 0 0 0 0 0 0 R R R R R R R R CHP_UV : Failure in auxiliary voltage generation. OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detected. OV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detected. UV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detected. ON : This Bit is set to '1' when the LDO1 is enabled. Bit Description LSB Table 13. Config Register of LDO1 LDO1 Config (0x11) MSB Content Reset Value Access EN_OC 0 0 0 0 1 R R R R R/W EN_OC : Bit 3 - enable for overcurrent interrupt 0..disabled 1..enabled EN_OV : Bit 1 - enable for overvoltage interrupt 0..disabled 1..enabled EN_UV : Bit 1 - enable for undervoltage interrupt 0..disabled 1..enabled ON : Bit 0 - regulator enable 0..disabled 1..enabled Bit Description LSB EN_OV 1 R/W EN_UV 1 R/W ON 1 R/W Table 14. LDO1 Interrupt Register LDO1 INT (0x33) MSB Content Reset Value Access OC OV UV 0 0 0 0 0 0 0 0 R R R R R/W R/W R/W R OC : This Bit is set to '1' when an overcurrent status change occured and cleared by writing a '1' to the bit. OV : This Bit is set to '1' when an overvoltage status change occured and cleared by writing a '1' to the bit. UV : This Bit is set to '1' when an undervoltage status change occured and cleared by writing a '1' to the bit. Bit Description LSB Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 24/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.8 LDO2-4 Topology LDOs 2-4 are linear low drop regulators with output current limitation. They are intended to be operated from the output of the secondary buck converter and are activated in the order described in chapter „6.3 Operation States“. In case the secondary buck converter is not requested to be active, LDOs 2-4 expect other in- put sources according to the maximum ratings specification. The output voltage is factory programmed. The outputs of LDOs 2-4 are discharged to ground in their off state. Table 15. LDO2..LDO4 Register Table Register Name LDO2 Status LDO2 Config LDO3 Status LDO3 Config LDO4 Status LDO4 Config LDO2 INT LDO3 INT LDO4 INT Address 0x12 0x13 0x14 0x15 0x16 0x17 0x34 0x35 0x36 Description Status Register of LDO2 Config Register of LDO2 Status Register of LDO3 Config Register of LDO3 Status Register of LDO4 Config Register of LDO4 LDO2 interrupt register LDO3 interrupt register LDO4 interrupt register Table 16. Status Register of LDO2 LDO2 Status (0x12) MSB Content Reset Value Access CHP_UV OC OV UV ON 0 0 0 0 0 0 0 0 R R R R R R R R CHP_UV : Failure in auxiliary voltage generation. OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detected. OV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detected. UV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detected. ON : This Bit is set to '1' when LDO2 is enabled and reset to '0' whe the LDO2 is disabled. Bit Description LSB Table 17. Config Register of LDO2 LDO2 Config (0x13) MSB Content Reset Value Access EN_OC 0 0 0 0 1 R R R R R EN_OC : interrupt enable for overcurrent 0..disabled 1..enabled EN_OV : interrupt enable for overvoltage 0..disabled 1..enabled EN_UV : interrupt enable for undervoltage 0..disabled 1..enabled ON : regulator enable 0..disabled 1..enabled Bit Description LSB EN_OV 1 R EN_UV 1 R/W ON 1 R/W Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 25/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 18. Config Register of LDO2 LDO2 Config (0x13) MSB Content Reset Value Access EN_OC 0 0 0 0 1 R R R R R EN_OC : interrupt enable for overcurrent 0..disabled 1..enabled EN_OV : interrupt enable for overvoltage 0..disabled 1..enabled EN_UV : interrupt enable for undervoltage 0..disabled 1..enabled ON : regulator enable 0..disabled 1..enabled Bit Description LSB EN_OV 1 R EN_UV 1 R/W ON 1 R/W Table 19. LDO2 Interrupt Register LDO2 INT (0x34) MSB Content Reset Value Access OC OC UV 0 0 0 0 0 0 0 0 R R R R R/W R/W R/W R OC : This Bit is set to '1' when an overcurrent status change occured and cleared by writing a '1' to the bit. OV : This Bit is set to '1' when an overvoltage status change occured and cleared by writing a '1' to the bit. UV : This Bit is set to '1' when an undervoltage status change occured and cleared by writing a '1' to the bit. Bit Description LSB Table 20. Status Register of LDO3 LDO3 Status (0x14) MSB Content Reset Value Access CHP_UV OC OV UV ON 0 0 0 0 0 0 0 0 R R R R R R R R CHP_UV : Failure in auxiliary voltage generation. OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detected. OV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detected. UV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detected. ON : This Bit is set to '1' when LDO3 is enabled and reset to '0' whe LDO3 is disabled. Bit Description LSB Table 21. Config Register of LDO3 LDO3 Config (0x15) MSB Content Reset Value Access EN_OC 0 0 0 0 1 R R R R R EN_OC : interrupt enable for overcurrent 0..disabled 1..enabled EN_OV : interrupt enable for overvoltage 0..disabled 1..enabled EN_UV : interrupt enable for undervoltage 0..disabled 1..enabled ON : regulator enable 0..disabled 1..enabled Bit Description LSB EN_OV 1 R EN_UV 1 R/W ON 1 R/W Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 26/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 22. LDO3 Interrupt Register LDO3 INT (0x35) MSB Content Reset Value Access OC OV UV 0 0 0 0 0 0 0 0 R R R R R/W R/W R/W R OC : This Bit is set to '1' when an overcurrent status change occurred and cleared by writing a '1' to the bit. OV : This Bit is set to '1' when an overvoltage status change occurred and cleared by writing a '1' to the bit. UV : This Bit is set to '1' when an undervoltage status change occurred and cleared by writing a '1' to the bit. Bit Description LSB Table 23. Status Register of LDO4 LDO4 Status (0x16) MSB Content Reset Value Access CHP_UV OC OV UV ON 0 0 0 0 0 0 0 0 R R R R R R R R CHP_UV : Failure in auxiliary voltage generation. OC : This Bit is set to '1' when the LDO is switched on and an overcurrent is detected. OV : This Bit is set to '1' when the LDO is switched on and an overvoltage is detected. UV : This Bit is set to '1' when the LDO is switched on and an undervoltage is detected. ON : This Bit is set to '1' when LDO4 is enabled and reset to '0' whe the LDO4 is disabled. Bit Description LSB Table 24. Config Register of LDO4 LDO4 Config (0x17) MSB Content Reset Value Access EN_OC 0 0 0 0 1 R R R R R EN_OC : interrupt enable for overcurrent 0..disabled 1..enabled EN_OV : interrupt enable for overvoltage 0..disabled 1..enabled EN_UV : interrupt enable for undervoltage 0..disabled 1..enabled ON : regulator enable 0..disabled 1..enabled Bit Description LSB EN_OV 1 R EN_UV 1 R/W ON 1 R/W Table 25. LDO4 Interrupt Register LDO4 INT (0x36) MSB Content Reset Value Access OC OV UV 0 0 0 0 0 0 0 0 R R R R R/W R/W R/W R OC : This Bit is set to '1' when an overcurrent status change occurred and cleared by writing a '1' to the bit. OV : This Bit is set to '1' when an overvoltage status change occurred and cleared by writing a '1' to the bit. UV : This Bit is set to '1' when an undervoltage status change occurred and cleared by writing a '1' to the bit. Bit Description LSB Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 27/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.9 Monitoring The main supply (pins VIN1A,B), the host interface supply (VIO), the supply for the secondary buck regulator (VIN2A,B), the auxiliary supply (CHP), the regulator outputs and the chip temperature are monitored. Failure conditions can be read via SPI in the respective status registers. Moreover, as soon as all regulator outputs that are requested to be active have reached their nominal output voltage with all under and over voltage flags inactive, output PGOOD indicates this condition instantaneously with a high level. Supply Monitoring In case the supply falls below the V VIN1A,B range, the IC remains operable, however, parameter specifications may not be fully met. If the supply voltage decreases further below V VIN1A,B_UV_vf (power fail), the regulated supply VDDA may fall below V VDDA_UV. In this case a power-on reset circuit generates a reset to the circuit control logic. With the logic in reset state output FS_ON is active low, all IC outputs are disabled. Output RSTN remains inactive in this case. In power down state no supply monitoring is performed. The subsequent table lists the IC responses in case of failure conditions. Table 26. Monitoring Table Monitor VIN1A,B under voltage VIN1A,B under voltage VIN1A,B under voltage Operation FS_ON Mode RSTN Interrupt PGOOD Regulators Watchdog normal active low - - - off except LDO1 - sleep active low - - - - - active low - - - - - - - - active low Buck2 off - sleep with LDO1 on VIN2A,B under normal, buck2 enavoltage bled VDDA under voltage - VIO under volt- normal age active low - - - all regulators off; reset of all reset configuration settings - - - - LDO2-4 are not switched on (if on they are not switched off) CHP under voltage normal - - - - LDO1 under voltage LDO1 under voltage BUCK1-2, LDO1-4, over current BUCK1-2, LDO1-4, over voltage BUCK1-2, LDO2-4, under voltage over temperature warning watchdog fail normal - - yes active low - sleep with LDO1 on - - yes active low if VIO applied - normal - - yes - - - normal - - yes active low - - normal - - yes active low - - normal - - yes - - - normal active low - yes - - reset Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 28/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.10 Watchdog; Pin RSTN) The design implements a watchdog functionality that can be used in window or timeout mode. The watchdog starts operation if V VIO > V VIO_UV. 6.11 Time Out Mode The time out mode is an easier and less secure type of the watchdog modes. A closed window does not exist. The watchdog trigger can be applied any time within the watchdog cycle. Writing the correct trigger value to register „WD_TRIG (0x22)“ starts a new window period. Alternating triggers must be used. In case of an incorrect watchdog trigger the watchdog will generate a watchdog reset. In case of a watchdog reset the open drain pin RSTN is set to low and the corresponding bit in register „WD_ STAT (0x21)“ is set. Pin RSTN needs an external pull up device in order to deliver a logical high level. Figure 4. Watchdog time out mode Figure 5. Watchdog time out mode without trigger Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 29/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.12 Window Mode The window mode is the secure type of the watchdog modes. It consists of a closed and an open window. A closed window is 50% of the configured watchdog period. Triggering the watchdog is allowed in the open window only.Writing the correct trigger value to register WD_TRIG starts a new window period. Alternating triggers must be used. In case of an incorrect watchdog trigger the watchdog will generate a watchdog reset. In case of a watchdog reset the open drain pin RSTN is set to low and the corresponding bit in register WD_ STAT is set. Pin RSTN needs an external pull up device in order to deliver a logical high level. Figure 6. Watchdog window mode Figure 7. Watchdog window mode no trigger Behaviour of watchdog in case of missing trigger in open window. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 30/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Figure 8. Watchdog window mode trigger in closed window Behaviour of watchdog in case of missing trigger in open window. Figure 9. Watchdog window mode no trigger in open window Behaviour of watchdog in case of missing trigger in open window. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 31/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Figure 10. Watchdog window mode wrong trigger in open window Behaviour of watchdog in case of wrong trigger in open window. Figure 11. Safe trigger area 6.13 Configuration The period can be configured in register „WD_PER_CFG (0x23)“ in the range from 4ms up to 1024ms using formula 4ms*(1+PER[7:0]). The first period always starts with 256ms. Trigger values A and B must be sent alternately. The first trigger byte must be trigger value A. Registers „WD_CFG (0x20)“ and „WD_PER_CFG (0x23)“ can be written and read any time. The content of „WD_ CFG (0x20)“ and „WD_PER_CFG (0x23)“ is activated by writing an activation trigger value to the „WD_TRIG (0x22)“ register. Register „WD_STAT (0x21)“WD_STAT is updated from „WD_CFG (0x20)“, register „WD_PER_ STAT (0x24)“WD_PER_STAT from „WD_PER_CFG (0x23)“. Any invalid trigger value results in a watchdog reset. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 32/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 27. Watchdog Register Table Register Name WD_CFG WD_STAT WD_TRIG WD_PER_CFG WD_PER_STAT Address 0x20 0x21 0x22 0x23 0x24 Description Watchdog configuration. Watchdog status register (active configuration) Watchdog trigger register Watchdog period configuration Status of watchdog period (active configuration) Table 28. Watchdog Configuration WD_CFG (0x20) MSB Content Reset Value Access 0 0 0 0 R R R R SWDM : Software development mode 1...software development mode enabled 0...software development mode disabled MODE : Watchdog mode 1...time out mode 0...window mode Bit Description LSB 0 R 0 R SWDM 0 R/W MODE 1 R/W Table 29. Watchdog Status Register (Active Configuration) WD_STAT (0x21) MSB Content Reset Value Access WDRSTN SWDM MODE 0 0 0 0 0 0 0 0 R R R R R R R R WDRSTN : Watchdog reset 1...watchdog failure event occured 0...no watchdog failure event occured The bit is reset by updating the configuration registers (sending an update trigger). SWDM : Software development mode 1...software development mode enabled 0...software development mode disabled MODE : Watchdog mode 1...time out mode 0...window mode Bit Description LSB Table 30. Watchdog Trigger Register WD_TRIG (0x22) MSB LSB Content Reset Value Access Bit Description TRIG[7] TRIG[6] TRIG[5] TRIG[4] TRIG[3] TRIG[2] TRIG[1] TRIG[0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TRIG[7] : Watchdog trigger value (alternating content according to following table) Table 31. Watchdog Period Configuration WD_PER_CFG (0x23) MSB Content Reset Value Access Bit Description LSB PER[7] PER[6] PER[5] PER[4] PER[3] PER[2] 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W PER[7] : Bit 7 .. 0: watchdog period configuration value PER[1] 1 R/W PER[0] 1 R/W Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 33/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 32. Status of Watchdog Period (Active Configuration) WD_PER_STAT (0x24) MSB Content Reset Value Access Bit Description LSB PER[7] PER[6] PER[5] PER[4] PER[3] 0 0 1 1 1 R R R R R PER[7] : Bit 7 .. 0: watchdog period status value PER[2] 1 R PER[1] 1 R PER[0] 1 R Table 33. Valid Watchdog Trigger Values Value 0x65 0x6a 0x95 0x9a any other Trigger Event trigger A trigger B trigger A trigger B invalid trigger Register Update no register update no register update config register content activated config register content activated no register update 6.14 SPI Communication; Pins SCK, SDI, SDO, CSN The SPI interface is used for: • status information for over- and under voltages, on-status, over currents, over temperature warning • watchdog configuration (time) and trigger via SPI By setting CSN to low level, the communication can be enabled and setting it to high level disables the communication (in this case, pin SDO is high impedance). Data shifts are controlled by the serial clock signal (SCK) dur- ing the transmission according to the following rules: • data is shifted MSB first, LSB last • data is shifted out on the rising edge of SCK and is sampled on the falling edge of SCK • data transmission length is always 16 Bit SPI write is performed setting MSB Bit RW of address value to 1. During read Bit RW needs to be 0. The pull up for pin CSN is de- activated in sleep mode. Figure 12. SPI access Bit RW • 1: write access • 0: read accessdur Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 34/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Figure 13. SPI Timing diagram SPI timing diagram. For configuration of write and read access check corresponding diagrams. 6.15 Interrupt; Pin INTN The interrupt pin is driven low if the following interrupt sources/conditions occur: • over temperature warning • undervoltage at LDO1..4, PB, SB • overvoltage at LDO1..4, PB, SB • overcurrent at LDO1..4, PB, SB • internal failures Interrupts can be enabled in configuration registers of the corresponding modules. For over temperature warning, under/over voltage and current the appearance and disappearance is signalled via an interrupt. The interrupt is cleared by writing the corresponding status register, „Figure 14. Interrupt and Status Register Dependency“ . During startup of the IC and after sleep mode deactivation the IC checks its configuration. In case of detection of a configuration failure an interrupt is raised and additional failure information is provided in the internal interrupt register. In case of a severe failure the IC is sent to a failsafe mode with all voltage sources are switched off and RSTN and FS_ON are driven to low level. Table 34. INTN Register Table Register Name INT BIST INT_EN OT_STAT Address 0x30 0x37 0x38 0x39 Description Interrupt status register Internal failure register Enable register for over temperature and BIST interrupts Over temperature status register Table 35. Interrupt Status Register INT (0x30) MSB LSB Content Reset Value Access LDO4 LDO3 LDO2 LDO1 SB PB BIST 0 0 0 0 0 0 0 R R R R R R R LDO4 : 1: A LDO4 event is reason for interrupt LDO3 : 1: A LDO3 event is reason for interrupt LDO2 : 1: A LDO2 event is reason for interrupt LDO1 : 1: A LDO1 event is reason for interrupt SB : 1: A secondary buck event is reason for interrupt PB : 1: A primary buck event is reason for interrupt BIST : 1: An internal startup interrupt occured OTW : 1: An overtemperature warning level crossing is reason for interrupt OTW 0 R/W Bit Description Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 35/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 Table 36. Internal Failure Register BIST (0x37) MSB Content Reset Value Access INT3 INT2 0 0 0 0 0 0 R R R R R R INT3 : The bit reflects the state of an internal startup failure. INT2 : The bit reflects the state of an internal startup failure. INT1 : The bit reflects the state of an internal startup failure. INT0 : The bit reflects the state of an internal startup failure. Bit Description LSB INT1 0 R INT0 0 R Table 37. Enable Register for Over Temperature and BIST Interrupts INT_EN (0x38) MSB Content Reset Value Access 0 0 0 0 0 R R R R R BIST_EN : enable for BIST interrupt 0..disabled 1..enabled OT_EN : enable for over temperature interrupt 0..disabled 1..enabled Bit Description LSB 0 R BIST_EN 1 R/W OT_EN 1 R/W Table 38. Over Temperature Status Register OT_STAT (0x39) MSB LSB Content Reset Value Access Bit Description 0 0 0 0 R R R R OT_W : over temperature warning 0 R 0 R 0 R OT_W 0 R Figure 14. Interrupt and Status Register Dependency In case of interrupt detailed information can be read from the device in order to evaluate the reason for interrupt. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 36/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 6.16 Fail Safe; Pin FS_ON Pin FS_ON is released and can be set to high level by an external pull up resistor after the reception of three valid watchdog trigger pulses after output RSTN had been released. The reason for a fail safe condition is stored in „FS_ON status register (0x25)“. It is recommended to read FS_ON status register after every start up. Table 39. FS_ON Status Register Register Name FS_ON status register Address 0x25 Description FS_ON Status Register Table 40. FS_ON Status Register FS_ON status register (0x25) Content Reset Value Access Bit Description MSB LSB BIST 0 0 0 0 R R R R BIST : BIST failed (internal failure) VIN : under voltage at pin VIN1A or VIN1B VIO : VIO time out exceeded WD : Watchdog reset OT : Over temperatur shut down occured VIN 0 R VIO 0 R WD 0 R OT 0 R 7Register Table Table 41. Register Table Register Name PB Status PB Control SB Status SB Control LDO1 STAT LDO1 Config LDO2 Status LDO2 Config LDO3 Status LDO3 Config LDO4 Status LDO4 Config WD_CFG WD_STAT WD_TRIG WD_PER_CFG WD_PER_STAT FS_ON status register INT PB INT SB INT LDO1 INT LDO2 INT LDO3 INT LDO4 INT BIST INT_EN OT_STAT Address 0x01 0x02 0x03 0x04 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x20 0x21 0x22 0x23 0x24 0x25 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 Description Primary Buck Converter Status Register Primary Buck Converter Control Register Secondary Buck Converter Status Register Primary Buck Converter Control Register Status Register of LDO1 Config Register of LDO1 Status Register of LDO2 Config Register of LDO2 Status Register of LDO3 Config Register of LDO3 Status Register of LDO4 Config Register of LDO4 Watchdog Configuration Watchdog Status Register (Active Configuration) Watchdog Trigger Register Watchdog Period Configuration Status of Watchdog Period (Active Configuration) FS_ON Status Register Interrupt Status Register Primary Buck Interrupt Register Secondary Buck Interrupt Register LDO1 Interrupt Register LDO2 Interrupt Register LDO3 Interrupt Register LDO4 Interrupt Register Internal Failure Register Enable Register for Over Temperature and BIST Interrupts Over Temperature Status Register Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 37/40 QM-No.: 25DS0121E.01 DUAL BUCK - QUAD LDO PACKAGE Date: 04.02.2013 PRODUCTION DATA - MAR 9, 2016 8Package Information Author: ASto E522.51 OUTLINE SPECIFICATION 48 Lead Quad Flat Non Leaded Package QM-No.: 08SP0644.02 All devices are available in a Pb free, RoHs compliant QFN48L7 plastic package according to JEDEC MO-220 K, vari(QFN48L7) ant VKKD-6. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a Package peak Outline and Dimensions are according JEDEC MO-220 K, variant VKKD-6, except reduced soldering temperature of (260+5)°C. terminal length of 0.4mm. Description Symbol min mm typ max min inch typ max A 0.80 0.90 1.00 0.031 0.035 0.039 Stand off A1 0.00 0.02 0.05 0.000 0.00079 0.002 Thickness of terminal leads, including lead finish A3 -- 0.20 REF -- -- 0.0079 REF -- b 0.18 0.25 0.30 0.007 0.010 0.012 Package height Width of terminal leads D/E -- 7.00 BSC -- -- 0.276 BSC -- D2 / E2 4.60 4.75 4.90 0.181 0.187 0.193 e -- 0.5 BSC -- -- 0.020 BSC -- Length of terminal for soldering to substrate L 0.35 0.4 0.45 0.014 0.016 0.018 Number of terminal positions N Package length / width Length / width of exposed pad Lead pitch 48 48 Note: the mm values are valid, the inch values contains rounding errors Note 1: for assembler specific pin1 identification please see QM-document 08SP0363.xx (Pin 1 Specification) Page 1 of 1 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 38/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 9Marking 9.1 Top Side ÿÿ ÿÿ ÿÿ ÿÿ Elmos (Logo) E52251A XXXXU YWW*# Signature 52251 E A Y WW * # XXXX U Explanation Elmos project number Volume production Elmos project revision code Year of Assembly Week of Assembly Mask Revision Code Mask Revision Code Production Lot Number Assembler Code Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet 39/40 QM-No.: 25DS0121E.01 E522.51 DUAL BUCK - QUAD LDO PRODUCTION DATA - MAR 9, 2016 WARNING – Life Support Applications Policy Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. 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Elmos Semiconductor AG reserves the right to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability. Application Disclaimer Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos Semiconductor AG or others. Contact Information Headquarters Elmos Semiconductor AG Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany) : +492317549100 : sales-germany@elmos.com Sales and Application Support Office North America Elmos NA. Inc. 32255 Northwestern Highway • Suite 220 Farmington Hills MI 48334 (USA) : +12488653200 : sales-usa@elmos.com Sales and Application Support Office China Elmos Semiconductor Technology (Shanghai) Co., Ltd. Unit 16B, 16F Zhao Feng World Trade Building, No. 369 Jiang Su Road, Chang Ning District, Shanghai, PR China, 200050 : +86216210 0908 : sales-china@elmos.com Sales and Application Support Office Korea Elmos Korea B-1007, U-Space 2, #670 Daewangpangyo-ro, Sampyoung-dong, Bunddang-gu, Sungnam-si Kyounggi-do 463-400 Korea : +82317141131 : sales-korea@elmos.com Sales and Application Support Office Japan Elmos Japan K.K. BR Shibaura N Bldg. 7F 3-20-9 Shibaura, Minato-ku, Tokyo 108-0023 Japan : +81334517101 : sales-japan@elmos.com Sales and Application Support Office Singapore Elmos Semiconductor Singapore Pte Ltd. 3A International Business Park #09-13 ICON@IBP • 609935 Singapore : +65 6908 1261 : sales-singapore@elmos.com : www.elmos.com © Elmos Semiconductor AG, 2016. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited. Elmos Semiconductor AG Data Sheet 40/40 QM-No.: 25DS0121E.01
