www.ietdl.org
Published in IET Microwaves, Antennas & Propagation
Received on 12th May 2013
Revised on 25th September 2013
Accepted on 2nd October 2013
doi: 10.1049/iet-map.2013.0241
ISSN 1751-8725
Complementary metal-oxide semiconductor Doherty
power amplifier based on voltage combining method
Chenxi Zhao, Byungjoon Park, Bumman Kim
Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Gyeongbuk
790-784, Republic of Korea
E-mail: cxzhao@postech.ac.kr
Abstract: A 1.75 GHz Doherty power amplifier (PA) is designed and implemented in a 0.18-µm complementary metal-oxide
semiconductor (CMOS) process. This Doherty PA uses a voltage combining transformer to combine the output power and
realise the load modulation which is different from conventional current combining Doherty amplifiers. The prototype has a
power-added efficiency (PAE) of 31.6% at a maximum output power of 28.6 dBm from 3.4 V supply voltage. The PAE at 6
dB back-off is still high, about 25%. It shows clearly the efficiency enhancement at the power back-off point because of the
Doherty operation. This is the first use of voltage combining techniques in CMOS Doherty PA design.
1
Introduction
The power amplifier (PA) is the main energy consumption
component in wireless portable device. When the signals
have a high peak to average power ratio, the PA should
work at a back-off point from the peak power to ensure
linear operation. However, power-added efficiency (PAE) at
the low power level is poor because of the fixed supply
voltage and the load impedance optimised at the maximum
power level. Consequently, a large portion of the battery
power is wasted at the low power amplification. Therefore,
improving the efficiency of a PA at the power back-off
condition can save energy and increase battery lifetime. The
Doherty architecture is a good choice to enhance the
back-off efficiency because only half of the power cell
works in the low power region [1, 2].
Recently, the increasing number of RF components are
being integrated using the complementary metal-oxide
semiconductor (CMOS) process to meet the requirements of
cost reduction and small size in wireless consumer markets.
However, the CMOS PA is difficult to design because of
the low breakdown voltage, conductive Si substrate and
lack of ground via.
Here, a 1.75 GHz Doherty PA is designed and
implemented in a 0.18-µm CMOS process. This Doherty
PA uses a voltage combining transformer to combine the
output power and realise the load modulation which is
different from the conventional current combining Doherty
amplifier. The prototype has a power-added efficiency
(PAE) of 31.6% at a maximum output power of 28.6 dBm
from a 3.4 V supply voltage. The PAE at 6 dB back-off is
still high, at about 25%. It shows clearly the efficiency
enhancement at the power back-off point due to the
Doherty operation. This is the first reported use of voltage
combining techniques in CMOS Doherty PA design.
IET Microw. Antennas Propag., 2014, Vol. 8, Iss. 3, pp. 131–136
doi: 10.1049/iet-map.2013.0241
2 Voltage combining method of Doherty
amplifier
The Doherty technique is based on load modulation at the
output. The output load is modulated by the current ratio
between the carrier and peaking amplifiers [3]. The carrier
amplifier operates in class AB or class B, and the peaking
amplifier operates in class C. For a low power level, only
the carrier amplifier is turned on. The peaking amplifier
turns on at the power level of 6 dB back-off from the peak
power. A quarter wavelength transmission-line (λ/4 T-line)
combines the power from both amplifiers and realises the
load modulation. The conventional current combining
structure places the λ/4 T-line behind the carrier amplifier
as shown in Fig. 1. It acts as an impedance inverter, which
causes the resistive impedance seen by the carrier amplifier
to decrease as the peaking amplifier current increases.
In CMOS PA design, the voltage combining method is
utilised and the current combining method can cause
problems. In order to obtain high output power, the
optimum resistance (Ropt) of CMOS amplifier is small, and
the impedance after the current combining is Ropt/2 leading
to a large loss when it is matched to 50 Ω, thus limiting the
bandwidth. Second, the standard RF CMOS process does
not have a ground via that can connect transistor’s source to
ground perfectly. Therefore, the differential structure is
widely used to supply a virtual ground. Last, the
transformer provides a low loss matching circuit on
conductive Si substrate [4]. The voltage combining
transformer is a good solution to solve those problems.
Owing to the voltage combining output matching of the
CMOS PA, it is advantageous to design a Doherty amplifier
based on the voltage combining method.
Fig. 2 depicts an idealised schematic of the CMOS Doherty
PA based on the transformer. To simplify the analysis, the
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Fig. 1 Block diagram of conventional current combining Doherty PA
ideal voltage combining transformer is used. Theoretically, at
the maximum output power, the peaking and the carrier
amplifiers should have the same fundamental output
voltages (Vp = Vc = V ) and currents (Ip = Ic = I ) so that the
two amplifiers have the same load impedance (Zp = Zc =
Ropt) and generate the same power. In this structure, the AC
voltages on the secondary loops are added, while the
primary loops are driven by the voltages of the peaking and
the carrier amplifiers. However, the current of the secondary
loops are identical to that of the primary loops (Iout = I )
because the transformer is assumed as ideal. The Zout can
then be calculated as
Vout
I
out +VP − −VP + (+VC ) − (−VC )
=
I
VP VP VC VC
+ +
+
=
I
I
I
I
= Zc+ + Zc− + Zp+ + Zp−
4V
= 4Ropt
=
I
Zout =
(1). This series combining is the main difference from the
current combining in parallel. Compared to current
combining, voltage combining has a smaller impedance
transformation ratio when matched to 50 Ω and a wider
bandwidth.
At a low power level (0 ≤ Vin ≤ 0.5Vin,max), the peaking
amplifier is turned off and sees infinite impedance
Zpeaking+ = Zpeaking− = 1
The λ/4 T-line which is placed after the peaking amplifier has
a characteristic impedance of Ropt. It functions as an
impedance inverter. Consequently, the impedances seen at
the transformer’s input are
Zp+ = Zp− = 0
(3)
Therefore, the carrier amplifier sees the load impedance of
Zc+ = Zc− =
(1)
Therefore, the output impedance of the voltage combining
transformer Zout is fixed to four times of Ropt of the power
cell, which is four-way series combined, as expressed in
(4)
Operation of proposed CMOS Doherty PA
3.1
Fig. 2 Block diagram of an ideal voltage combining Doherty PA
4Ropt − 2 × 0
= 2 × Ropt
2
Hence, the carrier amplifier sees twice the larger impedance
of the optimum resistance (2Ropt). This high impedance
leads to premature saturation of the carrier amplifier while
the current Ic is only half of its maximum value.
At a high power level (0.5Vin,max ≤ Vin < Vin,max), the
carrier amplifier reaches its maximum output swing and the
peaking amplifier turns on the generating current Ip.
Increasing of Ip decreases the effective impedance of
(Zpeaking+) and (Zpeaking−) from infinity. Owing to the λ/4
T-line, (Zp+) and (Zp−) increase from 0 to Ropt and (Zc+) and
(Zc−) decrease from 2Ropt to Ropt, allowing the carrier
amplifier to supply more current and keep the output
voltage swing at its peak value.
At the peak power (Vin = Vin,max), (Zp+) and (Zp−) change
from 0 to Ropt and this results in (Zc+) and (Zc−) decreasing
from 2Ropt to Ropt. Both amplifiers can work with the peak
efficiency and achieve the second peak in the overall
efficiency. The impedance variation curves are shown in
Fig. 3, which is the ideal load modulation for Doherty
operation.
3
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(2)
Circuit design methodology
Based on the basic concept of the voltage combining
technique, a CMOS Doherty amplifier has been designed.
The circuit topology is shown in Fig. 4. The attached
IET Microw. Antennas Propag., 2014, Vol. 8, Iss. 3, pp. 131–136
doi: 10.1049/iet-map.2013.0241
www.ietdl.org
T-lines are employed. The second harmonic short circuits
are attached at the drain of the each power cell to improve
the linearity.
3.2
Fig. 3 Load impedance variation of an ideal voltage combining
Doherty PA
capacitors at the transformer tune the output impedance for
50 Ω matching. To reduce the chip size and facilitate high
integration, lumped element pi networks instead of λ/4
Voltage combining transformer design
The voltage combining transformer plays a key role in this
design. It not only combines the output power from both
amplifiers but also realises the output impedance matching.
More importantly, it works with the λ/4 T-line as an
inverter and reduces the load impedance of the carrier
amplifier when the input power increases. The transformer
used in this work is shown in Fig. 5. It has an 8-shape
composed of two loops and the loops are twisted to have an
opposite current flow, immune to the common mode
oscillation [5–7]. The secondary loop is placed between the
double primary loops to enhance the coupling factor k and
reduce the primary inductance. Both the loops utilise the
top layer (4.0 µm thickness copper metal) and dual
secondary loops are connected with lower layers. The
Fig. 4 Schematic of the proposed CMOS Doherty PA
Fig. 5 Eight-shape transformer
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doi: 10.1049/iet-map.2013.0241
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Table 1 Transformer characteristics at 1.75 GHz
Primary
inductance Lp,
nH
0.66
Secondary
inductance Ls, nH
Primary
resistance Rp,
Ω
Secondary
inductance Rs, Ω
Primary
quality factor
Qp
Secondary
quality factor Qp
Coupling
factor k
Turn
ratio
3.4
0.6
5.6
12.04
6.67
0.73
1:2.27
transformer characteristics at 1.75 GHz are listed in Table 1.
The test pattern of the transformer is shown in Fig. 6. To
measure the three-port transformer using a two-port
network analyser, the same two transformers are laid out in
a back-to-back configuration. The differential ports of one
transformer are directly connected to the other transformer’s
Fig. 6 Test pattern of transformer
Fig. 7 Simulation results of input impedance
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differential ports. The insertion loss of a single transformer
is half the total loss in dB. The insertion loss of the single
transformer is 1.23 dB (efficiency of 76%) at 1.75 GHz.
3.3
Input driven unevenly
Besides the output transformer design, the input power
dividing ratio is very important for proper Doherty
operation [8]. Owing to the different bias conditions of the
two amplifiers, the gain of the peaking amplifier is lower
than that of the carrier amplifier. For this reason, an uneven
drive is adopted to improve the output power and it can be
realised through matching the fundamental input impedance
of the carrier and the peaking amplifiers to different points
as shown in Fig. 7. At a low power operation, the
fundamental input impedance of the peaking amplifier is
highly mismatched and the carrier amplifier is slightly
mismatched. Hence, more input power is driven to the
carrier amplifier, improving the gain and preventing the
peaking amplifier turning on early. At a high power level,
the fundamental input impedance of the carrier amplifier
remains almost constant with the input power variation,
while that of the peaking amplifier changes significantly
because of the class-C bias. Therefore, the fundamental
input impedance of the carrier amplifier is still slightly
mismatched and that of the peaking amplifier is matched to
the port impedance at the maximum output power
condition. The differential structure offers a cancellation
effect of even-order harmonics, and second harmonic short
circuits are attached at the output. Moreover, the second
harmonic input impedance affects efficiency very slightly.
The third harmonic input impedance of the carrier and the
peaking amplifiers are located around the open area as
shown in Fig. 7. Consequently, the peaking amplifier
obtains more input power, compensating for the smaller
currents and gain due to the low bias. Simulation results are
shown in Fig. 8. The carrier input power is reduced by 1.5
dB, and 1.5 dB more power is delivered to the peaking
Fig. 8 Simulation results of uneven drive
IET Microw. Antennas Propag., 2014, Vol. 8, Iss. 3, pp. 131–136
doi: 10.1049/iet-map.2013.0241
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Fig. 10 Fabricated chip photograph of CMOS Doherty power
amplifier
Fig. 9 Simulation results for input power-dependent variations
a Device voltages
b Device currents
Fig. 11 Measured PAE, power gain and DC consumptions against
output power at 1.75 GHz
amplifier at the maximum output power, realising the uneven
driven for optimum operation of the Doherty PA. Thus, at
the maximum output power point, both amplifiers can have
the same fundamental voltages and currents, generating the
same output power.
Simulation has been carried out to check the load
modulation behaviour. Fig. 9 shows the current and voltage
amplitudes of the carrier and peaking devices over the
whole input power range. The peaking amplifier does not
consume any current at a low power region until 18 dBm
input power. The voltage and current of it are close to
0. For the upper 6 dB region, the current and voltage of the
peaking amplifier increase very quickly while the voltage of
carrier amplifier remains almost constant at 3.0 V. At the
maximum power point, the carrier and peaking amplifiers
achieve the same amplitudes of current and voltage.
4 Implementation and measurement results
of the CMOS Doherty PA
The proposed CMOS Doherty PA has been fabricated using a
0.18-µm CMOS process. A chip micrograph is shown in
Fig. 10. The prototype was assembled on a four-layer FR-4
test board. The PA output pads and 3.4-V power supply pads
are double-wire bonded to minimise the bonding wire
inductance. The loss of the bonding wire, the input balun and
the output transformer are included in the measurement results.
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doi: 10.1049/iet-map.2013.0241
Fig. 12 Two-tone measurement results at 1.75 GHz with a tone
spacing 10 MHz
The test results for a 1.75 GHz one-tone signal are given in
Fig. 11. The PA achieves 28.6 dBm maximum output power
with a peak PAE of 31.6%. The PAE is kept above 25% over
a 6 dB range of output power. This prototype shows a
significant improvement of PAE at the power back-off
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6
Table 2 Comparison of CMOS performance
Design Technology Pout, max,
dBm
PAE (%) at 6
dB back-off/
peak
Technique
transformer
combining
current
combining
current
combining
voltage
combining
[9]
45 nm
31.5
20/27
[10]
0.13-µm
31.5
20/33
[11]
90 nm
26.5
12.2/39
this
work
0.18-µm
28.6
25.1/31.6
point. The DC current consumption of the carrier and the
peaking amplifiers is also shown in Fig. 11. At the
maximum output power point, both amplifiers consume
almost the same current and generate the same output
power. This result demonstrates the successful realisation of
the uneven drive. Fig. 12 shows the measured IMDs from
the two-tone test. Table 2 compares this work with other
reported CMOS PA designs. This work achieves the highest
6 dB back-off efficiency performance using the voltage
combining method.
5
Conclusion
A CMOS Doherty PA using a voltage combining method has
been proposed. It is believed that this is the first reported use
of the voltage combining technique in CMOS Doherty PA
design. The λ/4 T-line and voltage combining transformer
work together as an impedance inverter and reduce the load
impedance of the carrier amplifier when the peaking amplifier
turns on, realising the load modulation characteristic of
Doherty operation. With the Doherty technique, the
amplifier’s PAE is kept above 25% over a 6 dB range of
output power. The proposed method of voltage combining is
an attractive solution in the design of CMOS Doherty PA.
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Acknowledgment
This research was supported by the World Class University
program funded by the Ministry of Education, Science and
Technology through the National Research Foundation of
Korea (R31-10100), and by the Brain Korea 21 Project in
2012.
7
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IET Microw. Antennas Propag., 2014, Vol. 8, Iss. 3, pp. 131–136
doi: 10.1049/iet-map.2013.0241