RADIO FREQUENCY (RF)
COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS)
ULTRA WIDEBAND (UWB)
TRANSMITTER AND RECEIVER FRONT-END DESIGN
A Dissertation
by
MENG MIAO
Submitted to the Office of Graduate Studies of
Texas A&M University
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
May 2008
Major Subject: Electrical Engineering
RADIO FREQUENCY (RF)
COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS)
ULTRA WIDEBAND (UWB)
TRANSMITTER AND RECEIVER FRONT-END DESIGN
A Dissertation
by
MENG MIAO
Submitted to the Office of Graduate Studies of
Texas A&M University
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
Approved by:
Chair of Committee,
Committee Members,
Head of Department,
Cam Nguyen
Steven Wright
Laszlo Kish
Reza Langari
Costas Georghiades
May 2008
Major Subject: Electrical Engineering
iii
ABSTRACT
Radio Frequency (RF) Complementary Metal-Oxide Semiconductor (CMOS)
Ultra Wideband (UWB) Transmitter and Receiver Front-end Design. (May 2008)
Meng Miao, B.S., Nanjing University, People’s Republic of China;
M.S., Nanjing Research Center of Electronics Engineering, People’s Republic of China;
M. Eng., National University of Singapore
Chair of Advisory Committee: Dr. Cam Nguyen
The low-cost low-power complementary metal-oxide semiconductor (CMOS)
ultra wideband (UWB) transmitter and receiver front-ends based on impulse technology
were developed. The CMOS UWB pulse generator with frequency-band tuning
capability was developed, which can generate both impulse and monocycle pulse signals
with variable pulse durations. The pulse generator integrates a tuning delay circuit, a
square-wave generator, an impulse-forming circuit, and a pulse-shaping circuit in a
single chip. When integrated with the binary phase shift keying (BPSK) modulator, the
transmitter front-end can generate a positive impulse with 0.8 V, negative impulse with
0.7 V, as well as the positive/negative monocycle pulse with 0.6 – 0.8 V, all with tunable
pulse durations.
The UWB receiver front-end including the template pulse generator, low noise
amplifier (LNA), and multiplier was developed. The cascoded common-source
inductively degenerated LNA, with extended ultra-wideband ladder matching network,
as well as shunt-peaking topology, was selected to form the impulse-type UWB LNA.
The structure-optimized and patterned ground shield (PGS) inductors were also studied
and used in LNA design to improve the LNA performance. The maximum gain of 12.4
dB was achieved over the band. For the 3-dB bandwidth, 2.6 – 9.8 GHz was achieved.
The average noise figure of 5.8 dB was achieved over the entire UWB band of 3.1-10.6
GHz. The UWB multiplier based on the transconductor multiplier structure was
iv
investigated, with the shunt-peaking topology applied to achieve the pole-zero
cancellation and extend the multiplier bandwidth from 2 GHz to 10 GHz.
A low-cost, compact, easy-to-manufacture coplanar UWB antenna was
developed that is omni-directional, radiation-efficient and has a stable UWB response. It
covers the entire UWB frequency range of 3.1 – 10.6 GHz, with the return loss better
than 18-dB. This novel uniplanar antenna was integrated with the developed CMOS
tunable pulse generator to form the UWB transmitter front-end module. This UWB
module can transmit the monocycle pulses and the signals having shape similar to the
first derivative of the monocycle pulses, all with the tunable pulse durations. The
proposed UWB front-ends have the potential application in short-range communication,
GPR, and short-range detections.
v
To my family
vi
ACKNOWLEDGEMENTS
I would like to express my deepest gratitude to my advisor, Dr. Cam Nguyen, for
his advice, encouragement and support throughout this research. I would also like to
thank my committee members, Dr. Steven Wright, Dr. Laszlo Kish, and Dr. Reza
Langari for their valuable time and advice.
I am also grateful to my wife, Qingmei Lu, daughters, Hannah and Cathy, and to
my parents and relatives for their encouragement and support over these years. This
research was supported in part by the National Science Foundation, in part by the Texas
Advanced Research Technology Program, and in part by Dell Computer.
vii
TABLE OF CONTENTS
CHAPTER
Page
I
INTRODUCTION................................................................................
1
II
FUNDAMENTALS OF UWB SYSTEMS..........................................
5
2.1
III
UWB Basics ..........................................................................
2.1.1 UWB Definitions..........................................................
2.1.2 UWB Advantages.........................................................
2.1.3 UWB Applications .......................................................
2.2 UWB Pulse Signals ...............................................................
2.2.1 Gaussian Impulse .........................................................
2.2.2 Gaussian Monocycle Pulse...........................................
2.2.3 Gaussian Doublet Pulse................................................
2.3 Basic Modulation Topologies ...............................................
2.3.1 PPM ..............................................................................
2.3.2 PAM .............................................................................
2.3.3 OOK .............................................................................
2.3.4 BPSK............................................................................
2.4 Impulse-type UWB Structures ..............................................
2.4.1 UWB Transmitter .........................................................
2.4.2 UWB Receiver .............................................................
2.5 UWB Antennas .....................................................................
2.5.1 Introduction ..................................................................
2.5.2 Antenna Types..............................................................
2.5.3 Simulation Tools ..........................................................
2.5.4 Measurement Techniques.............................................
5
5
7
8
10
11
11
13
14
15
16
16
16
17
18
20
23
23
23
25
26
UWB TRANSMITTER DESIGN ........................................................
28
3.1 Basic Components Overview ................................................
3.1.1 CMOS Inverter Basics .................................................
3.1.2 Inverter Switching Characteristics ...............................
3.1.3 Two-input NOR/NAND Gate Blocks ..........................
3.1.4 Tunable Delay Cell.......................................................
3.2 Tunable Pulse Generator Design...........................................
3.2.1 Tuning Delay Component ............................................
3.2.2 Square Wave Generator ...............................................
3.2.3 Impulse-forming Block ................................................
3.2.4 Pulse-shaping Circuit ...................................................
30
30
33
36
37
39
39
41
44
45
viii
CHAPTER
IV
Page
3.2.5 Tunable Pulse Illustration.............................................
3.2.6 Simulation and Measurement Results ..........................
3.3 BPSK Modulator Design.......................................................
3.4 Tunable Transmitter Design..................................................
46
47
59
63
UWB RECEIVER DESIGN ................................................................
70
4.1
UWB LNA ............................................................................
4.1.1 LNA Design .................................................................
4.1.2 Inductor Optimization ..................................................
4.1.3 LNA Fabrication and Test............................................
4.2 UWB Correlator Design........................................................
4.2.1 DC Analysis .................................................................
4.2.2 AC Analysis .................................................................
4.2.3 Fabrication and Results ................................................
4.3 Receiver Front-end................................................................
V
71
71
88
93
99
101
104
106
110
UWB UNIPLANAR ANTENNA ........................................................ 112
5.1 Uniplanar Antenna Design .................................................... 113
5.2 Antenna Fabrication and Test ............................................... 122
5.3 UWB Transmitter Module .................................................... 126
VI
CONCLUSIONS .................................................................................. 130
REFERENCES.......................................................................................................... 133
VITA ......................................................................................................................... 140
ix
LIST OF FIGURES
FIGURE
Page
2.1
Indoor UWB Systems’ Spectrum Mask .....................................................
5
2.2
Power Levels of UWB Signal and a Typical Narrowband (NB) Signal ....
6
2.3
Gaussian Impulse and Frequency Spectrum ..............................................
10
2.4
Gaussian Monocycle Pulse and Frequency Spectrum................................
12
2.5
Gaussian Doublet Pulse and Frequency Spectrum.....................................
13
2.6
Pulse Position Modulation .........................................................................
15
2.7
Pulse Amplitude Modulation .....................................................................
15
2.8 On-off Keying ............................................................................................
16
2.9
Bi-phase Shift Keying ................................................................................
17
2.10 Transmitter Top Level Schematic ..............................................................
18
2.11 Receiver Top Level Schematic ..................................................................
21
3.1
CMOS Inverter Circuit and Its Symbol......................................................
30
3.2
CMOS Inverter Delay-time Definitions .....................................................
34
3.3
CMOS NOR2 Gate Block and Its Symbol.................................................
36
3.4
CMOS NAND2 Gate Block and Its Symbol..............................................
37
3.5
Shunt-capacitor Delay Element..................................................................
38
3.6
Block Diagram of CMOS UWB Tunable
Monocycle Pulse Generator Chip ..............................................................
39
Circuit Schematics of Tunable Delay Cell (a) and Reference Cell (b) ......
40
3.8 Cascade of Inverters Used to Drive a Large Load Capacitance.................
42
3.7
x
FIGURE
3.9
Page
Illustration of Signal Shapes at Each Node of
Tunable Pulse Generator Shown in Fig. 3.6...............................................
46
3.10 Photograph of the 0.18-µm CMOS Tunable Monocycle Pulse
Generator Chip Including Pads for On-wafer Probe Measurement ...........
48
3.11 Output Signal of Square Wave Generator..................................................
49
3.12 Rising and Falling Edges of Tunable Square Wave Signal .......................
50
3.13 Transfer Function of Designed Pulse Shaping Circuit...............................
51
3.14 Pulse-shaping Circuit Performance for Impulse Input ...............................
52
3.15 Measured and Simulated Impulse Signals with
Tunable Pulse Duration..............................................................................
53
3.16 PSD of Tunable Impulse Signal (a) 100 ps. (b) 300 ps..............................
55
3.17 Measured Impulse Width vs. Tuning Delay Voltage .................................
56
3.18 Measured Negative Impulse Signals with
Tunable Pulse Duration (NAND Gate Block)............................................
57
3.19 Tunable Monocycle Pulse Generator .........................................................
58
3.20 Spectrum of Tunable Monocycle Pulse Signal ..........................................
59
3.21 BPSK Diagram Block ................................................................................
60
3.22 BPSK Modulation Circuit ..........................................................................
61
3.23 Simulated Insertion Loss and Isolation of BPSK Modulator .....................
62
3.24 Simulated Time-domain Performance of BPSK Modulator ......................
63
3.25 Diagram Block of Tunable Impulse Generator with BPSK Modulator .....
64
3.26 Photograph of Impulse Generator with BPSK Modulator .........................
65
3.27 Measured Results of Impulse Transmitter .................................................
65
xi
FIGURE
Page
3.28 Monocycle Pulse Generator with BPSK Modulator ..................................
66
3.29 Photograph of Monocycle Pulse Generator with BPSK Modulator ..........
68
3.30 Measured Results of Monocycle Pulse Transmitter...................................
68
4.1
Various Wideband LNA Topologies..........................................................
72
4.2
Ladder Matched UWB LNA ......................................................................
74
4.3
Third-order Chebyshev Bandpass Filter ....................................................
76
4.4
Performance of Three-section Chebyshev Bandpass Filter .......................
77
4.5
Noise Model for Transistor M 1 .................................................................
80
4.6
Source-follower Buffer for UWB LNA .....................................................
87
4.7
Inductor π-model ........................................................................................
89
4.8
Layout of Patterned Ground Shield Inductor .............................................
91
4.9
Performance of the Patterned Ground Shield Inductor L1 .........................
92
4.10 Photograph of LNA Chip ...........................................................................
93
4.11 Return Loss of Input Port for LNA ............................................................
94
4.12 Return Loss of Output Port for LNA .........................................................
94
4.13 Reverse Isolation of LNA ..........................................................................
95
4.14 Power Gain of LNA with Buffer................................................................
96
4.15 Phase Performance of S 21 for LNA ...........................................................
97
4.16 Measured LNA Performance in Time-domain...........................................
97
4.17 Noise Performance for LNA ......................................................................
98
4.18 Correlator in UWB Receiver......................................................................
99
xii
FIGURE
Page
4.19 Schematic of the Proposed Multiplier ........................................................ 102
4.20 Simplified Small-signal Equivalent Circuit ............................................... 105
4.21 Frequency Response for Dominant Pole .................................................... 107
4.22 Frequency Response for Shunt-peaking Inductor Effect ........................... 108
4.23 Photograph of the Fabricated Multiplier .................................................... 108
4.24 Conversion Gain and RF Return Loss with the IF Frequency
10 MHz, LO Power is -1 dBm, and RF Power is -20 dBm........................ 109
4.25 Block Diagram of the Receiver Front-end ................................................. 110
4.26 Transient Simulation of the Receiver Front-end ........................................ 111
4.27 Layout of the Proposed Receiver Front-end .............................................. 111
5.1
Basic Structure of the Uniplanar Antenna.................................................. 114
5.2
Simulated Return Loss of the Designed Uniplanar Antenna ..................... 119
5.3
Simulate Input Reflection of the Designed Antenna in Time-domain....... 120
5.4
Simulated Amplitude of Transfer Function ............................................... 120
5.5
Simulated Phase of Transfer Function ....................................................... 121
5.6
Simulated Antenna Patterns ....................................................................... 122
5.7
Photograph of the Developed UWB Antenna along with
50-Ω CPW Feed Line and SMA Connector (on the Left) ......................... 123
5.8
Measured and Simulated Return Loss of Uniplanar UWB Antenna.......... 124
5.9
Measured and Calculated TDR Responses of
Uniplanar UWB Antenna ........................................................................... 125
5.10 Photograph of the Fabricated UWB Transmitter Module .......................... 126
xiii
FIGURE
Page
5.11 Test Setup for Pulse Transmission Measurement of
UWB Transmitter Module ......................................................................... 127
5.12 Measured Received Signals of the Impulses Transmitted by
UWB Transmitter Module for Different Control Voltages........................ 128
5.13 Measured Received Signals of the Monocycle Pulses Transmitted by
UWB Transmitter Module for Different Control Voltages........................ 128
xiv
LIST OF TABLES
TABLE
Page
3.1
The Size of Inverters in Square Wave Generator.......................................
49
3.2
The Size of NOR Gate Block.....................................................................
53
3.3
The Size of NAND Gate Block..................................................................
57
3.4
The Size of Transistors in BPSK Modulator..............................................
62
4.1
Component Values of Third-order Chebyshev BPF ..................................
77
4.2
Final Component Values of LNA ..............................................................
87
5.1
Parameters of 50-Ω Quasi-CPW Feed Line ............................................... 116
5.2
Dimensions of Uniplanar Antenna ............................................................. 118
1
CHAPTER I
INTRODUCTION
In the past decades, ultra-wideband (UWB) was mainly used for military
communications, radar, and sensing applications. With the approval of Federal
Communications Commission (FCC) in February 2002, UWB technology pushes the
limits of high data-rate, and has been proposed for high-rate, short-range
communications [1], such as home networks, in-building communications, and cordless
phones. Contrary to the traditional narrowband, sinusoidal wave radio signals, an UWB
signal is typically composed of a pulse train of sub-nanosecond pulses modulated either
in polarity or in position. The narrowness of the pulses in time corresponds to a wide
bandwidth in the frequency domain. Since the total power is spread over such a wide
range of frequencies, its power spectral density is extremely low. This effectively
produces extremely small or no interference to other existing radio signals while
maintains excellent immunity to interference from these signals [2]-[3]. UWB
technology can also be used to achieve other wireless applications, such as through-wall
and medical imaging systems, radars, ground penetrating radars (GPRs), and military
applications with relatively high emission power levels. The signals of UWB systems
can provide all the above applications with penetration and target tracking feasibility that
narrow-band signals may not.
Currently, two different topologies are widely considered for UWB systems. One
is the orthogonal frequency division multiplexing (OFDM) based multi-band UWB, in
which the frequency band is divided into tens of hundred-MHz bands; the other is the
impulse-based single/dual band system. In multi-band OFDM UWB scheme, data is
transmitted using OFDM on different bands in a time-interleaved fashion. Each band has
____________
This dissertation follows the style of IEEE Transactions on Microwave Theory and
Techniques.
2
a minimum bandwidth of 500 MHz and frequency hopping is employed to cover a wide
bandwidth. Since the device can dynamically select which bands to use for transmission,
multi-band OFDM UWB has the advantages of inherent robustness to multi-path,
excellent robustness to narrowband interference, ability to comply with worldwide
regulations. Compare with multi-band UWB approach, where the up-converter is needed
to generate the modulated signal that can transmit effectively, implementing an impulsebased UWB system requires a simpler circuit structure with less power dissipation, no
up-conversion circuitry is needed, since UWB signal itself can be used for transmission.
Furthermore, an impulse-based UWB system can potentially use a bandwidth of over 7
GHz, reducing the chance of fading in case where the noise exists in a narrow frequency
band within the UWB band, resulting in better immunity to destructive channel
environments. This is an advantage as compared to the OFDM case, where the noise in a
particular frequency channel may disrupt that channel. Additionally, since impulse-based
UWB uses very short duration impulse signals, the accuracy of position detection is
higher. Based on above facts, the research of this dissertation will focus on the impulsetype UWB technology.
The selection of the impulse signal types for the UWB system is one of the
fundamental considerations in designing UWB circuits and systems, because the impulse
types determine the spectrum characteristics of UWB signals. Many kinds of signals can
be used in UWB systems, such as step pulse, Gaussian impulse, monocycle, or multicycle signal with short pulse duration; where the monocycle signal is most often used in
impulse-type UWB systems because of its better spectral shape and wider bandwidth
characteristic [2], [4]-[8]. Several monocycle pulse shapes were introduced in [9], and all
of them have wideband spectrums. Among them the Gaussian monocycle pulse has
relatively wide 3-dB bandwidth and no DC components, better bit-error-rate (BER)
performance, hence fits the FCC emission regulation better than any other pulse,
therefore the design of a Gaussian pulse generator is an important work in the whole
impulse-type UWB system.
3
Up to now, many existing UWB pulse generators are based on approaches
developed for radar applications and involve hybrid circuit techniques [10]-[12]. On the
other hand, UWB system prefers radio frequency integrated circuit (RFIC) designs in
order to achieve low cost and low power consumption, easy integration with other
components, such as digital circuits and planar antennas. Though some expensive IC
technologies such as Silicon-Germanium (SiGe) or Gallium-Arsenide (GaAs) have been
used to realize transceiver, Complementary-Metal-Oxide-Semiconductor (CMOS)
technology is more desirable for a single-chip, low-cost solutions. However, some
inherent characteristics of CMOS technology, such as low breakdown voltage, poor
passive components, lack of accurate RF models etc, limit the CMOS RFIC applications
on such high frequencies and such a wide bandwidth, and make it a challenging work.
Fortunately, with the rapid development of current technology scaling and advances of
more accurate RF models, CMOS is quickly becoming the preferred choice for RFIC’s.
In order to use standard CMOS technology to generate sub-nanosecond pulses, new type
of integrated-circuit pulse generator, different from the traditional hybrid circuits, should
be employed based on CMOS process to produce Gaussian pulse with sub-nanosecond
pulse width. Similar research work is also applied to other important RF blocks such as
low noise amplifier (LNA) and mixer (correlator) in UWB systems.
Since UWB signals cover a relatively wide frequency band, the power density
can be extremely low, which avoids causing interference to users at the same frequency.
The fractional bandwidth of UWB signal normally exceeds 25%, which brings great
challenge on the UWB antenna design. Transmitting and receiving of UWB signal not
only requires the antenna to be able to radiate the energy over a wide frequency band but
also requires a linear phase response over the band to avoid signal distortion [13]. This
necessitates an antenna with a fixed phase center for different frequencies in the band.
However, many of existing wideband antennas such as tapered slot antennas and log
periodical antennas are not suitable for UWB communication because they have floated
phase centers for different frequencies. Currently, a few high-quality non-dispersive
UWB antennas are commercially available [14]. However, the large size of these
4
antennas makes them less suitable for most commercial applications and not feasible for
portable or handheld uses. Therefore, there is great need for a low-cost, compact, easyto-manufacture coplanar UWB antenna that is omni-directional, radiation-efficient and
has a stable UWB response. This type of antenna can be easily integrated with UWB
CMOS RFIC chips.
In this dissertation, novel low-cost low-power CMOS RFIC front-ends of
transmitter and receiver based on impulse-type UWB technology are presented, and they
are further integrated with the developed compact UWB coplanar antennas. With the
help of pulse tuning capability, the transmitter can generate both impulse and monocycle
pulse signals with variable pulse durations. This system has the potential application in
short-range communication, GPR, and short-range detections. Chapter II begins with an
overview of the UWB radio architecture; also, the fundamentals of UWB signal, UWB
modulation topology, and UWB antenna type are introduced. In chapter III, the design
and implementation of impulse-type UWB CMOS RFIC front-end module of the
transmitter with tunable pulse duration, integrated with Bi-Phase Shift-Keying (BPSK)
modulator, is presented. Chapter IV describes the design of the impulse-type UWB
CMOS RFIC front-end of the receiver. The design of a novel compact UWB uniplanar
antenna is presented in chapter V. Chapter VI includes the suggestion to improve the
system for future research.
5
CHAPTER II
FUNDAMENTALS OF UWB SYSTEMS
In this chapter, a review of the basic concepts of UWB systems is presented, with
particular emphasis on impulse radio (IR) techniques. The types of UWB pulse signal,
commonly used modulation topologies, and typical UWB antennas are also described.
2.1
UWB Basics
2.1.1
UWB Definitions
Fig. 2.1. Indoor UWB systems’ spectrum mask.
The FCC has defined UWB signals as that, over 3.1GHz to 10.6 GHz band, 10dB bandwidth of the signal occupies an absolute bandwidth greater than 500 MHz or a
fractional bandwidth greater than 0.20. However, one of the important conditions is that
the power levels of the UWB signal in this spectrum must be low enough to avoid
6
interference with the already existing technologies. The FCC specifies the power
emission levels suitable for co-existing with other technologies in the UWB allocated
band. The spectrum mask for in-door applications is shown in Fig. 2.1, where part 15
limit is the maximum allowed power spectral density of unintentional radiators, which is
-41.3 dBm/MHz.
Here the fractional bandwidth is the bandwidth expressed as a fraction of the
center frequency. Assume f H is the highest frequency limit and f L is the lowest
frequency limit of the 10-dB bandwidth, the fractional bandwidth of the UWB signal is
defined as
Fractional Bandwidth =
2( f H − f L )
≥ 20%
fH + fL
Power Spectral Density
NB
UWB
10-dB Bandwidth
fL
fc
fH
Frequency (Hz)
Fig. 2.2. Power levels of UWB signal and a typical narrowband (NB) signal.
(2.1)
7
2.1.2
UWB Advantages
For impulse-type UWB technology, the impulse radio communication systems
and impulse radars both utilize extremely short duration pulses, normally in the order of
subnanoseconds, instead of continuous waves to transmit information. The pulse directly
generates a very wide instantaneous bandwidth signal, and the duty cycle of the pulses
can be as low as 1%. Therefore the pulse spreads the energy over a wide frequency band,
which is shown in Fig. 2.2. Compare with narrow-band signal, the UWB signal is noise
like which makes interception and detection quite difficult. Due to the low-power
spectral density, UWB signals cause very little interference with existing narrow-band
radio systems.
Compare with conventional narrow-band systems, impulse-type UWB systems
have many advantages.
1.
Low complexity and low cost: Unlike traditional narrow-band radio
systems, the impulse-type UWB system produces a very narrow timedomain pulse, which is equivalent to a carrier-less baseband signal and is
able to propagate without further mixing with carrier signal. Hence the
additional up-conversion and amplification circuit is not needed. This
means the omission of local oscillator, the associated complex delay and
phase tracking loops. Therefore, the impulse-type UWB systems can be
implemented in low cost, low power, integrated circuit process, such as
CMOS technology.
2.
Low probability of interception: As shown in Fig. 2.2, the UWB signal
has much broader bandwidth, therefore much lower energy density than
that of the conventional narrow-band radio systems. For the UWB signal,
the extreme low energy density over the ultra-wide frequency range
appears as the noise to most other wireless devices, which makes
unintended detection quite difficult and results in low probability of
interception/detection. This characteristic makes UWB a good choice for
secure and military applications.
8
3.
Excellent immunity to interference from other existing radio signals:
Because the pulse signal is very narrow in time-domain, the transmission
duration of UWB pulse is shorter than a nanosecond in most cases, the
reflected pulse has an extremely short window of opportunity to collide
with the line of sight (LOS) pulse and cause signal degradation, hence
very high multi-path resolution is achieved. Since UWB spectrum covers
a vast range of frequencies from near DC to several gigahertz and offers
high processing gain for UWB signals, the frequency diversity caused by
high processing gain makes UWB signals relatively resistant to
intentional and unintentional jamming, because no jammer can jam every
frequency in UWB spectrum at once. Even if some of the frequencies are
jammed, there is still a large range of frequencies that remains untouched.
This makes the impulse-type UWB signal resistant to severe multi-path
propagation and jamming/interference. Therefore the impulse-type UWB
systems offer excellent immunity to interference from other existing radio
signals.
4.
Good time-domain resolution for location and tracking applications:
The very narrow time-domain pulses make the UWB radios able to offer
timing precision much better than global positioning system (GPS) and
other
radio
systems.
Along
with
good
substrate
penetration
characteristics, the impulse-type UWB systems offer opportunities for
short-range radar applications such as rescue and anti-crime operations,
as well as in surveying and in the mining industry such as GPR. The
inherent advantages of the impulse-type UWB systems offer the good
time-domain resolution for location and tracking applications.
2.1.3
UWB Applications
The wide spectrum of UWB system provides a wireless channel with high spatial
capacities, according to well-known Shannon’s channel capacity theorem
9
C = B ⋅ log 2 (1 + SNR )
(2.2)
where C is the channel capacity in bits/second, B is the bandwidth in Hertz, and SNR is
the Signal-to-Noise ratio.
(2.2) shows that the channel capacity is in linear relation with bandwidth and
logarithmic relation with SNR. Because of its inherent ultra wideband property, the
UWB system can achieve high data rates while operating below the noise floor. The
inherent high data rates and low power as well as attractive features like excellent multipath immunity and good immunity to external interference make the UWB technology a
good candidate in vast applications. Some of the potential application areas of the UWB
technology are listed below.
1.
Communications: The major commercial UWB application is for
communication, since it has very high data transfer rate for short distance.
UWB transceivers can send and receive high-speed data with very low
power at relatively low cost. UWB communication systems are often
advantageous
in
short-range
wireless
market.
Currently,
UWB
technologies are primarily targeting at indoor applications of short-range
at bit rates up to hundred of megabits per second, such as home
networking, high speed wireless local area networks (LAN), and personal
area networks (PAN) communications.
2.
Radars: Due to its precise time resolution, UWB technique may also be
used for both indoor and outdoor 3-D positioning. This makes the
impulse-type UWB GPR useful equipment for detecting internal structure
under the ground. Another important application is imaging like
microwave remote sensing, in which UWB signals pass through the doors
and walls and hence can detect the objects inside the building.
3.
Location finding: The good performance of UWB devices in multi-path
channels can provide accurate location capability for indoor and
environments where GPS receivers cannot work. One such application is
10
radio frequency identification (RFID). The major use of RFID is the
tracking device, which can be attached to the objects in the office, lab,
warehouse, etc, for locating or tracking inventory. Another application is
employee identification cards, which can be used to access the offices.
Because of the low power required and relatively low data rate, these
devices can be made to have a long lifetime on a single battery at a
relatively low cost.
2.2
UWB Pulse Signals
Since the impulse-type UWB system employs the very short pulses, pulse
generation and pulse shaping are among the most fundamental problems in the design of
UWB systems. Currently, three types of UWB pulses have often been used in the
impulse-type UWB systems, i.e., Gaussian impulse, Gaussian monocycle pulse, and
Gaussian doublet pulse.
1
1
Normalized Amplitude
Voltage Amplitude (V)
0.8
0.5
0
-0.5
-1
-0.2
0.6
0.4
0.2
-0.1
0
Time (ns)
0.1
0.2
0
0
2
4
6
8
10 12 14
Frequency (GHz)
Fig. 2.3. Gaussian impulse and frequency spectrum.
16
18
20
11
2.2.1
Gaussian Impulse
A Gaussian impulse has a shape of Gaussian distribution as shown in Fig. 2.3
and is expressed as
2 2
y (t ) = Ae − a t
(2.3a)
where A is the amplitude of the Gaussian impulse, a is the time constant. The power
density spectrum of the Gaussian impulse is
Y (ω ) =
A
a 2
e
−
ω2
4a2
(2.3b)
The corresponding frequency with peak value of power density spectrum is
fc = 0
(2.3c)
Therefore, the 3 dB bandwidth can be derived as
Δf = 0.8326
2.2.2
a 2
2π
(2.3d)
Gaussian Monocycle Pulse
Gaussian monocycle pulse is the first derivative of the Gaussian impulse signal,
which is shown in Fig. 2.4. Its general formula is shown as follows
2 2
y (t ) = −2a 2 Ate − a t
(2.4a)
12
where A is the amplitude of the Gaussian monocycle pulse, a is the time constant. The
power density spectrum of the Gaussian monocycle pulse is
Y (ω ) =
iAω
a 2
e
−
ω2
4a2
(2.4b)
The corresponding frequency with peak value of power density spectrum is
fc =
a 2
2π
(2.4c)
And the 3 dB bandwidth can be derived as
Δf = 1.155
0.8
0.5
Normalized Amplitude
Voltage Amplitude (V)
(2.4d)
1
1
0
-0.5
-1
-0.2
a 2
2π
0.6
0.4
0.2
-0.1
0
Time (ns)
0.1
0.2
0
0
2
4
6
8
10 12 14
Frequency (GHz)
Fig. 2.4. Gaussian monocycle pulse and frequency spectrum.
16
18
20
13
1
0.8
0.5
Normalized Amplitude
Voltage Amplitude (V)
1
0
-0.5
0.6
0.4
0.2
-1
-0.2
-0.1
0
Time (ns)
0.1
0
0
0.2
2
4
6
8
10 12 14
Frequency (GHz)
16
18
20
Fig. 2.5. Gaussian doublet pulse and frequency spectrum.
2.2.3
Gaussian Doublet Pulse
Gaussian doublet pulse is the second derivative of the Gaussian impulse signal,
which is shown in Fig. 2.5. Its general formula is shown as follows
2 2
(
y (t ) = −2a 2 Ae − a t 1 − 2a 2 t 2
)
(2.5a)
where A is the amplitude of the Gaussian doublet pulse, a is the time constant. The
power density spectrum of the Gaussian doublet pulse is
Y (ω ) =
− Aω 2
a 2
e
−
ω2
4a2
(2.5b)
The corresponding frequency with peak value of power density spectrum is
fc =
a
π
And the 3 dB bandwidth can be derived as
(2.5c)
14
Δf = 1.155
a 2
2π
(2.5d)
The waveforms of above three pulse signal show that Gaussian impulse has no
zero crossing point, Gaussian monocycle pulse has one zero crossing, and Gaussian
doublet pulse has two zero crossings.
The power density spectra of the three pulse signals are also compared.
According to (2.3c), for Gaussian impulse, majority frequency components of power
density spectrum are low-frequency ones and close to DC, which brings the greater
challenge to the transmission antenna of UWB system. For the Gaussian monocycle
pulse and Gaussian doublet pulse, the 3dB bandwidths are same, and there are no major
low-frequency components, which makes the signal transmission through the antenna
much easier.
2.3
Basic Modulation Topologies
There are several of modulation techniques that can be used to create modulated
UWB signals, and these topologies modulate information bits directly into very short
pulses [15]. Since there is no intermediate frequency (IF) processing in such systems,
they are often called base-band or impulse radio systems. For impulse-type systems, the
typical UWB modulations can be divided into mono-phase techniques and bi-phase
techniques. The three most popular mono-phase UWB approaches are pulse position
modulation (PPM), pulse amplitude modulation (PAM), and on-off keying (OOK). In
these techniques, data signal “1” is differentiated from “0” either by the size of the signal
or when it arrives in time – but all the pulses generated have the same shape. For the
more efficient bi-phase case, bi-phase shift keying (BPSK) is one of the most popular
topologies. This modulation transmits a single bit of data with each pulse; with positive
pulse representing “1”, and negative pulse representing “0”. Following will give brief
description for each of these modulation topologies.
15
1
0
0
1
Fig. 2.6. Pulse position modulation.
2.3.1
PPM
PPM is one of the common modulation technologies used in impulse-type UWB
systems. In this technique, both pulses (indicating digital data bit “1” or “0”) have the
same amplitude, and the system transmits the same pulse in one of two positions in the
time domain in order to represent a “0” or “1”. This method may require a more complex
receiver in order to determine the precise position of the received pulse. An example of
PPM is shown in Fig. 2.6, where the position of the pulses representing “1” leads that of
the pulses representing “0”.
1
0
1
Fig. 2.7. Pulse amplitude modulation.
0
16
2.3.2 PAM
PAM works by separating the “tall” and the “short” pulse waves. The amplitude
of the pulse is varied according to the different digital data information, where largeamplitude pulse represents “1” and small-amplitude pulse for “0”. Fig. 2.7 illustrates the
PAM technique.
1
0
1
0
Fig. 2.8. On-off keying.
2.3.3
OOK
For OOK modulation, the pulse amplitude of information bit “1” is set to the
same amplitude of that UWB pulse, which is equivalent to on; while the pulse amplitude
of information bit “0” is set to zero, which is equivalent to off. By setting the pulse on
and off, binary information bits, “1” and “0”, are being sent out. An example of OOK is
shown in Fig. 2.8, where “1” is when there is pulse and “0” is when there is no pulse.
2.3.4 BPSK
The most common bi-phase approach used in impulse-type UWB systems is
BPSK. Bi-phase differentiates “1” with a positive pulse and “0” with a negative pulse.
Comparing with PPM, where the series of ultra-wideband circuits are needed to generate
very accurate time steps, this approach is simple and only requires two kinds of pulses
17
be generated, and requires less processing at receiver side. BPSK offers several
advantages such as power efficiency and smooth spectrum with smaller-amplitude
spikes over above-mentioned mono-phase techniques like PPM, OOK, and PAM that
have larger amplitude spikes. These spikes are caused by the multi-pulse occurring
periodically, the most significant of which is a two times improvement in overall power
efficiency than OOK or PPM [15]. This makes the bi-phase UWB approach extremely
efficient for high data rate, portable applications. An example of BPSK is shown in Fig.
2.9.
1
0
1
0
Fig. 2.9. Bi-phase shift keying.
2.4
Impulse-type UWB Structures
Impulse-type UWB systems have several advantages over conventional narrowband systems and multi-band OFDM systems. First is its relatively simple structure,
because some complicated components such as up-converter related frequency
synthesizer and local oscillator used in traditional radio systems are not necessary. This
reduces the cost and makes the system compact. In addition, since there is no power
consumed on the up-converter circuit like the traditional narrow-band case, impulse-type
UWB consumes less power; therefore the life time of battery is much longer.
Furthermore, the large bandwidth of impulse signal makes the interception quite difficult
for unintended detectors.
18
In this section, the basic architectures of the proposed impulse-type UWB
system, which include the front-end modules of UWB transmitter and receiver, are
introduced and investigated. In particular, the concentration will focus on the design and
implementation of pulse generator, the critical part for both transmitter and receiver,
which can generate pulse with narrow duration. For the impulse-type UWB receiver, the
research will focus on the LNA and correlator design, which are the central parts of the
correlation-based UWB receiver.
2.4.1
UWB Transmitter
Compare with continuous-wave transmitters, one of the great advantages of the
impulse-type UWB transmitter is that there is no complex RF modules such as the power
amplifier (PA) and frequency synthesizer, which contain circuits such as the phaselocked-loop (PLL), voltage-controlled oscillator (VCO) and mixers [2]-[3]. All these
components make the traditional transmitters relatively difficult and expensive to design
and implement. In contrast, an impulse-type UWB transmitter costs not that much and
moderately easy to design and implement because of its simpler structures.
Transmitter Front End
Antenna
Pulse
Generator
Modulator
PRF Oscillator
Data In
Fig. 2.10. Transmitter top level schematic.
19
At the block level, the impulse-type transmitter is very simple, and its block
diagram is shown in Fig. 2.10. It consists of a pulse generator and a digital-controlled
modulator circuit that controls the timing or polarization of the transmitted pulse signal.
The local oscillator, either crystal oscillator or custom designed oscillator, determines
the pulse repetition frequency (PRF) of the system. The pulse generator can produce the
desired waveform, such as impulse, monocycle pulse, etc. The modulator circuit
modulates the pulse signal with incoming digital data information using abovementioned BPSK or PPM topology, depending on the timing or polarization modulation
requirement.
For the pulse generator design, there are many ways to generate the short pulse
signals with different technologies. Existing methods for generating subnanosecond
pulses are generally based on hybrid circuit design topologies, requiring different kinds
of discrete components, therefore resulting in large-size circuits and increased cost.
These existing pulse generators normally are not optimized for power consumption and
the feasibility of integrating them into a wireless device. Some of the pulse generators
were developed using spark gaps [16], which are not an option for consumer electronics
due to their size. Another method of generating subnanosecond impulse and monocycle
pulses involves the hybrid circuits based on Schottky diode, step recovery diode (SRD),
and planar transmission lines [10]-[12], which are also not suitable for RFIC
applications.
In addition to the above-mentioned pulse generation in time-domain, the pulse
signal can also be generated with frequency-domain topology, which should be very
accurate in theory [17]-[18]. The fundamental of this topology is to use the Fourier series
based method to implement the waveform generation in frequency domain. By
expanding the desired waveform into Fourier series, the corresponding sinusoidal
components are generated and transmitted to obtain the signal in frequency-domain by
summing the low power harmonics, and the resulted pulse signal should be very
accurate. However, the Fourier series expansion contains an infinite amount of terms; in
20
reality the transmitter only transmits a finite number of harmonic terms, depending on
the desired performance.
Although in theory this method can generate extremely accurate pulse signal with
any shape, it requires a very complex transmitter design because of the large amount of
harmonic components. In addition, the receiver will have to receive all of the generated
harmonics, resulting in the complicated receiver. Due to the complex nature of the
design, it is not suitable for most wireless UWB applications.
Unfortunately, all the design topologies mentioned above have one common
problem, relatively large circuit size, therefore high cost. This problem makes them not
the good choice for the compact UWB applications. With the development of
semiconductor technology, more and more UWB designs focus on CMOS RFIC
technology because of its low cost and low power consumption, easy integration with
other components, such as digital circuits and planar antennas. In this dissertation, the
novel tunable pulse generator based on commercial CMOS technology is developed to
produce both Gaussian impulse and monocycle pulse with tunable duration.
Furthermore, this pulse generator is integrated with BPSK modulator together to form
the transmitter front-end module. The design details of the impulse-type UWB
transmitter will be described in chapter III.
2.4.2
UWB Receiver
The impulse-type UWB receiver directly converts the received RF signal into a
baseband output signal. The corresponding block diagram is shown in Fig. 2.11. The
receiver examined here consists of a LNA, a correlation circuit, and a template pulse
generator. The local oscillator drives the pulse generator and determines the PRF of the
system. To maximize the processing gain and SNR, the template waveform should have
similar shape to that of the received signal. After passing LNA, the received pulse signal
is coherently correlated with the template pulse waveform through front-end crosscorrelator, and the input pulse train is converted to baseband signal in one stage.
21
Therefore no intermediate frequency stage is needed, thus greatly reducing the system
complexity.
Receiver Front End
Antenna
Data Out
LNA
Integrator
S/H
Correlator
Pulse
Generator
PRF Oscillator
Fig. 2.11. Receiver top level schematic.
The correlation circuit is the essential element of the impulse-type UWB
receiver. It consists of the multiplier, integrator, and sampling/holding (S/H) circuit. The
multiplier multiplies the received signal with the template waveform. The result of the
multiplier is integrated over several periods of the received pulse train to maximize the
received signal power and to minimize the noise component. Having a train of pulses to
integrate over, the correlated signal is raised from the noise. Therefore if more pulses are
used for each symbol, it will result better SNR, since more correlated energy is
integrated over the duration of each symbol.
Considering the unique feature of the impulse-type UWB, there is a stringent
requirement for the correlation speed. That means both multiplier and integrator must be
fast enough to process each pulse. This brings great challenge to the correlator design.
Like most spread spectrum systems, where energy generated in a particular
bandwidth is deliberately spread in the frequency domain, resulting in a signal with a
wider bandwidth, processing gain (PG) is also an important characteristic in an UWB
22
system. To combat noise and interference, a group of N pulses are used to transmit each
symbol, hence the energy of the symbol is spread over N pulses and processing gain can
be achieved. The processing gain in dB derived from this procedure can be defined as
[19]
PG1 = 10 log10 ( N )
(2.6)
Furthermore, the pulse signal only occupies a very small part of the entire period.
This means the duty cycle of the pulses can be extremely low, sometimes less than 1%.
Therefore the receiver is only required to work for a small fraction of the period between
pulses, and the impact of any continuous source of interference is reduced so that it is
only relevant when the receiver is attempting to detect a pulse. Hence the processing
gain due to the low duty cycle is given by [19]
⎛ Tf
PG2 = 10 log10 ⎜
⎜T
⎝ p
⎞
⎟
⎟
⎠
(2.7)
where T f is the period time and T p is pulse width.
Total processing gain PG is the sum of the two processing gains [19]
⎛ Tf
PG = PG1 + PG2 = 10 log10 ( N ) + 10 log10 ⎜
⎜T
⎝ p
⎞
⎟
⎟
⎠
(2.8)
For an impulse-type UWB, suppose the period time is 100 ns and the pulse width
is 200 ps, the PG2 from the duty cycle will be about 27 dB. Since the UWB uses
multiple pulses to recover each bit of information, if one digital bit is determined by
integrating over 100 pulses, then the PG1 will be another 20 dB. The total PG for the
23
UWB system is about 47 dB. Since PRF of the pulse is 10 MHz and each bit covers 100
pulses, the resulting data rate is 100 Kbps as obtained from (2.8).
2.5
UWB Antennas
2.5.1
Introduction
Unlike traditional narrow band systems, where antennas are often considered as
non-distortion device in system analysis, UWB antennas play a very important role in
signal analysis of UWB system. Because of the very large bandwidth of an UWB signal,
the antenna has a strong impact on parameters such as impedance matching, radiation
pattern as well as gain variations in UWB than in narrow band systems. For such very
wideband antennas, issues of linearity of antenna transfer function, radiation efficiency
and impedance match across the band present difficult problems. Therefore, an effective
UWB antenna is a critical part of an overall UWB system design.
2.5.2 Antenna Types
Considering the traditional ultra wideband antennas, a lot of them are multinarrowband antennas, which means the operational band of the antennas at specific time
is actually narrowband channel, such as AM broadcast antenna, the real effective
fractional bandwidth is only very small amount value, and only one channel can be
received at a time. On the contrary, in UWB systems, the ultra wideband requirement
brings great challenges to the antenna design. For impulse-type UWB systems, this
demanding is especially strict, as the antenna needs to cover the entire frequency range
of 3.1 – 10.6 GHz and radiates or receives all the frequency components coherent
simultaneously. Thus, antenna behavior and performance must be consistent with no
obvious variations and predictable across the entire band. Ideally, pattern and matching
should be constant and no variations across the entire band.
Furthermore, the transmitted and received UWB signals require antennas not
only radiating energy efficiently but also having linear phase response over the ultra
24
wide frequency band, so clean, temporally non-dispersed waveforms can be achieved
with very precise timing accuracy. Unfortunately, many conventional ultra wide
antennas cannot meet these requirements; one such example is the log-periodic antenna.
It is one kind of frequency-independent antennas, but it is dispersive. The smallest
antenna part radiates the highest frequency component while the largest antenna part
radiates the lowest frequency component. The result is a chirp-like, dispersive waveform
with different shape at different azimuthal angles around the antenna because of the
dispersion variations depending on the different direction and ranges. Obviously it is not
suitable to UWB applications.
Antennas currently used in UWB systems normally can be classified as
directional or omni-directional. Directional antennas include TEM horn and its variants,
Vivaldi, and reflector antennas [14], [20]-[23], while the omni-directional antennas
include dipoles, loops and their variants [24]-[26]. The directional antennas have the
common properties of high gain, narrow field of view, and relatively larger size; which
find applications in outdoor base station communications, GPRs. On the other hand, an
omni-directional antenna has relatively low gain, a wide field of view, and smaller size,
therefore is suitable for use in short range, low power indoor UWB radio systems.
Currently, a few high-quality non-dispersive UWB antennas are commercially
available [27]. However, the large size of these antennas makes them less suitable for
most commercial applications and particularly not feasible for portable or handheld uses
where space is at a particular premium. Therefore, there is a great need for low-cost,
compact, easy-to-manufacture UWB antennas that are omni-directional, radiationefficient, and have low distortion. These antennas should also facilitate integration with
UWB CMOS RFIC chips. Since a small element antenna not only tends to be nondispersive, but also more compact, small element antennas are preferred in many
applications.
25
2.5.3 Simulation Tools
UWB antenna simulations can be performed in both time domain and frequency
domain, since time and frequency domain are connected through Fourier transform. But
considering the unique characteristic of UWB signal, very narrow width in time domain
and ultra wideband in frequency domain, the time-domain simulation should be the
better option. Since conducting analysis in the frequency domain requires the calculation
of far-field values for both amplitude and phase, and it must be done over a very wide
frequency range to be able to accurately extract the shape of the radiated pulse, which
makes certain calculations very time consuming or, due to lack of memory, impossible
to perform.
Typically, the electromagnetic simulation software available to UWB antenna
analysis can be classified as following categories:
1.
Finite-element method: The software based on finite-element method
(FEM) can simulate antennas with arbitrary shape and material, such as
Ansoft HFSS [28]. Hence they are the three-dimensional (3D) software.
However, when the antenna structure is complicated, FEM mesh number
is too large to consume all the computer resource. In addition, the
technique only works on single frequency at a time, implying that the
huge simulation time for ultra wideband simulation.
2.
Method of moments: The software based on method of moments (MoM)
runs much faster than that of FEM technique, especially for planar
antenna structure with regular shapes. MoM based software such as
Zeland IE3D [29] and Agilent MOMENTUM [30] do not use adaptive
meshing, instead user-defined grid density is used, therefore the
simulation time is reduced. One of the limitations is that most MOM
codes can only support planar structures with infinite dielectric layers.
Therefore sometimes they are called two and half dimensional (2.5D)
software, not suitable for the objects with arbitrary three-dimensional
shape.
26
3.
Finite-difference time-domain: The finite-difference time-domain
(FDTD) and other time-domain methods are inherently applicable for
antenna simulation with the ultra-short pulses. Software like CST
Microwave Studio [31] can simulate antennas with arbitrary shape and
material based on finite integration. So they are also 3D software. With
improved grid generation methods as well as increased computing
capacity, time-domain methods have the superior advantage for UWB
simulations.
2.5.4
Measurement Techniques
UWB antenna-to-antenna time-domain transmission response measurement can
be performed in both frequency-domain and time-domain [32]-[33]. Following is the
brief description for each method. As for the measurement techniques of impedance
matching performance of UWB antenna, chapter V will present the detailed description.
1.
Frequency-domain measurement: In frequency-domain, UWB antenna
can be measured using frequency sweeping technique with standard
vector network analyzer (VNA). This makes the measurement set-up
quite simple. Both amplitude and phase of the transmission are measured
and the time-domain performance is derived through Fourier transform.
Before measurement, the VNA should be calibrated over the whole UWB
frequency range to avoid artificial distortion of the waveform due to
aliasing. The frequency band that can be measured depends on the
frequency range of VNA.
2.
Time-Domain
measurement:
Typical
time-domain
antenna
measurement consists of a pulse generator and a digital sampling
oscilloscope. The pulse generator produces the pulse signal with very
short rising and falling times and excites the transmitting antenna; the
received waveform is captured by the oscilloscope which connected to
the receiving antenna. If the exciting pulse bandwidth is much larger than
27
the antenna system bandwidth, then the measured signal is a good
approximation of the system impulse response. Otherwise, deconvolution process is required to get actual transmission response of
UWB antenna when the bandwidth of excitation signal is comparable to
that of the antenna [32].
28
CHAPTER III
UWB TRANSMITTER DESIGN*
Impulse-type UWB transmitter normally consists of two fundamental parts: pulse
generator and modulator. The pulse generator is a key component for both the
transmitter and receiver. Based on the specific requirements, the pulse generator can
generate the impulse or monocycle pulse. Moreover, the generated UWB signal should
also meet the other specifications of the impulse UWB systems. As for the modulator,
depending on the different applications, PPM or BPSK modulation techniques can be
selected to modulate information bits directly into very short pulses.
The most essential specification of the pulse generator is the duration of the
output pulse. Small duration of the output pulse can provide very accurate resolution for
target detection or range accuracy. The generated pulse signal should also have good
shape with small distortion and minimum ringing tails. Another desirable function of
pulse generator is the tuning capability to generate pulse signals of different durations.
For instance, tunable pulse generators produce flexibility for UWB impulse radar [34].
Tuning ability is also useful for compensating variations caused by CMOS process. In a
tunable pulse signal, the wider pulse contains large low-frequency components, which
can propagate more deeply into a medium due to relatively low propagation loss at low
frequencies. The shorter pulse, on the other hand, has more high-frequency components,
thus making feasible higher range resolution. Therefore, a pulse that can change its
duration, especially by an electronic means, would have both advantages of increased
penetration (or range) and fine range resolution and is attractive for UWB systems. The
polarimetric video impulse radar described in [7] and [8] is a good example showing the
usefulness of tuning capability of the pulse generator. UWB tunable impulse and
*
© 2006 IEEE. Parts of this chapter are reprinted, with permission, from Meng Miao and Cam Nguyen,
“On the development of an integrated CMOS-based UWB tunable-pulse transmit module,” IEEE
Transactions on Microwave Theory and Techniques, vol. 54, pp.3681-3687, October 2006.
29
monocycle pulse transmitters have been recently developed using step-recovery and PIN
diodes and hybrid circuits [11]-[12].
Most existing UWB pulse generators are based on approaches developed for
radar applications and involve hybrid circuit techniques. Commercial UWB systems,
particularly those for wireless communications and sensors, prefer CMOS RFIC design
for low cost, low power consumption, and easy integration with digital ICs (and hence
better potential for complex system-on-chip). To this end, new types of integrated-circuit
pulse generators, different from the traditional hybrid circuits, should be employed based
on CMOS processes to produce pulses with sub-nanosecond pulse-width.
Recently, several CMOS pulse generator topologies were proposed for UWB
communications using IBM 0.18-µm BiCMOS [35], TSMC 0.18-µm CMOS [36]-[37],
and CSM 0.18-µm CMOS/BiCMOS [38] process. However, no experimental results
were presented for these circuits. The calculated pulse-widths and amplitudes of the
output pulses are around 300 ps and 20 mV [35], 300 ps and 22.97 mV [36], 380 ps and
650 mV [37], and 200 ps and 27 mV [38]. Furthermore, a square-wave and a 1.5-GHz
clock signal were used externally as the input in [35], [38] and [36] for simulations,
respectively.
In this chapter, a novel fully integrated impulse-type UWB transmitter is
presented. The tunable monocycle-pulse generator [39] and a BPSK modulator were
designed and fabricated using a standard low-cost CMOS process. The pulse generator
component produces 0.7 – 0.75 V peak-to-peak monocycle pulse with 140 – 350 ps
tunable pulse duration. Without the pulse-shaping circuitry, it can also generate 0.95 –
1.05 V peak-to-peak Gaussian-type impulse signal with 100 – 300 ps tunable pulse
duration. These pulse signals can be used for various UWB systems. An external clock
signal operating at a low frequency of only 10 MHz is needed. BPSK modulator controls
the pulse generator to generate positive or negative pulse signal depending on the “1” or
“0” digital data information.
This chapter is arranged as follows. First, some basic components used in the
transmitter design, such as CMOS inverter, delay cell, and NOR/NAND gate block will
30
be briefly described. Then come with the tunable pulse generator design as well as
BPSK modulator design. At last the tunable impulse-type transmitter with fully
integrated tunable pulse generator and BPSK modulator is presented.
3.1
Basic Components Overview
3.1.1
CMOS Inverter Basics
CMOS inverter is the essential element in the tunable pulse generator design, and
plays an important role in the delay cell and square-wave generator. In fact, the CMOS
inverter is a basic building block for digital circuit design. However, the operation of the
CMOS inverter in tunable pulse generator design is somewhat different with that of the
digital case. As shown in Fig. 3.1, the CMOS inverter consists of a pair of enhancementtype NMOS and PMOS transistors, operating in complementary mode. The input voltage
Vin is connected to the gates of both transistors. The substrate of the NMOS transistor is
connected to the ground, while the substrate of the PMOS transistor is connected to the
power supply voltage Vdd , to reverse-bias the source and drain junctions. Since VSB = 0
for both transistors, there will be no substrate-bias effects.
Vdd
Vin
Vout
Vin
Fig. 3.1. CMOS inverter circuit and its symbol.
Vout
31
Comparing with other inverter configurations, such as MOS current mode logic
(MCML), the CMOS inverter has two important advantages. The first and the most
important one is its virtually negligible steady-state power dissipation, except for small
power dissipation due to the leakage currents. While in other inverter structures like
MCML, a nonzero constant steady-state current is drawn from the power source when
the driver transistor is turned on, which results in a significant DC power consumption.
The other advantage of the CMOS configuration is that the voltage transfer characteristic
(VTC) exhibits a full output voltage swing between 0 V and Vdd . On the contrary,
MCML has the much lower swing voltage than Vdd , which cannot provide enough
driving voltage and is not suitable to our tunable pulse generator design.
The inverter threshold voltage Vth , which is considered as the transition voltage
and defined as the point where Vin = Vout , is an important parameter characterizing the
steady-state input-output behavior of the CMOS inverter [40].
VT 0,n +
Vth =
1
⋅ (Vdd + VT 0, p )
kR
⎞
⎛
⎜1 + 1 ⎟
⎜
k R ⎟⎠
⎝
(3.1)
where Vdd is the power supply, VT 0, n is the NMOS threshold voltage, VT 0, p is the PMOS
threshold voltage, and k R is defined as [40]
kR =
kn
kp
Here the transconductance parameters are [40]
(3.2)
32
k n = μ n ⋅ C ox ⋅
W
L
k p = μ p ⋅ C ox ⋅
(3.3a)
W
L
(3.3b)
where μ n is the electron surface mobility in the NMOS transistor, μ p is the surface hole
mobility in the PMOS transistor, Cox is the gate oxide capacitance, W and L are the
channel width and length respectively.
Since CMOS inverter is fully complementary structure, to achieve completely
symmetric output signal, the threshold voltages are set as VT 0 = VT 0,n = VT 0, p .
Therefore [40]
⎛ kn
⎜
⎜k
⎝ p
⎞
⎟
=1
⎟ symmetric
⎠ inverter
(3.4)
From [40]
⎛W
kn
⎝L
=
kp
⎛W
μ p C ox ⋅ ⎜
⎝L
μ n C ox ⋅ ⎜
⎞
⎛W
μn ⋅ ⎜
⎟
⎠n
⎝L
=
⎞
⎛W
μp ⋅⎜
⎟
⎠p
⎝L
⎞
⎟
⎠n
⎞
⎟
⎠p
(3.5)
The unity-ratio condition for the ideal symmetric inverter requires that
⎛W ⎞
⎜ ⎟
⎝ L ⎠n μ p
=
μn
⎛W ⎞
⎜ ⎟
⎝ L ⎠p
(3.6)
33
Since μ p (230 cm 2 / V ⋅ s ) is much smaller than μ n (580 cm 2 / V ⋅ s ) [40], to
achieve symmetric input-output performance in our CMOS inverter design, we select the
ratio of PMOS transistor to NMOS transistor as:
⎛W ⎞
⎜ ⎟
⎝ L ⎠p
=3
⎛W ⎞
⎜ ⎟
⎝ L ⎠n
(3.7)
For the condition of same minimum gate length L for both PMOS and NMOS
transistors, W p = 3 Wn .
3.1.2
Inverter Switching Characteristics
First some commonly used delay time definitions are introduced. As shown in
Fig. 3.2, the propagation delay times τ PHL and τ PLH determine the input-to-output signal
delay during the high-to-low and low-to-high transitions of the output, respectively. τ PHL
is the time delay between the V50% -transition of the rising input voltage and the V50% transition of the falling output voltage. Similarly, τ PLH is defined as the time delay
between the V50% -transition of the falling input voltage and the V50% -transition of the
rising output voltage [40].
The rising time τ rise is defined as the time required for the output voltage to rise
from the V10% level to V90% level. Similarly, the falling time τ fall is defined as the time
required for the output voltage to drop from the V90% level to V10% level [40].
34
Fig. 3.2. CMOS inverter delay-time definitions.
Assuming the input signal waveform is a step pulse with zero rise and fall times,
the propagation delay time for high-to-low output transition τ PHL of CMOS inverter can
be expressed as: [40]
τ PHL =
⎡ 2VT ,n
⎛ 4(Vdd − VT ,n ) ⎞⎤
C load
+ ln⎜⎜
− 1⎟⎟⎥
⎢
k n (Vdd − VT ,n ) ⎢⎣Vdd − VT ,n
Vdd
⎝
⎠⎥⎦
(3.8a)
35
Similarly, the propagation delay time from low-to-high output transition τ PLH of
the CMOS inverter is [40]:
τ PLH =
(
C load
k p Vdd − VT , p
)
(
)
⎡ 2 VT , p
⎛ 4 Vdd − VT , p
⎞⎤
⎢
+ ln⎜
− 1⎟⎥
⎜
⎟⎥
Vdd
⎢Vdd − VT , p
⎝
⎠⎦
⎣
(3.8b)
where C load is the load capacitance which combines capacitance at the output node [40].
Comparing the above time delay expressions, for τ PHL = τ PLH , we have the
condition of VT ,n = VT , p and k n = k p .
Considering the situation where the input voltage waveform is not an ideal pulse
waveform, but has finite rising and falling times, τ r and τ f , the corresponding
propagation delay times can be empirically expressed as [40]:
⎛τ r ⎞
⎟
⎝2⎠
2
(step input ) + ⎜
τ PHL (actual ) = τ PHL
τ PLH (actual ) = τ
2
PLH
⎛τ
(step input ) + ⎜⎜ f
⎝ 2
2
⎞
⎟⎟
⎠
(3.9a)
2
(3.9b)
where τ PHL (step input ) and τ PLH (step input ) are the propagation delay time values for
step pulse input waveform given in (3.8).
Assuming the input voltage of the CMOS inverter is an ideal step waveform with
negligible rising and falling times, the average power dissipation of the CMOS inverter
can be written as: [40]
Pavg = Cload ⋅ Vdd2 ⋅ f
(3.10)
36
From (3.10) we can find that the average power dissipation of the CMOS inverter
is proportional to the switching frequency f. Since in our pulse generator design the
frequency of the clock signal is only 10 MHz, comparing with MCML structure, where
the static power consumption is Vdd ⋅ I , hence the CMOS inverter has the much smaller
average power dissipation.
3.1.3
Two-input NOR/NAND Gate Blocks
Fig. 3.3 shows the circuit diagram of a two-input CMOS NOR gate block. The
circuit consists of series-connected complementary PMOS transistors and parallelconnected NMOS transistors. The input voltages V A and V B are applied to the gates of
one NMOS and PMOS transistors respectively.
Vdd
VA
VB
Vout
VA
Vout
VB
Fig. 3.3. CMOS NOR2 gate block and its symbol.
For NOR gate block, the output voltage is high only at the condition that both
input signals V A and V B are low voltages. For all the other conditions, the output voltage
is always low. Based on this characteristic, NOR gate block can be used to generate
37
positive impulse signal in our pulse generator design by adjusting the time difference
between two low-voltage input signals to a very small value.
Fig. 3.4 shows the circuit diagram of a two-input CMOS NAND gate block. The
circuit consists of parallel-connected PMOS transistors and series-connected
complementary NMOS transistors. The operating principle is exact dual of the CMOS
NOR gate block. Therefore for NAND gate block, the output voltage is low only at the
condition that both V A and V B are high voltages. For all the other conditions, the output
voltage is always high. Hence the NAND gate block can be used to generate negative
impulse signal in pulse generator design by controlling the time difference between two
high-voltage input signals to a small value.
Vdd
VA
Vout
VA
Vout
VB
VB
Fig. 3.4. CMOS NAND2 gate block and its symbol.
3.1.4
Tunable Delay Cell
Variable delay elements are often used to manipulate the rising or falling edges
of the clock or any other signal in ICs. There are three different kinds of delay element
architectures in CMOS VLSI design: transmission gate based, cascaded inverter based,
and voltage controlled based [41]. Here we select the voltage-controlled shunt-capacitor
38
delay element as the tuning delay cell in the tunable pulse generator design because of its
relatively simple structure [42]-[43].
Fig. 3.5 shows the basic circuit of the voltage-controlled shunt-capacitor delay
element. It consists of a shunt-controlled transistor M1 and the shunt MOS capacitor M2.
The control voltage Vctrl adjusts the resistance of the shunt transistor M1, which
connects the load capacitance M2 to the output of a logic stage. Tuning voltage Vctrl
modulates the resistance of shunt transistor M1, which is equivalent to changing the
effective shunt capacitor value to the output of the inverter. Larger value of Vctrl
decreases the resistance of the shunt transistor M1, so the effective shunt capacitance at
the logic gate output is bigger, producing a larger time delay. By selecting a suitable size
shunt capacitor M2 with respect to the specific output capacitor load, the desired
continuous time tuning range can be achieved. The tunable capability of this shuntcapacitor delay element plays an important role in our tunable pulse generator design,
and the details will be described in next section.
Vin
M1
Vout
Vctrl
M2
Fig. 3.5. Shunt-capacitor delay element.
39
3.2
Tunable Pulse Generator Design
Pulse generator is a fundamental component in impulse-type UWB systems. It
can function as a source for the transmitter or an internal source for the template signal
in the receiver. The continuous tunable advantage makes this pulse generator immune to
the CMOS process variations and temperature changes. Fig. 3.6 shows the block
diagram of the proposed CMOS UWB tunable monocycle pulse generator. It integrates a
tuning delay circuit, a square-wave generator, an impulse-forming circuit, and a pulseshaping circuit in a single chip.
Tuning
delay
Square wave
generation
Impulse
forming
Pulse
shaping
Tunable
delay cell
A
NOR
Input
Reference
cell
B
C
D
Output
Fig. 3.6. Block diagram of CMOS UWB tunable monocycle pulse generator chip.
3.2.1
Tuning Delay Component
The tuning delay component includes a pair of parallel tunable delay cell and
reference cell using shunt-capacitor delay elements [43], as shown in Fig. 3.7. M2 is a
NMOS-type capacitor. The NMOS transistor M1 controls the charging and discharging
current to the capacitor M2. The only difference between the circuits of the tunable delay
cell and reference cell is the gate voltage of the shunt transistor M1, which controls the
charge current. For the tunable delay cell, variable control voltage Vctrl between 0 V and
Vdd is applied to the gate of transistor M1 to produce continuous delay variation. On the
40
other hand, for the reference cell, the gate of the transistor M1 is directly connected to
the ground, so the gate voltage of M1 is fixed to zero, therefore the time-delay is
constant and provides a reference position to the tunable delay cell.
Vin
M1
Vout
Vin
M1
Vout
Vctrl
M2
M2
(a)
(b)
Fig. 3.7. Circuit schematics of tunable delay cell (a) and reference cell (b).
The advantage of using two identical delay structures is that the relative timedelay between the two paths can be easily controlled. Another reason is that for single
delay cell situation, under the perfect condition, the delay cell is equivalent to an
infinitesimal capacitor when the gate voltage of the shunt transistor M1 is 0 V. However,
in reality, there always exists the leak current inside the shunt transistor M1 and makes
the effective capacitor a finite value. That means for the method where only single delay
cell is used, an inherent minimum absolute time delay always exists caused by the nonperfect delay cell, and the value of this time delay sometimes is much larger than the
minimum pulse width required to achieve. Therefore single delay cell topology prevents
us to design the pulse generator with extremely narrow pulse signal, even it occupies less
die area. With the adoption of the parallel delay elements, this parasitic time delay effect
can be totally eliminated, and the minimum relative time difference achieved can be as
small as possible. This advantage guarantees the designed pulse generator to produce the
pulse signal with extremely small pulse width. The larger the value of capacitor M2, the
41
broader the tuning range of the generated pulse width. Hence by tuning the gatecontrolled voltage Vctrl within the range of 0 V to Vdd , the pulse signal with different
pulse width can be achieved.
Another issue concerning the delay element is that the pair of parallel delay cells
is located at the first stage of the entire pulse generator circuit, directly in front of the
square wave generator. This arrangement helps reduce the strict requirement for the
delay element design. As the input signal of the pulse generator is the sinusoidal signal
with the frequency of only 10 MHz, which is much lower comparing to the maximum
operating frequency of the CMOS inverter and delay cell. The extra capacitor load
introduced by the tuning delay cell has negligible effects on the rising and falling times
of the final output signal of the CMOS inverter, with the reasonable tuning range of the
time delay around 500 ps. If the tuning delay cells succeed the square wave generator
and precede the impulse-forming circuit, which seems a straightforward topology to
generate tunable delay at the first glance, it actually brings other potential problems on
the delay cell design. The reason is very clear, the signals produced by square wave
generator have the very sharp rising and falling edges, normally in the order of less than
100 ps, which correspond to the frequency components of more than 10 GHz. After
passing the delay cell, the signal should keep the same rising and falling times, which
means the operating frequency of the delay cells should be more than 10 GHz; this
makes the delay cell design a really difficult work. Furthermore, the input capacitor of
the next stage impulse-forming circuit is very large because of the driving capability
requirement; to achieve the same time delay range of 500 ps, the size of the shuntcapacitor M2 should increase dramatically.
3.2.2
Square Wave Generator
For the tunable pulse generator design, the tunable delay cells that can produce
the extremely short relative time difference between two signal paths are certainly
important to generate the pulse signal with very narrow pulse width, but it is still not
enough if only these components are involved in pulse generation. There are also other
42
factors affecting the final pulse signal performance, and these parameters are the rising
and falling times of the generated square wave signals.
The function of the square-wave generator is to produce a square-wave signal
with very short rising and falling times when a sinusoidal clock signal is fed to the
circuit. Sharp rising/falling time is needed as the minimum width of the impulse signal
generated in the subsequent stage is determined by the rising and falling times of the
feed square-wave. The succeeding stage of square wave generator is the impulseforming block, whose size should be large enough to provide the driving capability for
the next stage circuit, therefore the input capacitor of the impulse-forming block is very
large. To drive this large capacitance effectively without sacrificing rising/falling edge
performance, a series of CMOS inverters with increasing size for each step, i.e., a buffer
circuit, is used to increase the drive capabilities and shorten the rising and falling times
of the square-wave signal.
A0(Wp1/Wn1)
A1(Wp1/Wn1)
In
AN-1(Wp1/Wn1)
Out
......
1
2
N
Cload
Fig. 3.8. Cascade of inverters used to drive a large load capacitance.
Consider the cascade circuit of N inverters driving a load capacitance C load ,
which is shown in Fig. 3.8, where A is the constant larger than 1, W p1 and Wn1 are the
channel widths of the PMOS and MOS of the first CMOS inverter respectively. Each
inverter is A times larger than the previous one, therefore each inverter’s input
capacitance is larger than the previous inverter’s input capacitance by a factor of A [44]:
43
C in 2 = A ⋅ C in1 , C in 3 = A 2 ⋅ C in1 , KK , C inN = A N −1 ⋅ C in1
(3.11)
The corresponding effective switching resistances are [44]:
Rn , p 2 =
Rn , p1
A
, Rn , p 3 =
Rn , p1
A
2
, KK , Rn , pN =
Rn , p1
A N −1
(3.12)
where the effective switching resistance of the first CMOS inverter Rn , p1 is defined as
[44]
Rn , p1 =
μ n C ox
2
Vdd
(Vdd − VTHN )
2
Vdd
L
L
+
W
Wn1 μ p C ox
(Vdd − VTHP )2 p1
2
(3.13)
Therefore, for each stage of the buffer, same delay of Rn , p1 ⋅ C in1 is achieved.
Typically, assume the load capacitance C load has the following relation with
input capacitance of the last inverter of the buffer [44]:
C load = A ⋅ C inN = A N ⋅ C in1
(3.14)
We can determine the factor A:
⎛C
A = ⎜⎜ load
⎝ C in1
⎞
⎟⎟
⎠
1/ N
(3.15)
Therefore the total delay of the inverter buffer can be found from [44]
(τ PHL + τ PLH )total
= 0.7 ⋅ N (Rn1 + R p1 )(C out1 + A ⋅ C in1 )
(3.16)
44
where C out1 is the total capacitance on the output of the first inverter, which includes the
sum of the output capacitance of the inverter, any capacitance of interconnecting lines,
and the input capacitance of the following stage.
For the square wave generator in the tunable pulse generator design, minimum
time delay is not an essential parameter, so the value of factor A can be selected other
than ℮ = 2.72 (corresponding to minimum time delay condition) [44] to reduce the stage
number of the square wave generator. During the square wave generator design, the size
of the inverters sets the rising and falling times; however, there are some constraints that
should be considered. First, the size of the first stage inverter should be chosen with a
small value, so that the input capacitance Cin1 of the CMOS inverter is small enough to
maintain the large enough ratio of C shunt to Cin1 , where C shunt is capacitor M2 of tuning
delay cell. Therefore the broad enough tuning range is achieved. If the size of the first
stage inverter increases too much, to keep the same time-delay tuning range, the size of
the shunt-capacitor in tuning delay element has to increase accordingly. This will
consume more die area. Another problem is that if too large inverters are used, according
to equation (3.12), the number of buffer stages N in the square wave generator must be
increased, which increases the power consumption. The last demand was that the rising
and falling times should be approximately the same, which is important to the symmetric
pulse signal generation. This was accomplished by making the PMOS transistor about 3
times larger than the NMOS transistor in each inverter because of the different carrier
surface mobility in PMOS and NMOS [44].
3.2.3 Impulse-forming Block
The impulse-forming block can be designated to generate positive or negative
impulse signal, depending on which gate block was selected as the impulse-forming
core. If the NOR gate block is used in the impulse-forming block, the output signal is
positive impulse; for the NAND gate block, the negative impulse signal is generated.
From now on, only impulse-forming block with positive impulse will be described, the
45
analysis of the impulse-forming block with negative impulse signal can follow the
similar design topology.
The impulse-forming block is made up of an inverted delay stage and a NOR
gate block, as shown in Fig. 3.6. The main purpose of the NOR gate block is to generate
a positive impulse-like signal and provide driving capability to the next stage. This
impulse should also be able to evoke the impulse response of the succeeding component
to further produce a monocycle pulse (or other kind of pulse waveforms as needed for
UWB systems). The function of the inverted delay stage is to provide one input of the
NOR gate block with a square wave signal, which is the reverse replica of the other input
signal. As the signal produced by square wave generator has the extremely-narrow
symmetric rising/falling edges, the size of this inverter should be selected to provide
enough driving capability to maintain the same rising/falling edges for the output signal.
With the help of the previous stage tuning delay component, the time difference between
two input signals of NOR gate block can be adjusted continuously to generate the
positive impulse signal with tunable pulse width.
3.2.4
Pulse-shaping Circuit
The last stage of the tunable monocycle pulse generator is the pulse-shaping
circuit, which consist of a shunt on-chip spiral inductor and a series metal-insulatormetal (MIM) capacitor, operating as a high pass filter (HPF). The on-chip octagonal
shape spiral inductor was designed using the EM software IE3D [29] to achieve the
improved quality factor Q comparing with the inductor library model provided in
foundry design kit. By optimizing the values of spiral inductor and MIM capacitor, the
pulse-shaping circuit functions approximately like a differentiator for the designed
tunable impulse signal. As a result, a monocycle pulse signal with tunable duration can
be generated when the impulse-like signal from the impulse-forming circuit is fed to the
pulse-shaping circuit.
46
3.2.5
Tunable Pulse Illustration
Fig. 3.9 illustrates the voltage variations at different nodes A, B, C, and D of the
tunable monocycle pulse generator designated in Fig. 3.6 when a 10-MHz sinusoidal
clock signal is fed to the generator.
Tunable
delay
A
B
C
D
Fig. 3.9. Illustration of signal shapes at each node of tunable pulse generator shown in
Fig. 3.6.
As shown in Fig. 3.6, the input clock signal is divided equally into two paths: one
signal passing through the tunable delay cell in the top path and another going through
the reference cell in the bottom path. At node B, a square-wave signal (0 V to Vdd ) with
very short rising and falling times is generated and functions as one of the inputs to the
following NOR gate block. For the tunable delay cell, by choosing a suitable control
47
voltage Vctrl between 0 V and Vdd , another square wave with a different delay time is
generated at node A. This signal is the reversed replica of that at node B with a certain
time difference and acts as another input signal to the NOR gate block.
The output of the NOR gate block is at high state ( Vdd ) only when the inputs to
the NOR gate are both at low state (0 V). For all the other input states, the output are
always low (0 V). When these two reversed square waves at A and B are fed to the NOR
gate block, a narrow impulse-like signal is generated at node C. The width of this
impulse signal depends on the relative time difference between these two square-wave
signals and the widths of their rising and falling edges. The impulse signal at node C,
therefore, can be easily generated with a continuously tuning duration. A smaller time
difference between nodes A and B generates a narrower impulse with a smaller peak-topeak voltage on node C, while a larger time difference produces a broader impulse with
a higher peak-to-peak voltage. When the tunable impulse signal is sent to the pulseshaping circuit, a monocycle pulse signal with different durations is achieved at node D.
3.2.6
Simulation and Measurement Results
All the chips designed in this dissertation were fabricated using the standard,
low-cost TSMC 0.25-µm, 0.18-µm, or Jazz 0.18-µm CMOS process [45]-[47]. For
TSMC 0.25-µm, a single 2.5-V low supply voltage was used for the whole circuits,
while for TSMC 0.18-µm and Jazz 0.18-µm, a single 1.8-V low supply voltage was
applied. The design and simulation were performed using the Agilent Advanced Design
System (ADS) [48], Cadence Design Systems [49], TSMC 0.25-µm, 0.18-µm, and JAZZ
0.18-µm CMOS process Design Kit [45]-[47].
Fig. 3.10 shows the photograph of the tunable CMOS monocycle pulse generator
fabricated using Jazz 0.18-µm CMOS process. Comparing to the pulse generator
fabricated with TSMC 0.25-µm in [39], the proposed circuit achieves the improved
performance on pulse width and pulse tuning range, with the more compact size. The
monocycle pulse generator core itself occupies an area of 240 µm × 160 µm. The CMOS
tunable monocycle pulse generator circuit and other accessory components were
48
measured on-wafer in both time and frequency domains using a probe station, digitizing
oscilloscope, and spectrum analyzer.
Fig. 3.10. Photograph of the 0.18-μm CMOS tunable monocycle pulse generator chip
including pads for on-wafer probe measurement.
To verify the design concept of each component inside tunable monocycle pulse
generator, several separate components were fabricated and measured. All the
measurements are performed under the condition of 50-Ω load unless otherwise
specified.
49
First the square wave generator integrated with tunable delay cell is measured,
with the 10-MHz sinusoidal clock signal as the input. The capacitor value of shuntcapacitor M2 of the tuning delay cell was optimized through simulation with ADS [48]
based on the structure parameters shown in Table 3.1, to achieve 500 ps around delay
tuning range. The final capacitor value of the shunt-capacitor M2 was chosen as 0.2 pF
in simulation. The sizes of the inverters in corresponding square wave generator are
shown in Table 3.1.
Table 3.1. The sizes of inverters in square wave generator.
Transistor
Width (µm)
Length (µm)
First stage inverter
NMOS PMOS
5
15
0.18
0.18
Last stage inverter
NMOS
PMOS
80
240
0.18
0.18
1.5
Output Signal (V)
1.25
1
0.75
0.5
0.25
0
0
50
100
150
Time (ns)
200
250
Fig. 3.11. Output signal of square wave generator.
300
50
The measured output signal of the tunable square wave generator with the abovementioned structure parameters is shown in Fig. 3.11, with the period of 100 ns. The
calculated pattern is presented in Fig. 3.12 for comparison purpose. The rising and
falling edges of the generated square wave signal, corresponding to the delay tuning
voltage Vctrl of 0 V and 1.8 V respectively, are presented in Fig. 3.12 as well in details.
Fig. 3.12. Rising and falling edges of tunable square wave signal.
As shown in Fig. 3.11, the generated waveform from tunable square wave
generator is symmetric and has the good square wave shape, which validates the design
of this component. In addition, Fig. 3.12 presents the important information about delay
tuning range and rising/falling edges, which are the critical factors in tunable pulse
generator design. As shown in Fig. 3.12, the measured tuning range of this tunable
square wave generator is around 400 ps, which is a little narrower than the simulated
one. Since the delay tuning range is in proportional to the ratio of the shunt-capacitor to
the input capacitor value of the first stage inverter of the square wave generator, the
parasitic capacitor associated with the inverter makes the overall input capacitor value
larger than the simulated one, which results in the reduced capacitor ratio, therefore, the
smaller tuning range. However, the 400 ps delay tuning range still can meet the
51
requirement of the tunable pulse generator design. The details of rising and falling edges
in Fig. 3.12 also confirm the symmetry of the generated square wave. Comparing with
simulation results, measured rising and falling edges (10% to 90%) have the width of
around 40 ps, which is close to the simulated results. The difference between two results
is caused by the parasitic capacitors associated with stage inverters of the square wave
generator. The parasitic resistance makes the high-level voltages of the measured results
a little lower than the simulation. Because of the very compact structure, extremely short
interconnecting lines, and large enough vias used in the circuit, the resulting parasitic
resistance is not big, hence the difference is not much.
0
-5
Magnitude (dB)
-10
-15
-20
-25
-30
-35
0
5
10
Frequency (GHz)
15
20
Fig. 3.13. Transfer function of designed pulse shaping circuit.
Next, the performance of the pulse shaping circuit was checked, in both
frequency-domain and time-domain. The designed shunt on-wafer spiral inductor has the
inductor value of 0.53 nH, and the selected series MIM capacitor is 0.4 pF. Fig. 3.13
52
shows the simulated transfer characteristics of this high pass filter (HPF). The
corresponding measured time-domain results for input impulse signal with different
pulse widths are shown in Fig. 3.14. Here the commercial pulse generator was used to
generate the positive impulse signal with different pulse widths.
As shown in Fig. 3.13, the pulse-shaping circuit effectively attenuates the lowfrequency components of the input signal below 3GHz. The measured time-domain
performance of the pulse-shaping circuit also confirmed the design validity as shown in
Fig. 3.14. The input signals are impulses generated by the commercial pulse generator
with 1 Vp-p and pulse widths of 100, 200, and 300 ps, respectively. The output signals
from the pulse-shaping circuit are clearly the monocycle pulse signals with amplitude of
0.8 Vp-p and almost symmetric positive and negative shapes. Therefore the proposed
pulse-shaping circuit can work effectively to generate the monocycle signal when the
input impulse signal is within the pulse width range of 100 to 300 ps, which is the
operating range of the proposed pulse generator.
Fig. 3.14. Pulse-shaping circuit performance for impulse input.
53
Table 3.2. The size of NOR gate block.
Transistor
Width (µm)
Length (µm)
NMOS
80
0.18
PMOS
320
0.18
To verify the design concept for generating tunable impulse, a separate chip
without the pulse-shaping circuitry was first measured. The parameters of the impulseforming component of the circuit, i.e. NOR gate block as shown in Fig. 3.3, are given in
Table 3.2. Large size transistors were selected to provide enough driving capability for
the external 50-Ω load. To reduce the parasitic capacitor and resistor effects, multiplefinger gate structure was applied to all the transistors of the circuit to improve the high
frequency performance and output power of the generated impulse signal.
Fig. 3.15. Measured and simulated impulse signals with tunable pulse duration.
54
The measured and calculated impulse signals with different durations are shown
in Fig. 3.15 for a 50-Ω load condition, and are expectedly similar to the illustrated
voltage waveforms at node C shown in Fig. 3.9. Impulse signals having 0.95 – 1.05 V
peak-to-peak voltage with 100 – 300 ps tunable pulse duration were measured. The pulse
duration is defined at 50% of the peak amplitude. The pulse width tunability is achieved
by varying the gate control voltage Vctrl of the tunable delay cell within the range of 0 V
to Vdd . Fig. 3.15 also shows clearly that the generated impulse signals have a common
rising edge, whose position is only determined by the falling edge of the square wave at
node B; while the position of the falling edge of the generated impulses is determined by
the rising edge of the square wave at node A and the tunable relative time offset between
nodes A and B. It is noted that the measured waveforms are very symmetrical with
almost no distortion. Good symmetry and low distortion are important for most pulse
applications. As can be seen, the measured results are well matched to the simulated
ones. Comparing to the previous work using TSMC 0.25-µm in [39], the tuning duration
range with constant pulse amplitude improves a lot.
It should note that the final impulse signal generated generally consists of three
parts: rising edge, tunable relative time offset, and falling edge, as shown in node C of
Fig. 3.9. For impulse with very narrow pulse width, only part of the rising and falling
edges of the square waves are involved in the pulse forming, resulting in amplitude
much smaller than those for wider pulses do. When the pulse width reaches a certain
value, the full rising and falling edges of the square waves and tunable relative timeoffset part all contribute to the pulse generation, so the amplitude of the generated
impulse signal does not change anymore, and different tuning relative time-offsets will
only change the final pulse width. Consequently, there is not much difference in
amplitude for different impulse signals if the pulse width exceeds the certain value. As
for the situation where the impulse signal with minimum pulse width is desired, there is
a compromise between the minimum pulse width and the signal amplitude, since the too
narrow pulse will sacrifice too much pulse energy. Using a better technology such as
0.13-µm RFCMOS process would improve the tuning range of pulses with uniform
55
amplitude and the amplitude of the minimum width pulse, because the better process
will achieve the much sharper rising/falling edges of the square wave, which means the
pulse with much narrower minimum width. Hence the corresponding pulse tuning range
with constant pulse amplitude is extended.
To verify the frequency response performance of the generated impulse signals,
the power spectral density (PSD) of the impulse signal was also measured using a
spectrum analyzer which can cover the frequency of 9 KHz to 22 GHz. Fig. 3.16
displays the measured PSD of the impulse signals with 100 ps and 300 ps pulse
durations respectively. The measured results clearly show that, for impulse signals,
major PSD components always concentrate on low-frequency range approximately to
DC. Accordingly, the bandwidth of the impulse signal was changed simply by tuning the
control voltage of the delay cell. For 100 ps impulse in Fig. 3.16(a), the first null
frequency of the PSD appears at 8 GHz, while for 300 ps impulse in Fig. 3.16(b), the
first null frequency is around 3.5 GHz. Therefore the above results verified the design of
the tunable impulse generator module. The proposed tunable impulse generator can be
used further to generate tunable monocycle pulses.
-40
-40
-45
Power Density (dBm)
Power Density (dBm)
-45
-50
-50
-55
-55
-60
-65
0
2
4
6
8
Frequency (GHz)
10
12
-60
0
2
4
6
8
Frequency (GHz)
(a)
(b)
Fig. 3.16. PSD of tunable impulse signal (a) 100 ps. (b) 300 ps.
10
12
56
400
350
Pulse Width (ps)
300
250
200
150
100
50
0
0.6
0.8
1
1.2
1.4
1.6
1.8
Tuning Voltage (V)
Fig. 3.17. Measured impulse width vs. tuning delay voltage.
The relation of the impulse width to the tuning delay control voltage Vctrl of the
tunable impulse generator is also investigated, and the result is presented in Fig. 3.17.
For the tuning voltage below 0.6 V, the transistor M1 is actually “off”, hence functions
as a very large resistor. The equivalent capacitor of the tunable delay cell therefore can
be ignored, and the very short relative time-offset between two paths produced the
impulse signal with very low amplitude that can not be used in UWB applications. When
the tuning voltage was increased from 0.7 V to 1.1 V, the impulse width increased
linearly from 45 ps to 90 ps, and the corresponding amplitude of the impulse signal
increased from 0.4 V to 0.9 V. Further increasing the tuning voltage to 1.6 V only
widened the impulse width from 90 ps to 340 ps, with the much faster width variation,
but the amplitude of the impulse signal increased is very little, and can be considered as
constant. That’s because the transistor M1 entered into the saturation region, the value of
the corresponding equivalent shunt capacitor does not change anymore. As shown in
Fig. 3.16, from 1.6 V to 1.8 V, the impulse width variation is not much. For the
57
applications where the requirement is that the pulse width variation should be in
proportional with tuning voltage variation, the shunt NMOS capacitor can be replaced by
other components with extended linear tuning range to meet the requirement.
Table 3.3. The size of NAND gate block.
Transistor
Width (µm)
Length (µm)
NMOS
80
0.18
PMOS
240
0.18
0.2
100 ps
200 ps
300 ps
0
-0.2
Voltage (V)
-0.4
-0.6
-0.8
-1
-1.2
-1.4
1
1.5
2
2.5
Time (ns)
3
3.5
4
Fig. 3.18. Measured negative impulse signals with tunable pulse duration
(NAND gate block).
As mentioned-above, when NAND gate block is used as impulse-forming
component in tunable impulse generator, the tunable impulse signal with negative
amplitude can be generated. The corresponding separate tunable negative impulse
58
generator was also fabricated and tested following the same above-mentioned test
conditions. Table 3.3 presents the parameters of the corresponding NAND gate block.
Fig. 3.18 shows the measured results of the negative tunable pulse signals. As shown in
Fig. 3.18, three impulse signals with pulse width of 100, 200, and 300 ps share the
common falling edge, with the amplitude range from 1 V to 1.2 V. The negative impulse
signals also maintain the good symmetric shape.
Finally, the measured tunable monocycle pulse signals are shown in Fig. 3.19 for
50 Ω-load condition. By changing the gate control voltage Vctrl of the tunable delay cell
in the range of 0 V to Vdd , symmetric monocycle pulses with 0.7 - 0.75 V peak-to-peak
voltage and 140 – 350 ps tunable pulse duration, at 50% of the peak amplitude, were
measured, which are also similar to the pulse shapes at node D of Fig. 3.8. To verify the
frequency response performance of the generated monocycle pulses, the PSD was also
measured using a spectrum analyzer. Fig. 3.20 displays the measured PSD of the
monocycle pulse with 140-ps pulse duration, showing that most of PSD is below -50
dBm over the 3.1 – 10.6 GHz band.
0.5
100 ps
200 ps
300 ps
0.4
0.3
Voltage (V)
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
4.5
5
5.5
Time (ns)
Fig. 3.19. Tunable monocycle pulse generator.
6
6.5
59
-45
Power Density (dBm)
-50
-55
-60
-65
-70
0
2
4
6
8
Frequency (GHz)
10
12
Fig. 3.20. Spectrum of tunable monocycle pulse signal.
3.3
BPSK Modulator Design
For impulse-type UWB transmitter design, BPSK modulation normally was
chosen to modulate a digital information data sequence to a pulse sequence [38], [50].
For the BPSK modulation, the polarities of the output pulse signals can be controlled by
the polarities of the information data levels. BPSK has an advantage over pulse
amplitude and position modulation due to the two times improvement in overall power
efficiency [15], an inherent 3-dB increase in separation between constellation points. In
this section, a simple level triggered pulse modulation circuit is developed to achieve the
BPSK modulation, which is fully integrated with the tunable pulse generators proposed
in above sections.
The block diagram of the proposed pulse modulator is shown in Fig. 3.21, which
includes two pulse generators and one switch. The input signal Vin (t ) of the pulse
generators is a 10-MHz clock signal. The pulse generators can produce both positive and
negative tunable pulse signals. The control input Vctl (t ) to the BPSK modulator is the
60
information data sequence to be transmitted, and the level of this modulation signal will
determine the polarities of the final output pulse signal Vout (t ) . When the digital
modulation signal is in low level, such as “0”, the output signal of the BPSK modulator
will be pulse signal with negative amplitude; while for digital information signal with
high level of “1”, the positive pulse signal will be generated at the output of the BPSK
modulator.
BPSK
modulator
Positive pulse
generator
Vin(t)
Vout(t)
Negative pulse
generator
Vctl(t)
Fig. 3.21. BPSK diagram block.
The proposed compact BPSK modulation circuit implemented in CMOS
technology is shown in Fig. 3.22, which consists the components of R1 , R2 , C1 , C 2 ,
M 1 , M 2 , and M 3 . Vinp is the input pulse signal with positive amplitude, and Vinn is the
input pulse signal with negative amplitude. Vctl is the input digital information data
sequence to be transmitted, which can be low level “0” or high level “1”. Vout is the
output signal of the BPSK modulator, which is loaded by the external 50-Ω resistor not
shown in the circuit. NMOS transistors M 1 , M 2 , and M 3 together form the multiplixer,
where M 1 and M 2 are used as two transmission gates and biased by the complimentary
control voltages controlled by M 3 . Thus at one time only one input signal can pass
61
through the transmission gate M 1 or M 2 , and feed to the 50-Ω load to generate the
modulated positive or negative pulse.
Vdd
R2
R1
Vctl
M3
Vinn
Vinp
C1
M1
Vout
M2
C2
Fig. 3.22. BPSK modulation circuit.
As shown in Fig. 3.22, when the modulating digital data is high level “1”, the
corresponding control signal Vctl is Vdd , hence the gate voltage of both M 1 and M 3 is
Vdd . Therefore, transmission gate M 1 is in the “on” condition, and transistor M 3 is “on”
in the saturation region. Hence the gate voltage of M 2 is close to zero. This makes the
transmission gate M 2 in the “off” condition. So only the positive pulse signal Vinp is
passed to the output of BPSK modulator. For the digital data information of low level
“0”, the corresponding control signal Vctl is zero, hence the gate voltage of both M 1 and
M 3 is zero. So transmission gate M 1 and M 3 are both “off”, and the gate voltage of
62
M 2 is close to Vdd , resulting the “on” condition of M 2 , and the negative pulse signal
Vinn is generated at the output of BPSK modulator.
For BPSK modulator, the transmission gates M 1 and M 2 should drive 50-Ω load
effectively. As larger transmission gate transistors mean smaller on-resistance [44], the
transmission gates M 1 and M 2 should be selected large enough to avoid amplitude
degradation. Table 3.4 provides the parameters of corresponding NMOS transistors.
Table 3.4. The size of transistors in BPSK modulator.
Transistor
Width (µm)
Length (µm)
M1
160
0.18
M2
160
0.18
M3
20
0.18
Fig. 3.23. Simulated insertion loss and isolation of BPSK modulator.
63
Fig. 3.23 and 3.24 present the simulated performance of BPSK modulator in
frequency-domain and time-domain. 1.5 dB insertion loss was achieved on the entire
UWB band, while the isolation is below 20 dB over most of the frequency range. As
shown in Fig. 3.24, the output signals keep the same shape as the input pulses for both
“1” and “0” conditions.
Fig. 3.24. Simulated time-domain performance of BPSK modulator.
3.4
Tunable Transmitter Design
In this section, the tunable impulse-type UWB transmitter front-ends, integrating
the tunable pulse generator with BPSK modulator on a single CMOS chip, were
presented based on the tunable impulse generator or monocycle pulse generator and
BPSK modulator design described in previous sections.
64
Oscillator
(PRF)
Tunable Impulse
Generator
Inverter
BPSK
Modulator
Vout
Vctl
Fig. 3.25. Diagram block of tunable impulse generator with BPSK modulator.
First, the tunable impulse generator integrated with BPSK modulator is presented
in Fig. 3.25. The proposed UWB transmitter consists of the tunable impulse generator,
CMOS inverter, and BPSK modulator. The tunable impulse generator driven by the 10MHz input clock signal produces the impulse with tunable duration, which is divided
equally into two paths: one impulse signal is directly sent to BPSK modulator,
funcitoning as the positive impulse input signal Vinp , as shown in Fig. 3.22; another path
signal goes through the CMOS inverter to the BPSK modulator to generate the negative
pulse signal, therefore the impulse signal Vinn with negative amplitude is fed to the
modulator. Considering the extremely narrow rising and falling edges of the impulse
signal, the CMOS inverter with large size was chosen to provide enough driving
capability for the impulse, otherwise the generated negative impulse Vinn at the output of
CMOS inverter degrades the pulse width and amplitude performance. The output signal
Vout of the transmitter is determined by the external modulating signal Vctl to generate
the tunable impulse signal with positive or negative amplitude.
The layout of the impulse generator integrated with BPSK modulator is shown in
Fig. 3.26, which is fabricated with Jazz 0.18µm RFCMOS technology. The overall size
of the circuit is 580 µm × 550 µm, including the RF pads and DC pads for on-wafer
measurement purpose. The external modulating signal was fed to on-wafer pad of the
circuit through DC probe. The measurement results of the output modulated impulse
65
signals are shown in Fig. 3.27 for different modulation signals, where Vctl = Vdd is high
level, and Vctl = 0 is low level.
Fig. 3.26. Photograph of impulse generator with BPSK modulator.
(a)
(b)
Fig. 3.27. Measured results of impulse transmitter. (a) High level, (b) low level.
66
Fig. 3.27(a) shows the positive tunable impulse signal with pulse width 100 ps
and 300 ps for the condition of high level modulation signal. The pulse widths are
comparable with simulated results, while the measured amplitude is somewhat lower
than simulated one, which caused by extra parasitic resistance from interconnection lines
that not fully included in the simulation. Comparing with the impulse signal in Fig. 3.15
generated by tunable impulse generator, the modulated impulse signals have the smaller
amplitude of 0.8 V, and they still keep the symmetric shape and similar pulse width. As
for the negative impulse signals shown in Fig. 3.27(b) for the condition of low level
modulation signal, the amplitude is reduced to 0.7 V, with some distortion at the top of
the pulse waveform at the bottom pulse peak position. The reason is that the input
negative impulse to the modulator is produced by the CMOS inverter, which in practice
attenuates the pulse amplitude, and expands the pulse width to some extent. The
alterative way is to replace the CMOS inverter generated negative impulse with the
NAND gate block based negative impulse generator, which will provide the good
negative impulse signal as shown in Fig. 3.18, with large enough amplitude to the BPSK
modulator. Of course the consumed power also increased accordingly.
Oscillator
(PRF)
Tunable Impulse
Generator
Inverter
BPSK
Modulator
Vout
Vctl
Fig. 3.28 Monocycle pulse generator with BPSK modulator.
For the tunable monocycle pulse generator integrated with BPSK modulator,
there are two configurations that can be used for circuit realization. One setup is to put
the BPSK modulator succeeding two monocycle pulse generators that can generate
positive or negative monocycle pulse signals (here the positive monocycle pulse is
67
defined as the monocycle pulse with left positive peak and right negative peak, while the
negative monocycle pulse is the signal with left negative peak and right positive peak.),
which seems a straightforward way to produce the modulated monocycle pulse signal.
However, two monocycle pulse generators occupy too much die space, and power
consumption of double monocycle pulse generators is another concerning issue.
The other topology of monocycle UWB transmitter is to succeed the previous
designed impulse transmitter with pulse-shaping module. So the modulated impulse
signal with positive or negative amplitude was shaped to the modulated monocycle pulse
signal with positive or negative amplitude. Since only one pulse-shape component is
used comparing with the first topology, the occupied die area of the circuit reduced a lot.
Hence the second configuration is selected and the final structure of the monocycle
BPSK transmitter is shown in Fig. 3.28.
The monocycle UWB transmitter consists of the tunable impulse generator,
CMOS inverter, BPSK modulator, and pulse-shaping component. 10-MHz clock signal
drives the tunable impulse generator to produce the impulse with tunable duration.
Positive impulse signal directly from the tunable impulse generator and negative impulse
signal from CMOS inverter were fed to BPSK modulator. Depending on the high or low
external modulating signal Vctl , the positive (high level modulation) or negative (low
level modulation) modulated impulse output of BPSK modulator was sent to pulseshaping circuit. Finally the modulated positive or negative monocycle pulse signal was
generated at the output of the pulse-shaping circuit.
The photograph of the final monocycle transmitter with BPSK modulator is
shown in Fig. 3.29, which is fabricated with Jazz 0.18µm RFCMOS technology [47].
The overall size of the circuit is 620 µm × 550 µm, including the RF pads and DC pads.
The measurement results of the output modulated monocycle pulse signals are shown in
Fig. 3.30 for different modulation signals where Vctl = Vdd is high level, and Vctl = 0 is
low level.
68
Fig. 3.29. Photograph of monocycle pulse generator with BPSK modulator.
Fig. 3.30. Measured results of monocycle pulse transmitter. (a) High level, (b) low
level.
As shown in Fig. 3.30, the modulated monocycle pulse signals with pulse width
of 100 ps and 300 ps have the peak-to-peak amplitude of 0.6 - 0.8 V, and the symmetry
69
of the signal shape is somewhat degraded compared with simulation results while the
pulse widths keep the same. The unsymmetrical problem is caused by BPF succeeding
the BPSK modulator.
70
CHAPTER IV
UWB RECEIVER DESIGN
The function of impulse-type UWB receiver is to receive the transmitted UWB
pulse signal through the receiving antenna and down-convert this input signal to the
baseband signal. Since the received pulse signal covers such a wideband, the design of
the impulse-type receiver that can down-convert the input signal and recover the downconverted signal waveform in the same form as the RF input signal would be the
challenging work.
As shown in chapter II, the architecture of the impulse-type UWB receiver is
much simpler than conventional narrow-band system and MB-OFDM UWB receivers. It
only consists of the UWB LNA, down-conversion mixer (or in other term, correlator),
template pulse generator, and other accessory circuits. Among these components, UWB
LNA and correlator are two essential circuits. The specifications of LNA and correlator
directly determine the final performance of the UWB receiver. In impulse-type UWB
systems, not matter what kind of modulation technique used, the corresponding
correlator and LNA with minimum NF are always indispensable components for
detection of the receiver. For wireless mobile devices, to reduce the cost and power
consumption, it is necessary to integrate all the UWB components on a single chip.
Considering the UWB frequency range involved from 3.1 GHz to 10.6 GHz, this
requirement represents a big challenge for current VLSI technology.
In this chapter, impulse-type UWB receiver based on RFCMOS technology was
investigated, with the focus on the module of LNA and correlator. Furthermore, the
structure-optimized and patterned-ground-shield (PGS) inductors were also studied to
replace the low-Q inductor model provided in foundry library. First, the individual UWB
LNA and correlator circuits employing optimized PGS inductors were designed and
implemented to verify the design topology. Then the integrated CMOS UWB receiver
front-end including UWB LNA, correlator, and template pulse generator was presented.
71
4.1
UWB LNA
4.1.1 LNA Design
A wideband LNA operating over the whole UWB band of 3.1 to 10.6 GHz is
definitely an essential component in both MB-OFDM and impulse-type UWB receivers.
This amplifier should exhibit the performance of wideband input matching to the 50-Ω
antenna, flat gain, good linearity, minimum possible noise figure (NF) over the entire
bandwidth and low power consumption.
For wireless communications systems, the first step of LNA design is to select
the transistors with fast speed and low-noise features. Traditional wideband amplifiers
employ the composite semiconductor such as GaAs transistors because of the intrinsic
superior frequency characteristics; while silicon technology is used to design and
implement amplifiers with less strict requirements, such as narrow-band systems
operating in lower frequency band, where smaller gain and larger parasitic effects are
acceptable.
With the rapid development of technology scaling and advances of more accurate
RF models, CMOS is quickly becoming the preferred choice for RFIC’s, and more and
more high-frequency wideband amplifiers employ the silicon transistors. In this section,
an individual LNA was designed and implemented over the UWB band with Jazz 0.18µm RFCMOS process. To facilitate the measurement, the output buffer was also
included to drive the external 50-Ω load. Lately, the LNA core without the buffer will
further integrate with UWB correlator to form the essential module of the impulse-type
UWB receiver.
There are many different options for the high-frequency wideband amplifiers
design depending on the requirements and applications. Typical methods include classic
shunt feedback amplifier, distributed amplifier, the cascaded common-source (CS), or
common-gate (CG) circuit topologies, as shown in Fig. 4.1 [51]. First, the advantages
and disadvantages of these topologies are briefly described concerning the power
consumption, die area, and noise figure, which will facilitate our UWB LNA topology
selection and design.
72
Vdd
Vdd
RL
Vdd
Z0
RF
Vin
RS
Vin
(a)
Vout
Vout
Vg
Vg
Vin
Isource
Vin
Ls
Z0
(b)
RL
Vout
...
...
...
Vout
Vdd
RL
(c)
(d)
Fig. 4.1 Various wideband LNA topologies. (a) Shunt feedback. (b) Distributed
amplifier. (c) Common-gate. (d) Cascoded common-source.
Shunt Feedback LNAs
For the shunt feedback amplifiers, the negative feedback achieves the
simultaneous impedance match at both input and output ports, and produce the relative
constancy of input and output impedances over a broad frequency range [51]. However,
as shown in Fig. 4.1(a), inherent larger C gs of CMOS transistor results the larger
parasitic input capacitance, which means the limited input impedance match bandwidth
at higher frequencies [52]. Furthermore, the resistive feedback network generates its own
thermal noise and the overall noise figure of the amplifier generally exceeds the device
Fmin by a considerable amount [51]. Therefore, the shunt feedback structure cannot
provide sufficiently low NF and high gain while consuming low power, which is the
important specification in UWB LNA design.
Distributed LNAs
In contrast with typical amplifier cascades, the overall gain of the distributed
amplifier depends linearly on the stage numbers; hence the distributed amplifier can
operate at substantially higher frequencies and achieve ultra wideband performance.
However, the cost of the power consumption is several times higher than in a singlestage amplifier. As shown in Fig. 4.1(b), the number of inductors used in the structure
73
results the large die area usage, which also makes this type of amplifier less attractive to
UWB applications.
Common-gate LNAs
The common-gate amplifier seems to be the good choice for UWB radio in terms
of power dissipation and die area. As shown in Fig. 4.1(c), the wideband input match can
be achieved simply by proper selecting device size and adjusting the bias current such
that 1
gm
of the amplifying transistor is nearly 50 Ω over the broad frequency range
[51], and no area-intensive, LC input matching network is needed. However, the lower
bound of noise figure for CG amplifier is about 3 dB [51], and will be even worse at
high frequencies and when gate current noise is taken into account. Hence the presence
of noisy resistances in the signal path such as channel resistance results in noise figure
degradation [51], and limits the minimum possible noise figure, which is an adverse
effect in UWB system.
Cascoded Common-source LNAs
The cascoded CS topology, shown in Fig. 4.1(d), is often used in wideband LNA
design for the ease of achieving a low noise figure and a high gain. The structure is
based on a narrowband inductively degenerated cascoded LNA that is extended to large
bandwidths by including the band pass filter (BPF) at the input, where the reactive part
of the input impedance is resonated over the BPF frequency range [52]. The main feature
of this topology is the ability to match the NF close to NFmin while also achieving power
match. These characteristics make the cascoded CS topology the preferred option for
UWB LNA design. The disadvantage is that the wideband LC matching network
contains multiple on-chip spiral inductors, which occupies much die area.
74
Vdd
LL
RL
Vdd
ZIN
C1
RS
Vout
M2
L1
LG
M1
Vin
L2
C2
CP
LS
ZIN
L
C
R
Fig. 4.2. Ladder matched UWB LNA.
Comparing the above-mentioned several wideband LNA topologies in terms of
noise figure, power dissipation, and die area, the cascoded common-source inductively
degenerated LNA, with extended ultra-wideband ladder matching network, was selected
to form the impulse-type UWB LNA. As shown in Fig. 4.2, the structure is based on the
narrow-band cascoded inductively degenerated common-source LNA [51]. The
cascoded configuration of transistors M 1 and M 2 reduces the Miller-effect and
improves the input-output reverse isolation as well as frequency response. Because of
the reverse isolation achieved by cascoded structure, the effects of M 2 , RL , and LL to
the input impedance can be negligible. The input impedance of the NMOS transistor M1
75
with inductive source degeneration shown in Fig. 4.2 is equivalent to the impedance of a
series RLC circuit, and R is given by [51]
R = ω T LS
(4.1)
where ωT = g m / (C gs + C P ) = g m / CT is the cut-off frequency of the transistor. To make
the UWB LNA design more flexible, an on-chip spiral inductor LG is placed in series
with the gate of M 1 , and external MIM capacitor C P is placed in parallel with C gs of
M1 .
Hence the input impedance of M 1 with inductive source degeneration can be
written as [52]
Z IN =
1
jω (C gs + C P )
+ jω (LS + LG ) + ωT LS
(4.2)
where the real part of Z IN is chosen to be equal to the source resistance of RS , and the
reactive part of the input impedance is resonated at the operating frequency with nearly
optimal NF [51].
The bandwidth of the narrowband inductively degenerated cascoded LNA is
extended by adding the series inductor-capacitor ( L1 , C1 ) and parallel inductor-capacitor
( L2 , C 2 ) to match the topology of a third-order Chebyshev bandpass filter, as shown in
Fig. 4.3, where R is the load of 50-Ω. Since the reactive elements of the filter, i.e., L1 ,
C1 , L2 , C 2 , L , and C determines the bandwidth and ripple of the passband, assume 0
dB power loss in the passband with ripple of ρ P , the input reflection coefficient can be
written as [52]
76
1
2
Γ = 1−
(4.3)
ρP
ZFILT
RS
C1
L
L1
L2
C2
C
R = 50 Ω
Fig. 4.3. Third-order Chebyshev bandpass filter.
In the passband of the Chebyshev BPF, if the input reflection coefficient is
smaller than -10 dB, the tolerable ripple of less than 0.5 dB can be derived from (4.3).
For the impulse-type UWB applications, assuming the filter passband of 3.1 – 10.6 GHz,
the three-section Chebysheve BPF structure was selected considering the compromise
between filter complexity and component values. The module Filter Design Guide of
ADS [48] was employed as the simulation tool to quickly derive the initial ideal
component parameters of the three-section Chebyshev bandpass filter for 50-Ω input and
output matching, which is shown in Fig. 4.3. The component values of the three-section
Chebyshev BPF are presented in Table 4.1, where L = LG + LS , and C = C gs + C P .
The simulated return loss and insertion loss of the three-section Chebyshev BPF
are shown in Fig. 4.4, which cover the UWB band of 3.1 – 10.6 GHz. The components
of three-section Chebyshev BPF will later be replaced with on-chip MIM capacitors and
EM-optimized spiral inductors to achieve the fully integrated LNA structure.
77
Table 4.1. Component values of third-order Chebyshev BPF.
L1 (nH)
1.65
C1 (pF)
0.47
L2 (nH)
1.64
0
L (nH)
1.65
C 2 (pF)
0.47
C (pH)
0.47
Insertion Loss
-5
Return Loss
Amplitude (dB)
-10
-15
-20
-25
-30
-35
-40
2
4
6
8
Frequency (GHz)
10
12
Fig. 4.4. Performance of three-section Chebyshev bandpass filter.
As shown in Fig. 4.2, in order to achieve the flat gain over the whole UWB band,
the shunt-peaking topology was employed, which include the series inductor LL and
resistor RL as the load [51]. The value of LL should be large enough to provide the large
gain at the higher frequency edge, and in the meantime, it must be small so that the
resonating frequency generated by LL and C OUT is much higher than the operating
frequency band, where C OUT is the total capacitance between the drain of M 2 and
ground [52]. As for RL , the zero frequency ω Z = R L / LL should be close to the lower
frequency edge of the band to improve the gain at the lower frequencies. RL is limited
78
by an upper value above which the voltage drop is such large that reduces the voltage
Vdd supplied to the drain of M2.
Next step is to analyze the voltage gain of UWB LNA over the whole frequency
band. First assume the input network of the LNA, i.e. the Chebyshev BPF filter, has the
transfer function that is approximately unity in the passband, therefore the input
impedance can be considered as RS over the passband, as shown in Fig. 4.2. Hence the
current to amplifying transistor M 1 is iin = vin / RS . In addition, the CMOS transistor
functions as the current amplifier at the high frequency, with the current gain of
β = g m /( jωCT ) [51].
Considering the shunt-peaking load of RL and LL , the overall output load can be
expressed as:
⎛
1
Z LOAD = ( RL + jωLL ) ⎜⎜
⎝ jωC OUT
⎞
RL + jωLL
⎟⎟ =
⎠ 1 + jωC OUT ( RL + jωLL )
(4.4)
Using (4.4) and current gain expression β = g m /( jωCT ) , the overall voltage
gain of the amplifier can be written as [52]:
vout
Z
gm
R L + jω L L
= − β ⋅ LOAD = −
vin
RS
jωCT RS 1 + jωC OUT ( RL + jωLL )
(4.5)
Above equation clearly shows that, at lower frequencies, RL plays an important
role in voltage gain determination; while at higher frequencies, the current gain roll-off
is compensated by load inductor LL . Furthermore, the spurious resonance introduced by
C OUT with LL has to be kept out from the passband.
For calculation of the noise performance of LNA, normally two major noise
contributors should be considered: the losses associated with the input network and the
79
noise generated by amplifying component M 1 . For the input network, as shown in Fig.
4.3, the MIM capacitors have the much higher quality factor than those of the on-chip
spiral inductors. Hence the noise contribution of the three-section Chebyshev BPF is
mainly due to the limited quality factor of the on-chip spiral inductors. To reduce this
part of noise, the structure of the inductors should be optimized with EM simulation and
PGS topology, to achieve the highest Q for the specific inductance value. The detailed
design topology and final inductor parameters of input network will be presented in next
section.
As for the noise contribution from M 1 , for specific bias current, the
corresponding transistor width should be selected in order to achieve the optimum noise
value. Considering the ultra wideband feature in our case, the noise performance of the
amplifier over the whole UWB band should be studied. Hence both minimum NF and
average in-band NF should be investigated in order to achieve the optimum noise
performance.
During the noise analysis, typical two-port system topology was followed
represented by input-referred noise current and voltage source. Also, 1 / f noise will be
ignored because of the amplifier’s high operating frequency. Shown in Fig. 4.5(a) is the
MOS transistor noise sources including the loading effect of the local feedback inductor
2
LS . ing
is the induced gate noise due to the coupling of the fluctuating channel charge
2
into the gate terminal, while ind
is the drain noise current due to the carrier thermal
agitation in the channel. The corresponding induced gate noise and drain current noise
are expressed respectively as [51]:
2
ing
Δf
= 4kTδg g
2
ind
= 4kTγg d 0
Δf
(4.6)
(4.7)
80
where k is Boltzmann’s constant, T is the absolute temperature in degrees Kelvin,
gg =
ω 2 C gs2
5g d 0
, δ = 1.33 − 4 and γ = 0.67 − 1.33 are excess noise parameters, and g d 0 is
the channel conductance at V DS = 0 [51].
vn2
M1
2
ing
2
ind
CP
M1
in2
CP
LS
(a)
LS
(b)
Fig. 4.5. Noise model for transistor M 1 . (a) M 1 noise sources. (b) Input-referred
equivalent noise generators.
Employing the conventional input-referred topology in [51], the noise sources of
M 1 were replaced with two correlated noise generators of in2 and v n2 , which are shown
in Fig. 4.5(b) [52]. As seen in Fig. 4.5(b), when the input is short-ended, only noise
generator in2 exists. As the transistor can be considered as current amplifier [51], for
2
2
noise source ind
, assume the input-referred noise current is ind
,input , we have the
following relation between them [51]:
81
ind
Δf
=
g m ind ,input
jωCT Δf
(4.8a)
where 1 / jωCT is the output impedance caused by output parasitic capacitor, hence we
have
ind ,input
=
Δf
jωCT ind
gm
Δf
(4.8b)
Therefore the total noise current generator in2 can be derived from above formula
as:
in
Δf
=
ing
Δf
+
ind ,input
Δf
=
ing
Δf
+
jωCT ind
gm
Δf
(4.8c)
As shown in Fig. 4.5(b), when the input is open-ended, the noise generator v n2
can be expressed as:
v
v
vn
= n,1 + n, 2
Δf
Δf
Δf
(4.9a)
where vn2,1 is the input-referred noise from transistor M 1 , and vn2, 2 is from LS caused by
in2 . The corresponding equations are:
vn,1
Δf
=
ind
g m Δf
(4.9b)
82
and
vn, 2
Δf
= jωLS
in
Δf
(4.9c)
From (4.9a) to (4.9c), the equivalent noise voltage generator is:
vn
Δf
=
ind
g m Δf
+ jωLS
in
Δf
(4.9d)
Normally, the input-referred noise voltage source v n2 is partially correlated with
the input-referred noise current source in2 . Hence v n2 can be expressed as the sum of two
components, one fully correlated, v n2,c , and the other, v n2,u , uncorrelated to the noise
current source in2 as follows:
2
2
vn2 vn , c vn ,u
=
+
Δf
Δf
Δf
(4.10)
and the corresponding correlation impedance Z c can be expressed as [52]:
Zc =
where [52]
v n2,c
in2
= jωLS +
1 + c pαχ
1
jωCT 1 + 2 c pαχ + ( pαχ )2
(4.11)
83
c=
*
ing ind
≈ − j 0.395
(4.12a)
2 2
ng nd
i i
p=
χ=
α=
C gs
CT
(4.12b)
δ
5γ
(4.12c)
gm
gd 0
(4.12d)
In the above formula, c is the noise correlation coefficient between the gate
noise and the drain noise; α represents the short-channel effects and was used to
estimate the transconductance reduction due to the velocity saturation and mobility
decrease for vertical fields.
The other two important parameters in NF calculation are the uncorrelated noise
sources in2 and v n2,u , and the corresponding equivalent noise resistance or conductance
can be expressed in the following formula respectively [52].
in2
γ
Δf
(ωCT )2 1 + 2 c pαχ + ( pαχ )2
Gn =
= 2
4 KT α g d 0
(
v n2,u
(
)
( pαχ ) 1 − c
γ
Δf
Ru =
= 2
4 KT α g d 0 1 + 2 c pαχ + ( pαχ )2
2
2
)
(4.13)
(4.14)
84
Following the conventional two-port system noise analysis, the NF of the LNA
can be written in terms of these parameters [51]:
2
F = 1+
Ru + Z c + Z S Gn
(4.15)
RS
where Z S = RS + jX S is the source impedance.
When the source impedance was selected as Z S = Z opt = Ropt + jX opt , the
minimum NF can be realized, and the corresponding Z opt can be expressed in the
following manner [51]
( pαχ ) 1 − c
Ru
=
+ Rc2 =
Gn
ωCT 1 + 2 c pαχ + ( pαχ )2
2
Ropt
(
)
(4.16a)
and
X opt = − X c = −ωLS +
1 + c pαχ
1
ωCT 1 + 2 c pαχ + ( pαχ )2
(4.16b)
From (4.12), c = 0.395 , p < 1 , α ≤ 1 , and χ < 1 , therefore the coefficient of
1
in (4.16b) is close to one, hence the optimum source impedance can be roughly
ωC T
achieved if the series combination of CT and LS can be resonated over the interested
frequency band [52]. With the help of three-section Chebyshev BPF input network, the
overall input reactance looking into the filter is resonated over a wide bandwidth, so X opt
= 0 is generated over the wide bandwidth, hence quasi-minimum NF can be realized
85
over the entire LNA bandwidth, and the corresponding NF can be simplified from (4.15)
as [52]:
F ≈ 1+
Ru
+ Gn RS
RS
(4.17)
With the help of above derived equivalent noise parameters, the final expression
of NF can be derived by inserting (4.13)-(4.16) into (4.17) as:
(
)
⎡ ( pαχ )2 1 − c 2
2
2
⎢
+ (ωCT RS ) 1 + 2 c pαχ + ( pαχ )
F ≈ 1+
2
αg m RS ⎢⎣1 + 2 c pαχ + ( pαχ )
γ
(
⎤
)⎥ (4.18)
⎥⎦
For CMOS transistor, the transconductance g m can be derived from the
following saturation drain current equation that is applicable for both long and short
channel devices [51]:
ID =
μ n C ox W
2
ρ2
(Vgs − Vt )([ Vgs − Vt ) (LE sat )] = WLC ox vsat E sat
L
1+ ρ
(4.19)
where E sat is the filed strength at which the carrier velocity has dropped to half the value
extrapolated from low-field mobility, Vt is the threshold voltage, and
v sat =
μn
2
E sat , ρ =
V gs − Vt
LE sat
=
Vod
LE sat
Hence the transconductance is obtained from (4.19) as:
(4.20)
86
gm ≡
∂I D 1 + ρ / 2 ⎡
W
W
⎤
⎡
⎤
=
μ C
Vod ⎥ = α ⎢ μ n C ox Vod ⎥ = αg d 0
2 ⎢ n ox
∂V gs (1 + ρ ) ⎣
L
L
⎦
⎣
⎦
(4.21)
From (4.12), p < 1 , α ≤ 1 , and χ < 1 . From (4.18), the larger transconductance
will produce the better noise performance. Also, as shown in (4.21), for the fixed g m ,
smaller size transistor results bigger α , hence the better NF is achieved. From
g m = 2 μ n C ox
W
I D [51], for fixed g m , smaller transistor means larger I D , therefore
L
larger bias current is preferred for NF performance.
During the noise analysis for transistor M 1 , the average NF value over the entire
operating frequency band is also an important parameter to evaluate because of the ultra
wideband of LNA. Hence for the specific bias current I bias , there is an range for the
width of the amplifying transistor M 1 that can be chosen to achieve the minimum
average NF. Therefore, in the UWB LNA design, as long as the noise performance is
mainly limited by the contribution of M 1 , which is the case as cascoded topology is used
[52], the better noise performance of the system can be achieved if the larger bias current
is applied, as shown in (4.18).
In the proposed LNA design, the bias current I bias = 5 mA is assumed, and the
minimum length of 0.18 µm was selected for both transistors M 1 and M 2 . Considering
the balance between the thermal drain noise and induced gate noise, the size of the
amplifying transistor M 1 was selected as 260 µm using (4.18). While for the cascoded
transistor M 2 , in order to reduce the parasitic capacitances, the smaller size is preferred,
on the other hand, a lower limit to the width of M 2 is set by its noise contribution
because the smaller size transistor produces the higher noise [52]. And the final width of
60 µm is selected for M 2 .
As the on-chip spiral inductor model in Jazz 0.18µm CMOS design kit only
provides the rectangular structure with low quality factor, which is not suitable for the
87
UWB LNA application, it is necessary to generate the integrated spiral inductors with
optimized Q and inductor value over the operating band to replace the low Q inductor
model. Hence electromagnetic simulation was performed based on the multiple-layer
CMOS structure, and this part of inductor optimization work was described in next
section. On the above circuit analysis, the gate-drain capacitance of M 1 C gd was first
omitted for the analysis simplicity. However, at the high frequency, the presence of C gd
complicates the input impedance Z IN and make it differ from the simple series RLC
model assumed. During schematic simulation, C gd is included, so the values of on-chip
components were optimized through the circuit simulation, and the finalized component
parameters are presented in Table 4.2.
Table 4.2. Final component values of LNA.
L1 (nH) C1 (pF) L2 (nH) C 2 (pF) LG (nH) C P (pF) LS (nH) LL (nH) RL (Ω)
1.63
0.45
1.32
0.06
0.61
2.65
85
1.08
0.65
Vdd
Vout
M3
Vdd
I0
Fig. 4.6. Source-follower buffer for UWB LNA.
V'out
88
For the UWB LNA, to facilitate the on-wafer measurement, the typical sourcefollower buffer was also included to drive the external 50-Ω load, which is shown in Fig.
4.6, where 50-Ω load is connected to the source of M3. The buffer consists of transistor
M 3 and current mirror to provide the independent biased current source of 5 mA. The
parameters (length and width) of the two transistors in current mirror were optimized to
produce the higher output impedance. The size of M 3 was selected as 60 µm to achieve
the transconductance of g m3 = 1 / Rext = 1 / 50 S. As the output voltage of the buffer is
only half of that produced by LNA without buffer, the gain of the final LNA structure
with buffer is 6 dB lower than that of the LNA core. The performance of the designed
UWB LNA was presented in section 4.1.3.
4.1.2
Inductor Optimization
To meet the various requirements for today’s consumer and military
communication systems, integrated spiral inductors with compact structure, high Q, and
high self-resonant frequencies are highly desired. However, for silicon-based RFIC’s,
the quality factor of the inductor degrades at high frequencies because of the energy
dissipation in the silicon substrate. Hence inductor design becomes a major bottleneck
for the RF CMOS design.
The typical structures of the spiral inductors on CMOS can be square, octagonal,
or circular shapes. Some inductors have tapered width as a function of the particular
turn. Furthermore, the structure can be single metal layer, parallel multiple metal layer
and serial multiple metal layers. Among them, the single-layer square spiral inductor is
most commonly used because of its area efficiency and drawing easiness, just like the
case of Jazz 0.18 µm RFCMOS Design Kit [47]. Unfortunately, the quality factor for the
square inductor is not the optimal compared with other geometries. Another problem is
that the noise coupling from the silicon substrate is potentially big due to the large
occupied die size. Therefore, selecting optimal structure and decoupling the inductor
from the substrate will enhance the overall performance of the spiral inductor. Based on
above consideration, the octagonal-shape inductors with patterned ground shield were
89
designed to replace the Design Kit model. This topology is fully compatible with
standard CMOS technology and has the advantage of increasing Q and improving
isolation.
C1
RS
L
Port 1
Csb
Port 2
CP
CP
Rsb
Rsb
Csb
Fig. 4.7. Inductor π-model.
The typical electrical model of an inductor on silicon is shown in Fig. 4.7, which
is usually being called inductor “π-model”. The physical elements of this two-port
network consist of C1 , RS , L , C P , Rsb , and C sb [51]. The series feedforward
capacitance C1 represents the capacitance due to the overlaps between the spiral and the
center-tap underpass, and its value is determined by the space between two metal
sections. RS is the resistance from metal trace and its value is controlled by the sheet
resistance and the length/width ratio of the metal traces. This resistance is due to the
energy losses of the skin effect in the spiral interconnect structure, as well as the induced
eddy current in any conductance media close to the inductor. C P represents the parasitic
90
oxide capacitance between inductor and silicon substrate. Rsb and C sb stand for the
substrate parasitic resistance and capacitance loss, respectively.
Since the resistance in the inductor metal traces causes the primary energy loss,
reducing the resistance of the conductors RS increases the Q of the inductor. The same
approach can be applied to reduce the substrate loss due to magnetic coupling and
electrical coupling to increase the quality factor. To reduce the resistance, a wider metal
trace is usually used. Multi-layer metals can also be used to reduce the inductor area or
increase the inductance per area. However, the disadvantage of multi-layer is the
parasitic capacitance between each layer that tends to reduce the self-resonant frequency
[51].
From Fig. 4.7, it can be seen that the inductor’s parasitic effects of the substrate
are a very important factor for inductor performance. To reduce the parasitic uncertainty,
a ground shield between inductor and substrate can be considered. For the solid ground
shield condition, the inductor’s magnetic field was disturbed and induced the eddy
current in the solid ground shield, which flowed in the opposite direction of the current
in the spiral. This negative mutual coupling results the reduced inductance, which makes
it not a good choice. To increase the resistance to the eddy current, the patterned ground
shield with slots orthogonal to the spiral was introduced, therefore the eddy current loss
is reduced. The corresponding structure is shown in Fig. 4.8, where the slots act as an
open circuit to cut off the path of the induced eddy current [53].
To effectively cut the eddy current, the slots should be narrow enough so that the
vertical electric field cannot penetrate through the patterned ground shield into the
underlying silicon substrate. To prevent negative mutual coupling, the ground ring under
the spiral inductor was intentionally broken into several sections, to reduce the current
loop effects [53]. To minimize the impedance to ground, the ground ring should be
grounded to the true ground as close as possible [53].
91
Fig. 4.8 Layout of patterned ground shield inductor
Based on the Jazz 0.18 µm RFCMOS process, the top metal layer M6 with the
thickness of 2.81 µm was selected to construct the octagonal spiral inductors. Comparing
with other five metal layers (0.57 µm), the corresponding resistance in the inductor
metal traces is much smaller. The Metal layer M1 was selected to form the patterned
ground shield, which has the structure as shown in Fig. 4.8. EM software Zeland IE3D
[29] was used to optimize the parameters of the top layer spiral inductors as well as the
patterned ground plane, to achieve the desired quality factor and the inductance value
over the operating frequency band.
The spiral inductors of the designed LNA, i.e., L1 , L2 , LG , LS , and LL , were
optimized using the above design topology. They were also fabricated separately on the
same LNA chip for the design verification. To measure the S parameters of the
inductors, calibration components including interconnect and pad metals were fabricated
and open and short patterns were measured on the same wafer to de-embed the pad
effect. Two-port S parameters were measured on the fabricated inductors using the
92
HP8510C network analyzer and RF probe station over the frequency range of 2 − 12
GHz. The parameter extraction was performed by IE3D with the de-embedded S
parameters to generate the measured Q and inductance values over the entire frequency
band.
All five optimized inductors of LNA were measured. To make the context
concise, here only the measured and simulated results for the designed spiral inductor L1
are presented in Fig. 4.9. For the quality factor, the maximum value appears around 6
GHz, and Q is larger than 10 over the whole UWB band as shown in Fig. 4.9(a). From
Fig. 4.9(b), it is clear that the inductance is almost independent to the frequency
variations. Comparing to the inductor model in design kit with same inductance value, Q
of the optimized spiral inductor has the obvious improvement. The better Q of the spiral
inductor indicates the improved NF for the final LNA, therefore enhance the LNA
performance.
20
2
Measured
Simulation
1.5
L (nH)
15
Q
10
1
0.5
5
0
2
Measured
Simulation
4
6
8
Frequency (GHz)
(a)
10
12
0
2
4
6
8
Frequency (GHz)
10
(b)
Fig. 4.9 Performance of the patterned ground shield inductor L1 . (a) Quality factor
Q. (b) Inductance L.
12
93
Fig. 4.10. Photograph of LNA chip.
4.1.3
LNA Fabrication and Test
The picture of the designed LNA fabricated in Jazz 0.18-µm RFCMOS process is
shown in Fig. 4.10, with the overall size of 0.88 mm × 0.7 mm, including the
corresponding on-wafer RF and DC-bias pads. All the measurements are performed on
wafer.
First, S parameters of LNA were measured over the operating frequency band.
Fig. 4.11 shows the measured and simulated return loss of input port, which agrees each
other reasonably well. The bandwidth of 2.9 – 12 GHz where the return loss is below -10
dB was achieved, which validated the input matching network design.
94
0
Measured
Simulation
-5
Return Loss (dB)
-10
-15
-20
-25
-30
-35
-40
2
4
6
8
Frequency (GHz)
10
12
Fig. 4.11. Return loss of input port for LNA.
0
Measured
Simulation
-5
Return Loss (dB)
-10
-15
-20
-25
-30
2
4
6
8
Frequency (GHz)
Fig. 4.12. Return loss of output port for LNA.
10
12
95
Fig. 4.12 presents the measured and simulated return loss of output port, and they
match very close. The bandwidth of 2 – 12 GHz where the return loss is below -10 dB
was achieved, which validated the output buffer design.
-30
Measured
Simulation
-35
Isolation (dB)
-40
-45
-50
-55
-60
2
4
6
8
Frequency (GHz)
10
12
Fig. 4.13. Reverse isolation of LNA.
For the reverse isolation of LNA, the measured and simulated results are shown
in Fig. 4.13 and they are very close. Over the frequency band, -40 dB isolation was
achieved, which proved the effectiveness of the cascoded LNA structure. Fig. 4.14
presents the gain performance of the LNA including buffer stage. The maximum gain of
12.4 dB was achieved over the band. For the 3-dB bandwidth, 2.6 – 9.8 GHz with the
minimum gain of 9.4 dB was achieved
with the help of shunt-peaking topology.
Furthermore, the ripple of the power gain is very small over the whole band. The
difference between the measured and simulated results at the high-frequency end is
caused by extra parasitic capacitance from output buffer, which was not fully considered
96
during the simulation, hence only partially compensated by the shunt-peaked inductor
load.
20
Measured
Simulation
15
Gain (dB)
10
5
0
-5
-10
-15
-20
2
4
6
8
Frequency (GHz)
10
12
Fig. 4.14. Power gain of LNA with buffer.
Another important parameter for UWB LNA design is phase linearity of S 21
over the operating frequency band, which is shown in Fig. 4.15. It indicates that the
phase performance with good linearity was achieved over the entire UWB band, and
matched with simulation result, which will help to generate the pulse signal with less
distortion at the LNA output.
97
300
Measured
Simulation
Phase (degree)
200
100
0
-100
-200
-300
2
4
6
8
Frequency (GHz)
10
12
Fig. 4.15. Phase performance of S 21 for LNA.
0.2
0.15
Amplitude (V)
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
Input
Output (Simulation)
Output (Measured)
1
2
3
Time (ns)
4
Fig. 4.16. Measured LNA performance in time-domain.
5
6
98
To verify the UWB LNA performance in time-domain, on-wafer time-domain
measurement was also performed with the digitalized oscilloscope, and the results are
shown in Fig. 4.16. The input signal is the monocycle pulse, with the 3 dB pulse width
of 150 ps and peak-to-peak amplitude of nearly 0.1 V, generated by the commercial
pulse generator. The output signal has the peak-to-peak voltage of 0.3 V, with the almost
symmetric pulse shape and relatively small ripple. Compared to simulated result, there is
some pulse-width expansion because of the gain roll-off at high frequency part.
Fig. 4.17 shows the noise performance over the entire UWB band, the measured
values follow the simulated one. The measured minimum NF is 4 dB at the frequency of
5.2 GHz, while the average NF over the entire UWB band is around 5.8 dB.
11
10
9
NF (dB)
8
7
6
5
Simulation
Measured
4
3
2
4
6
8
Frequency (GHz)
Fig. 4.17. Noise performance for LNA.
10
12
99
To make the designed LNA robust, the package topology should be selected to
replace the on-chip structure for the future work, which means the parasitic effects
caused by package should be included in the input matching network design [54].
Therefore the parasitic inductance of the input pin and corresponding bonding wires can
be absorbed into the component of L1 , while the parasitic values of power-supply pin
and bonding wires of package can be taken account into the shunt-peaked components of
LL and RL .
Fig. 4.18. Correlator in UWB receiver.
4.2
UWB Correlator Design
Comparing to the traditional narrow band receiver, the complexity of the UWB
receiver front-end has been greatly reduced. In a simplest topology, the receiver frontend is only composed of a wideband LNA, a wideband correlator, and a high frequency
analog-to-digital converter (ADC) [55]. The basic function of the correlator is to convert
the received RF signal from LNA to baseband for detection. The correlator normally
consists of a multiplier followed by an integrator, as shown in Fig. 4.18. The two inputs
100
to the correlator, or the multiplier, are the input monocycle pulse signal from LNA and
its template signal generated on the chip. The received monocycle pulse signal is
correlated with the local template monocycle pulse during a certain period, normally the
pulse repetition period or several pulse periods used for one symbol and its output is
sampled and held to detect whether there is a signal in the observing window.
In theory, the correlator can be implemented either in analog or digital format.
However, for digital format, although a correlator can be realized for high data rates of
up to 100 Mbps at high bandwidth, direct sampling of 3.1 − 10.6 GHz frequency signals
is ultimately required, which is almost impossible for current ADC techniques.
Furthermore, the digital correlator normally consumes more power and is lower in
efficiency when compared with its analog counterpart. Considering above factors,
analog correlator is the preferred choice.
For the analog correlator, the advantage is that it can process signals in real time
and provide a continuous output at low frequency, and thereby can remove the need for
special requirements for the ADC in the receiver [56]. Analog correlators are therefore
well suited for UWB front-end implementation, where the analog multiplier is required
to have a good linearity for low distortion.
As the correlator is used to detect the signal presence with known waveform in a
noisy background, the output will be zero for noise only condition [2]. For the correlated
input sigal, it is integrated with local template signal over the pulse duration and achieve
the certain output voltage. The cross-correlation function can be expressed as:
f =∫
t =t 0 +T
t =t0
RF (t ) LO (t )dt
(4.22)
where LO (t ) is the local template signal, RF (t ) is the input RF signal of the correlator,
and T is the integration period.
In UWB receiver design, the multiplier is required to have wide bandwidth up to
10.6 GHz, which assures the output waveform preserve the input pulse shape. This
brings the great challenge to the design of CMOS analog multipliers. Currently, most of
101
the published CMOS analog multipliers can only operating at low frequencies [57]-[60].
Although some works on UWB mixer design can achieve very broad bandwidth [61][62], the information of the time-domain performance is not provided, while this
specification is the important consideration in impulse-type UWB receiver design. In
this section, an ultra wideband four quadrant multiplier is introduced, which can be used
for the correlator of UWB receiver.
4.2.1 DC Analysis
The schematic of the proposed multiplier, which is based on the transconductor
multiplier structure proposed in [63], is shown in Fig. 4.19. The central component of
this four quadrant multiplier is CMOS programmable transconductors. As a currentmode element, it converts the input voltage signals into differential current to realize the
multiplication.
As shown in Fig. 4.1,9, the differential structure was selected, hence the even
order terms generated by the nonlinear components were cancelled, therefore enhance
the linearity of the multiplier. In order to reduce the leakage of the input RF signal to the
output, a pair of NMOS transistors M 9 and M 10 is inserted between the outputs of the
transconductor M 5 – M 8 and the multiplier output. To compensate the gain roll-off at
the high frequencies, the shunt-peaking topology was employed, just like the case in
UWB LNA design. Two inductors L1 and L2 with optimized values are added in series
with load resistors at the output (drain of M 9 and M 10 ), hence the gain performance at
the high-frequency end was improved and the wide bandwidth was achieved. Two
source-follower buffers were also included to facilitate the intermediate frequency (IF)
signal measurement.
102
Vdd
IF-
Vdd
Vdd
L1
M11
L2
R1
Vo
IF+
+
Io2
Io1
M10
M9
I1
I4
I2
Y+y
M5
X+x
M12
R2
-
Vb
Vdd
M1
M6
M2
I3
Y-y
M7
X-x
M8
M3
M4
X+x
Fig. 4.19. Schematic of the proposed multiplier.
As shown in Fig. 4.19, the RF signal x enters the lower branches formed by
transistors M 1 − M 4 , which operate in the linear region through the bias voltage of X.
While for the transistors M 5 − M 8 used for LO template signal y, operating in
saturation region was achieved when proper DC bias voltage Y was provided. Under the
condition of the triode region, the large signal model of the MOS transistor was applied
to M 1 − M 4 , and the corresponding current flowing through each of the lower branches,
I 1 to I 4 , can be expressed as [19], [64]
V ⎞
⎛
I i = K ⎜ X ± x − Vtn − dsi ⎟Vdsi
2 ⎠
⎝
(4.23)
103
where K = μ n C ox
W
, Vtn is the NMOS threshold voltage, and Vdsi is the drain-source
L
voltage of the i-th MOS transistor.
For the MOS transistor, the value of the transconductance g m is dependent on
the dc bias conditions. As g m of the transistor in the saturation region is much larger
than that of the transistor in the triode region, the upper transistors ( M 5 − M 8 ) operating
in the saturation region can be considered as the source followers. Therefore, for the
lower branch transistors M 1 − M 4 , the corresponding drain-source voltage Vdsi can be
expressed as [64]
Vdsi = Vds + y
(4.24)
Vdsj = Vds − y
(4.25)
for M 1 and M 2 , and
for M 3 and M 4 , respectively. Here Vds is the drain-source voltage of the transistor at
the bias point under the condition of x = y = 0. As shown in Fig. 4.19, the total output
current I o can be derived as [64]
I o = I o1 − I o 2 = (I 1 + I 3 ) − (I 2 + I 4 ) = (I 1 − I 2 ) + (I 3 − I 4 )
(4.26)
where
V +
⎛
I 1 = K ⎜ X + x − Vtn − ds
2
⎝
y⎞
⎟(Vds + y )
⎠
(4.27a)
104
V + y⎞
⎛
I 2 = K ⎜ X − x − Vtn − ds
⎟(Vds + y )
2 ⎠
⎝
(4.27b)
V − y⎞
⎛
I 3 = K ⎜ X − x − Vtn − ds
⎟(Vds − y )
2 ⎠
⎝
(4.27c)
V − y⎞
⎛
I 4 = K ⎜ X + x − Vtn − ds
⎟(Vds − y )
2 ⎠
⎝
(4.27d)
Hence the final output current is
I o = 2 Kx(Vds + y ) − 2 Kx(Vds − y ) = 4 Kxy
(4.28)
where we assumed all the size of the transistors ( M 1 − M 4 ) are equal, therefore K is
same to all transistors. Hence the multiplication function was achieved, and the
corresponding output voltage of the multiplier can be expressed as [64]
Vo = − I o Z o = −4 KxyZ o
(4.29)
where Z o is the output load between the + and – output.
4.2.2 AC Analysis
Fig. 4.20 presents the simplified small-signal equivalent circuit used for
bandwidth analysis. First, the transconductor ( M 1 to M 8 ) was assumed to be an ideal
current source with the parasitic capacitance of C at its output. Furthermore, to simplify
the circuit analysis, the output resistance is omitted because of its much larger value
compared with the impedance seen from the source of the cascoded transistors such as
M 9 and M 10 . In Fig. 4.20, the L and RL are the load inductor and load resistor (i.e., L1
105
and L2 , and R1 and R2 shown in Fig. 4.19), g m and rds are the transcondctance and
output resistance of M 9 or M 10 , and v gs is the gate-source voltage of transistor M 9 or
M 10 . As shown in Fig. 4.19, in order to improve the bandwidth, the shunt-peaking
topology was employed, where the output load resistance RL is in series with the
inductor L to compensate the gain roll-off at the high-frequency end. For the output,
under the condition of the open circuit, the parasitic capacitance at the output can be
ignored in the analysis because of its very small value. Typically, the drain node is the
dominant pole, because the equivalent resistance seen at the source node is low and
approximately 1 / g m . However, in our case, the parasitic capacitance associated with the
source node could be large, because three transistors are connected to the same node,
thus produce the dominant pole [64].
I
gm vgs
-
i
vgs
rds
C
Vo
L
RL
+
Fig. 4.20. Simplified small-signal equivalent circuit.
As shown in Fig. 4.20, the transfer function can be expressed as [64]
106
vo
RL + jωL
=
2
i
− ω CL jωC (RL + rds )
+
+1
1 + g m rds
1 + g m rds
(4.30)
Hence the dominant and non-dominant poles can be expressed as follows,
assuming that the two poles can be separated from each other [64],
ω p1 =
ω p2 =
1 + g m rds
(RL + rds )C
R L + rds
L
(4.31a)
(4.31b)
and the zero is ω z = R L / L . According to schematic simulation ω p1 is around 2.2 GHz,
while ω p 2 is much higher than ω p1 . Hence ω p1 is the dominant pole for this case. In
theory, under the condition that the dominant pole ω p1 can be cancelled by the zero ω z
[51], the bandwidth of multiplier will be increased dramatically, hence shunt-peaking
topology effectively improve the bandwidth performance [51].
4.2.3
Fabrication and Results
The proposed multiplier is fabricated with 0.18-µm CMOS process. The layout
structure was arranged symmetrically to reduce the potential unbalance caused by nonsymmetric structure. The octagonal-shape inductors L1 and L2 are optimized to achieve
the constant inductance over the frequency range from 3.1 to 10.6 GHz.
To calculate the frequency response, the RF and LO ports were fixed to DC, the
input signal was directly fed to the source node of M 9 and M 10 . First, the frequency
response of the multiplier without shunt-peaking inductor and load capacitance at the
output was investigated, with the result showing in Fig. 4.21. The 3-dB bandwidth in this
case is around 2 GHz. For comparison purpose, an additional 100-fF capacitance was
107
connected to the same source node of M 9 ( M 10 ), as shown in Fig. 4.19, and the
bandwidth reduced to about 1 GHz, as shown in Fig. 4.21, which validates the dominant
pole assumption. Fig. 4.22 compares the frequency response between the situations of
with output buffer and without output buffer when the shunt-peaking inductors are used.
It is obvious that after the inductor of around 30 nH is included, the bandwidth is
increased to 10 GHz, indicating that pole-zero cancellation topology really took into
effect. In the case where the buffer is included to the output of the multiplier, the
simulation result indicates that the bandwidth of multiplier is reduced to 7 GHz, because
of the extra capacitive loading from the buffer.
-10
No Load
100 fF Load
-15
Gain (dB)
-20
-25
-30
-35
-40
-45
-50 -2
10
10
-1
0
10
Frequency (GHz)
10
1
10
2
Fig. 4.21. Frequency response for dominant pole.
Fig. 4.23 shows the fabricated multiplier chip, with the size of 1 mm × 0.7 mm,
including the RF and dc bias pads for on-wafer measurement purpose. The on-wafer RF
108
probes were used on RF and LO ports, while the IF ports were measured through offchip with package.
-10
W ithout Buffer
W ith Buffer
-15
Gain (dB)
-20
-25
-30
-35
-40
-45
-50 -2
10
10
-1
0
10
Frequency (GHz)
10
1
Fig. 4.22. Frequency response for shunt-peaking inductor effect.
Fig. 4.23. Photograph of the fabricated multiplier.
10
2
109
The measured conversion gain and RF-port return loss were shown in Fig. 4.24,
where IF frequency was fixed to 10 MHz and LO power is -1 dBm. The conversion gain
is somewhat lower than the simulated one, and has the value of more than 7 dB over the
band of 3 to 10 GHz, including the output buffer effects. The difference between
measurement and simulated one is caused by parasitic resistant loss from shunt-peaking
inductor and buffer, also the parasitic capacitor from the buffer. For the RF-port return
loss, over the band of 3 to 10 GHz, RF-port return loss of 10 dB was achieved, and
reasonably matched the simulated result.
Fig. 4.24. Conversion gain and RF return loss with the IF frequency 10 MHz, LO
power is -1 dBm, and RF power is -20 dBm.
110
4.3
Receiver Front-end
The receiver front-end consists of the above-designed template tunable pulse
generator, LNA, and multiplier, which is shown in Fig. 4.25. To simulate the time
domain response, two monocycle pulses with same width of 0.2 ns, but different
amplitudes are used. The pulse with smaller amplitude is applied to RF input of
multiplier through LNA, while the larger pulse is fed to the LO port of multiplier from
the template tunable pulse generator. IF signal was generated at the output of the sourcefollower buffer. Fig. 4.26 shows the simulated IF signal in time-domain, where the
output of the multiplier depends on the polarity of the received RF signal. When the RF
pulse is in-phase with LO pulse, the output is positive, as shown in Fig. 4.26(a). When
the RF pulse is out-of-phase with LO pulse, the output is negative, which is shown in
Fig. 4.26(b). Expected output is obtained at the output of the multiplier, and shows that
the multiplier has sufficient bandwidth and is able to work with the sub-nano second
pulse inputs. Fig. 4.27 shows the layout of CMOS receiver front-end including the
components of template tunable pulse generator, UWB LNA, multiplier as well as RF
and dc pads, with the final size of 1.4 mm × 0.7 mm.
Multiplier
RF input
LNA
IF
LO
Oscillator
(PRF)
Template tunable
pulse generator
Fig. 4.25. Block diagram of the receiver front-end.
LO Input
RF Input
0.2
Input (V)
Input (V)
111
0
-0.2
0
-0.2
0.2
0.4
0.6
Time (ns)
0.8
-0.4
0
1
0.06
0.02
0.04
0
Output (V)
Output (V)
-0.4
0
0.02
0
-0.02
0
LO Input
RF Input
0.2
0.2
0.4
0.6
Time (ns)
0.8
1
0.2
0.4
0.6
Time (ns)
0.8
1
0.2
0.4
0.6
Time (ns)
0.8
1
-0.02
-0.04
-0.06
0
(a)
(b)
Fig. 4.26. Transient simulation of the receiver front-end. (a) RF and LO pulses are inphase, (b) RF and LO pulses are out-of-phase.
Fig. 4.27. Layout of the proposed receiver front-end.
112
CHAPTER V
UWB UNIPLANAR ANTENNA*
Unlike the narrow band systems, the antenna of the UWB system is a critical
element
for
pulse
signal
transmission.
Many
antennas,
especially
in
the
telecommunication applications, are resonant elements that are tuned to particular center
frequencies and have relatively narrow bandwidths. In contrast, UWB antenna designs
seek much broader bandwidths and require non-resonating operation. For the impulsetype UWB system, the antenna should be able to radiate and receive the short pulse
signal without undesirable distortion on the transmitting or receiving signal waveform.
To fulfill this requirement, the antenna input reflection should be minimized over the
entire UWB frequency band. Otherwise the multiple reflections between antenna and
transmitter/receiver will produce the clutter-like signals and degrade the system
performance.
There are several types of UWB antennas that can be used for short pulse
transmission, such as TEM horn, bow-tie, Vivaldi and conical antennas [13], [27], [65][69]. All of these UWB antennas can transmit and receive short pulse waveforms with
much less undesirable distortions. Among them TEM horn antenna and its variants are
used often in the impulse-type UWB systems. One of the variants developed in our
research group, named microstrip quasi-horn antenna or quasi-horn antenna, has been
successfully applied to the subsurface penetrating radars [14], [70]. The quasi-horn
antenna uses the non-uniform transmission line (NUTL) structure realized by microstripline structure. Therefore the input feeding structure of the quasi-horn is compatible with
the microstrip line, which makes the easy implementation of input feeding possible in
most designs without any special transition. The performance of the quasi-horn antenna
is similar to the TEM horn antenna, which has the advantage of high gain and linear
*
© 2006 IEEE. Parts of this chapter are reprinted, with permission, from Meng Miao and Cam Nguyen,
“On the development of an integrated CMOS-based UWB tunable-pulse transmit module,” IEEE
Transactions on Microwave Theory and Techniques, vol. 54, pp.3681-3687, October 2006.
113
phase characteristic. In addition, when used as the receiving antenna, the quasi-horn
antenna outputs a voltage waveform that is identical to the incident E field in time
domain, therefore is a preferred metrology receiving antenna for making a direct
measurement of transient EM fields [27]. Hence the quasi-horn antenna will be used as
receiving antenna in the following UWB antenna measurement to verify the performance
of the designed UWB antenna in time-domain when used as transmitting antenna.
For most commercial applications, however, the large size of the abovementioned UWB antennas makes them not feasible for portable or handheld uses. In this
chapter, a low-cost, compact, easy-to-manufacture coplanar UWB antenna was
developed that is omni-directional, radiation-efficient and has a stable UWB response,
which can be easily integrated with the designed tunable UWB CMOS RFIC chips.
The developed uniplanar UWB antenna can be considered as the planar variant
of the TEM horn antenna, which covers the entire UWB frequency range of 3.1 – 10.6
GHz. The design procedure also follows the design method of TEM horn antenna [71],
optimizing the antenna structure to achieve the minimum reflections over the operating
frequency range. The performance of the designed antenna was also investigated to
achieve the transmitted pulse signal with the small distortion in time domain.
5.1
Uniplanar UWB Antenna Design
In general, an antenna may be viewed as the non-uniform impedance
transformer, coupling the energy between the closed transmission system and an open
system or the free space around the antenna. Therefore, by varying the TEM
characteristic impedance Z 0 of the antenna smoothly, the minimum internal reflections
of the antenna input signal over the operating frequency range can be achieved.
To facilitate integration with the designed CMOS tunable monocycle pulse
generator chip, a compact UWB antenna with uniplanar structure is preferred.
Additionally, a “center-fed” uniplanar structure should be avoided due to the reason that
the feed region of this structure lies in the heart of the most intense near-fields
114
surrounding the antenna. Strong coupling between the feed structure and antenna
seriously affects the near field and distorts the antenna pattern [72].
y
X
Conductor
x
Substrate
Input Feed
Fig. 5.1. Basic structure of the uniplanar antenna.
To overcome potential problems caused by the unwanted coupling between
above-mentioned field from feed network and antenna and to meet the requirements for
UWB applications, such as ultra-wide bandwidth, reasonable efficiency, satisfactory
radiation properties, and linear phase characteristics, the proposed structure of the UWB
uniplanar antenna is shown in Fig. 5.1. It is the planar NUTL-based traveling-wave
antenna, fabricated on a Duroid substrate having 0.025-in thickness and relative
dielectric constant of 10.5. The operation of the antenna is based on the principles of
NUTLs [73] and well-known traveling-wave antennas. As this antenna can be
115
considered as the planar variant of the TEM horn antenna, the similar design topology is
applied to this planar structure.
As shown in Fig. 5.1, the edge feed is used to overcome the center feed
disadvantage. In the quasi-uniform section of coplanar waveguide (CPW), most of the
energy is confined within the transmission line until it reaches the antenna center, where
the energy is coupled from the CPW to the two parallel NUTL slot lines. Assume the
source and load impedances are to be matched at x = 0 and X, as shown in Fig. 5.1, we
have [71]
(dZ 0 / dx ) = 0
(5.1)
at the input section (x = 0) and the output section (x = X), where Z 0 is the characteristic
impedance of NUTL slot line along x direction.
For the given maximum allowable input reflection coefficient R(0) max , the
optimum characteristic impedance variations of the NUTL is [71]:
log Z 0 ( x) =
⎡Z (X )⎤ ⎛ x ⎞
1
1
log[Z 0 (0) Z 0 ( X )] + log ⎢ 0
⎥ G ⎜ B, ⎟
2
2
⎣ Z 0 ( 0) ⎦ ⎝ X ⎠
(5.2)
⎛ x⎞
where X is the length of NUTL slot line as shown in Fig. 5.1, G⎜ B, ⎟ and its
⎝ X⎠
parameter B are given in [74]. The maximum allowable input reflection coefficient is:
⎡ B
Z0 (X ) ⎤
(0.21723) log
R(0) max = tanh ⎢
⎥
Z 0 (0) ⎥⎦
⎢⎣ sinh B
(5.3)
116
For the given input reflection coefficient R(0) max , parameter B determines the
antenna length X. For the special case B = 0, the structure of antenna will be the
commonly used exponential taper.
As shown in Fig. 5.1, the antenna substrate is Duroid microwave board with h =
0.25 in and ε r = 10.5, and the input feeding of the antenna is the section of quasi-CPW
transmission line with 50-Ω characteristic impedance. At the antenna center, the energy
is coupled from the 50-Ω CPW to the two parallel slot lines. Based on the substrate
parameters, the characteristic impedance of the slot line at the antenna center was chosen
as 100-Ω to facilitate the antenna etching, as the characteristic impedance of the slot line
less than 100-Ω will result in too narrow slot width. On the other hand, the transition of
50-Ω CPW to two parallel 100-Ω slot lines should be as smooth as possible to minimize
the internal reflection. Hence the slot width of the slot line should be close to the gap
width of CPW. When designing 50-Ω CPW, another consideration is the package
specifications associated to the CMOS RFIC chip. In our case, standard 52-lead LQFP
open–package was selected to accommodate the CMOS chip, which has 13 leads along
each side, with the lead width of 12-mil and gap width between the leads of l4-mil [75].
To achieve the smooth transition from the signal and ground leads of the package
accommodating the designed CMOS chip to the path of quasi-uniform 50-Ω CPW feed
line, the parameters of quasi-CPW feed line are selected as shown in Table 5.1.
Table 5.1. Parameters of 50-Ω quasi-CPW feed line.
Z 0 (Ω)
Central metal width (mil)
Gap width (mil)
50
20
10
For the uniplanar UWB antenna design, the tapered slot lines are used to emulate
an impedance transformer from the source impedance Z 0 (0) = 100 Ω to the free space
117
impedance Z 0 ( X ) = 377 Ω over the UWB frequency range of 3.1 to 10.6 GHz.
Considering above parameters, and assuming the maximum allowable input reflection
coefficient R(0) max = 0.1, the design parameter B can be derived as 1.53 from (5.3).
Considering the lower frequency limit of 3.1 GHz, from (5.3), the antenna half-length is
selected as X = 600 mils.
The initial value of the characteristic impedance Z 0 of the tapered sections were
selected using (5.2) to produce the minimum internal reflections for the antenna input
signal over the UWB frequency range of 3.1 to 10.6 GHz. It should note that the initial
value of the terminating characteristic impedance at the open end of the antenna is
selected as the intrinsic impedance of free space, i.e. 377 Ω. Since this value only works
for spherical wave in free space, which is not the condition in our antenna design, this
value is probably not the optimum value for Z 0 ( X ) to achieve smooth transition at the
end of the antenna. Therefore 3D EM simulator Microwave Studio was used to perform
the time-domain EM simulation and to optimize the antenna structure to minimize
reflections occurring at the open-end transition.
Another issue concerning the variations of the characteristic impedance Z 0 of
NUTL slot lines is the implementation of the tapered slot line. As shown in Fig. 5.1, to
achieve the compact structure, the proposed antenna utilizes the smooth-changed
contours. This will help to avoid any abrupt transition in the shape across the entire
antenna structure to minimize the undesirable reflection. For the NUTL slot line
transition sections close to the antenna aperture center, the gap width is much smaller
compared to the associated metal widths, therefore conventional characteristic
impedance formula of the slot line can be used to derive the gap width for the relatively
smaller Z 0 . On the contrary, for the NUTL slot line transition sections close to the open
end of the antenna, the gap widths are kept on increasing, while the metal widths
dropped quickly, so the typical slot line calculation method cannot be applied to the
transition structure anymore, instead the EM simulator was used to derive the accurate
gap width for the specific metal widths and required Z 0 .
118
Based on above-mentioned initial conditions, the structure parameters of the
proposed antenna with the variable characteristic impedances are derived from (5.2).
Considering the abrupt variations of the slot edges around the open end of the antenna,
along the x-axis the coordinate points with non-uniform steps are applied to the antenna
structure, which is sparse around the antenna aperture center and condensed round the
open end to maintain the good variation accuracy. Through EM simulation with IE3D
[29], the final optimized characteristic impedance Z 0 ( x) , the slot-line gap width g (x) ,
and the metal width W (x) (along the y-direction) are presented in Table 5.2 for each
coordinate value along the x-axis.
Table 5.2. Dimensions of uniplanar antenna.
x (mil)
10
58.8
117.1
174.2
229.6
282.8
333.3
380.6
424.3
463.8
498.9
529.2
554.3
574.2
588.7
597.1
600
Z 0 ( x) (Ω)
100
101
103
107
113
123
139
151
165
178
193
208
226
240
251
257
260
g ( x) (mil)
W ( x) (mil)
30
32.4
37.2
52.8
78.6
108.2
145.6
190.2
242
313
392
477.8
565.6
654.8
748.4
839.8
930
750
747.4
740.6
725.7
702.9
675.5
641.6
601.8
556.1
498.8
435.7
367.5
297
224.7
149.3
74.5
0
To fully investigate the performance of the proposed UWB antenna structure,
time-domain simulator CST Microwave Studio [31] was selected, which bases on the
119
fact that the final integrated UWB system operates in the time-domain. Hence the
antenna simulation is highly facilitated because of the inherent time-domain feature of
Microwave Studio.
First, the return loss of the antenna structure shown in Fig. 5.1 is studied, and the
result in frequency-domain is presented in Fig. 5.2. The simulating result provides the
very good return loss for UWB antenna over the frequency range of 3 to 12 GHz, where
more than -15 dB return loss was achieved. The corresponding time-domain reflection
result was also presented in Fig. 5.3, where the Gaussian monocycle pulse with the 50%
pulse width of 50 ps was used as the excitation input signal. As shown in Fig. 5.3, the
small value of the reflected signal was generated, which validate the optimized antenna
structure.
0
-5
Return loss (dB)
-10
-15
-20
-25
-30
-35
-40
2
4
6
8
Frequency (GHz)
10
12
Fig. 5.2. Simulated return loss of the designed uniplanar antenna.
120
0.8
Input signal
Reflected signal
0.6
Amplitude (V)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0
0.5
1
Time (ns)
1.5
2
Fig. 5.3. Simulated input reflection of the designed antenna in time-domain.
Relative amplitude (dB)
0
-5
-10
-15
-20
2
4
6
8
Frequency (GHz)
10
Fig. 5.4. Simulated amplitude of transfer function.
12
121
The transfer function performance of the proposed antenna was also simulated
with CST Microwave Studio [31], at the position of 2-inch directly above the center of
antenna aperture surface. The simulated results were shown in Figs. 5.4 and 5.5. As
shown in Fig.5.4, the transfer function was normalized to make it more easily
understand, and the simulated normalized amplitude of antenna transfer function has the
band pass property, while the phase of the antenna transfer function indicates the good
linearity over the entire UWB band, as shown in Fig. 5.5. The good phase linearity of the
proposed antenna means the little distortion effect to the final pulse shape.
0
-500
-1000
Phase (degree)
-1500
-2000
-2500
-3000
-3500
-4000
-4500
2
4
6
8
Frequency (GHz)
10
12
Fig. 5.5. Simulated phase of transfer function.
Fig. 5.6 shows the simulated antenna gain for the designed antenna for the
coordinate shown in Fig. 5.1. These results indicate that the maximum antenna boresight
gain is normally 2.2 dBi at the frequency of 3.1 GHz.
122
90
5 dB
120
60
0
150
30
-5
90
3.1 GHz
6.8 GHz
10.6 GHz
150
-5
3.1 GHz
6.8 GHz
10.6 GHz
30
-10
180
0
210
330
180
0
210
300
330
240
270
300
270
(a)
90
5 dB
120
(b)
60
0
-5
150
60
0
-10
240
5 dB
120
3.1 GHz
6.8 GHz
10.6 GHz
30
-10
180
0
330
210
300
240
270
(c)
Fig. 5.6. Simulated antenna patterns. (a) E-plane (x-y plane), (b) E-plane (y-z plane),
and (c) H-plane patterns for the frequencies 3.1, 6.8, and 10.6 GHz.
5.2
Antenna Fabrication and Test
To facilitate the antenna performance measurement, the individual planar
antenna was first fabricated, which is shown in Fig. 5.7, including antenna aperture,
SMA fixture, and section of uniform CPW transmission line. The area occupied by the
antenna aperture is only 1.2 in × 1.5 in.
123
Fig. 5.7. Photograph of the developed UWB antenna along with 50-Ω CPW
feed line and SMA connector (on the left).
In the uniform section of CPW connecting to the SMA connector to the antenna,
most of the energy is confined within the transmission line until it reaches the antenna
center, where the energy is coupled from the CPW to the two parallel 100-Ω slot lines. It
should be particularly noted that for impulse UWB applications, as is considered here,
the time-domain performance of the antenna is much more critical than its frequency
counterpart. The antenna is used for transmitting or receiving UWB time-domain signals
(impulse or monocycle pulses as addressed here), not multiple discrete frequency
components in CP mode. Another word, the antenna transmits all frequency components
simultaneously, not consecutively. Although, from the Fourier series point of view, the
frequency and time domain are correlated, and one can then view them as equivalent,
they should be distinguished from one to another for UWB time-domain applications.
Fig. 5.8 shows the measured and simulated results of return loss in the frequency
domain. Measured result shows more than 12-dB return loss over the entire 3.1 − 10.6
GHz UWB frequency band. As this return loss includes all effects from the designed
124
antenna, CPW feed line, and SMA connector, it is difficult to derive the antenna’s actual
performance from the frequency-domain results.
Fig. 5.8. Measured and simulated return loss of uniplanar UWB antenna.
On the contrary, it is relatively very easy to distinguish the antenna performance
from other effects in the time domain. Furthermore, as the antenna is intended for
radiating impulse or monocycle pulses, as discussed earlier, it is imperative to
characterize it in time domain. Fig. 5.9 shows the measured and simulated time-domain
reflectometry (TDR) response results in time domain for a 50-ps input impulse signal. It
is clear that, from 0 to 0.5 ns, the response corresponds to effects of the SMA connector
and CPW feed line. The response after 0.5 ns is cased by the designed antenna aperture
125
and, as can be seen, the measured result matches very well with that simulated, which
confirms the antenna design.
Fig. 5.9. Measured and calculated TDR responses of uniplanar UWB antenna.
The TDR performance also demonstrates excellent time-domain behavior of the
designed antenna, which is crucial for UWB time-domain impulse applications. The
measured time-domain results indicate that better than 18-dB return loss is achieved for
the antenna. Good performance together with small size and uniplanar structure make
the designed antenna a very good candidate not only for UWB applications but also for
integration with printed-circuit UWB transmitters and receivers.
126
5.3
UWB Transmitter Module
Fig. 5.10 shows the photograph of the fabricated tunable UWB transmitter
module integrating the previously described CMOS tunable monocycle pulse generator
and UWB uniplanar antenna. The CMOS chip is mounted directly onto the edge of the
antenna without a feed line. The transmission line connecting the SMA connector and
the CMOS chip, used for feeding the external 10-MHz clock signal, and the bias lines
are etched onto the same board of the antenna. It is noted that the CMOS chip contains
other RFICs besides the pulse generator.
Fig. 5.10. Photograph of the fabricated UWB transmitter module.
Fig. 5.11 shows the block diagram of the test setup used for pulse transmission
measurement of the UWB transmitter module. The quasi-microstrip antenna operating
127
from 0.2 to more than 20 GHz is used as the receiving antenna since it can produce
faithfully the waveform of the received UWB signal. The UWB antenna of the
developed UWB transmitter module and the quasi-microstrip antenna face each other
and spaced 3-ft apart. The pulse received by the quasi-microstrip antenna is fed into a
power divider and displayed in a 50-GHz digitizing oscilloscope.
Fig. 5.11. Test setup for pulse transmission measurement of UWB transmitter module.
Fig. 5.12 shows the pulse signals received from the tunable impulse signals,
shown in [39], transmitted by the UWB transmit module. The pulse-duration tenability is
clearly visible in the received pulses. As can be seen, the received signals are monocycle
pulses with pulse duration tunable from 160 −350 ps. The resultant monocycle
waveform is due to the differential function of the designed antenna. The received pulses
maintain good symmetry with no serious distortion and ringing.
128
Fig. 5.12. Measured received signals of the impulses transmitted by UWB
transmitter module for different control voltages.
Fig. 5.13. Measured received signals of the monocycle pulses transmitted by
UWB transmitter module for different control voltages.
129
Fig. 5.13 shows the received pulse signal corresponding to the monocycle pulse
signals, shown in [39], transmitted by the UWB transmitter module. The received pulse
also has tunable durations. All the received signals have shape similar to the first
derivative of the monocycle pulses, as expected from the designed antenna. Both the
measured impulse and monocycle-pulse transmission results clearly demonstrate the
workability of the developed CMOS-based tunable UWB transmitter module.
130
CHAPTER VI
CONCLUSIONS
Through this research, the compact low-cost low-power UWB CMOS transmitter
and receiver front-ends based on impulse technology were developed, with the tunable
operating frequency band, and the front-end is further integrated with the developed
compact UWB coplanar antenna. The proposed UWB front-ends have the potential
application in short-range communication, GPR, and short-range detections.
First, the CMOS UWB pulse generator with frequency-band tuning capability
was developed, which can generate both impulse and monocycle pulse signals with
variable pulse durations. The pulse generator integrates a tuning delay circuit, a squarewave generator, an impulse-forming circuit, and a pulse-shaping circuit in a single chip.
It can produce 0.7 – 0.75 V peak-to-peak monocycle pulse with 140 – 350 ps tunable
pulse duration. Without the pulse-shaping circuitry, it can also generate 0.95 – 1.05 V
peak-to-peak Gaussian-type impulse signal with 100 – 300 ps tunable pulse duration.
Individual BPSK modulator was also designed, and further integrated with
tunable pulse generator to generate positive or negative pulse signal depending on the
“1” or “0” digital data information. The final pulse generator with integrated BPSK
modulator can generate positive impulse with 0.8 V, negative impulse with 0.7 V, as
well as the positive/negative monocycle pulse with 0.6 – 0.8 V, all with tunable pulse
durations.
For the receiver circuit, the cascoded common-source inductively degenerated
LNA, with extended ultra-wideband ladder matching network, was selected to form the
impulse-type UWB LNA. The shunt-peaking topology was also applied to the LNA
structure to further improve the performance at high-frequency end. The structureoptimized and PGS inductors were studied to replace the low-Q inductor model provided
in foundry library, hence further improve the LNA performance. The return losses of
LNA with source-follower buffer for both input port and output port are better than 10-
131
dB over the entire UWB band. The reverse isolation of LNA of -40 dB was also
achieved over the frequency range of 3.1 to 10.6 GHz. The maximum gain of 12.4 dB
was achieved over the band. For the 3-dB bandwidth, 2.6 – 9.8 GHz was achieved with
the help of shunt-peaking topology. The average NF of 5.8 dB is achieved over the entire
UWB band.
The UWB multiplier based on the transconductor multiplier structure was
investigated, with the central component of CMOS programmable transconductors. It
converts the input voltage signals into differential current to realize the multiplication.
The shunt-peaking topology was applied at the output, which achieve the pole-zero
cancellation and extend the multiplier bandwidth from 2 GHz to 10 GHz for un-load
situation, and 7 GHz for buffer-load condition. The UWB multiplier then integrates with
UWB LNA and template pulse generator to form the UWB receiver front-end, and the
output of the multiplier shows that the receiver front-end has sufficient bandwidth and is
able to work with the sub-nano second pulse inputs.
A low-cost, compact, easy-to-manufacture coplanar UWB antenna was
developed that is omni-directional, radiation-efficient and has a stable UWB response,
which can be easily integrated with the designed tunable UWB CMOS RFIC chips. The
developed uniplanar UWB antenna can be considered as the planar variant of the TEM
horn antenna, which covers the entire UWB frequency range of 3.1 – 10.6 GHz, with the
return loss better than 18-dB.
This novel uniplanar antenna further integrated with the previously developed
CMOS tunable pulse generator to form the UWB transmitter front-end module. This
UWB module can transmit the monocycle pulses with pulse duration tunable from 140
−350 ps with the impulse from the integrated pulse generator. The resultant monocycle
waveform is due to the differential function of the designed antenna. The received pulses
maintain good symmetry with no serious distortion and ringing. For monocycle pulse
from pulse generator, the transmitted signals have shape similar to the first derivative of
the monocycle pulses, as expected from the designed antenna. Both the impulse and
132
monocycle-pulse transmission results clearly demonstrate the workability of the
developed CMOS-based tunable UWB transmitter module.
The work of this research can be further investigated to improve the system
performance as well as robustness.
For the UWB transmitter front-end design, to reject the noise coupled through the
substrate due to common-mode rejection, the differential circuits will be a better choice.
It will achieve double balancing without the need for passive baluns or transformers.
Furthermore, both NOR and NAND gate blocks should be selected to replace CMOS
inverter at BPSK modulator input, to achieve the symmetric positive/negative
impulse/monocycle pulse in the BPSK-integrated tunable pulse generator. In addition,
the other type delay cell should be selected to achieve the broader linear tuning range vs.
tuning voltage variation. If possible, the package of the CMOS chip should be removed
to make the chip directly attach to the surface of the uniplanar UWB antenna. This will
reduce much of the parasitic effects. The techniques such as flip-chip or direct wirebonding are the potential options.
For the receiver front-end design, the single-ended LNA can be replaced with the
differential structure, in order to integrate easily with next stage differential-type UWB
multiplier. This will also make the circuit overcome the noise coupled through the
substrate due to common-mode rejection problems caused by single-ended circuit.
Furthermore, the package effects should be considered for the real case, where the
parasitic effects of the package should be absorbed into the input matching network as
well as the output matching network design.
133
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VITA
Meng Miao received the B.S. degree in physics from Nanjing University in 1991,
M.S. degree in electrical engineering from Nanjing Research Center of Electronics
Engineering in 1994, and M.Eng. degree in electrical engineering from National
University of Singapore in 2000.
From 1994 to 1998, he was with Nanjing Research Institute of Electronics
Technology, China, where he was involved with research and development of
microwave circuits, antennas and radomes. From 2000 to 2001, he worked as a research
engineer at MMIC lab, National University of Singapore, where he worked on GaAs
MMIC design and test. In May of 2008 he graduated with his Ph.D at Texas A&M
University. His current research interests include MIC/MMIC, CMOS RFICs, and
antenna design and test.
Dr. Miao may be contacted via Dr. Cam Nguyen, Texas A&M University,
Department of Electrical and Computer Engineering, College Station, TX 77843-3128.