Vol. 36, No. 12
Journal of Semiconductors
December 2015
Progress in complementary metal–oxide–semiconductor silicon photonics and
optoelectronic integrated circuits
Chen Hongda(陈弘达)1; Ž , Zhang Zan(张赞)1 , Huang Beiju(黄北举)1 , Mao Luhong(毛陆虹)2 ,
and Zhang Zanyun(张赞允)3
1 State
Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences,
Beijing 100083, China
2 Department of Electronics and Information Engineering, Tianjin University, Tianjin 300072, China
3 School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300387, China
Abstract: Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects.
Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this
paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated
circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected
to benefit several application domains, including communication, sensing, computing and nonlinear systems.
Key words: silicon photonics; silicon LED; grating coupler; silicon modulator; optoelectronic integrated circuits
DOI: 10.1088/1674-4926/36/12/121001
EEACC: 4270
1. Introduction
Copper-based electrical interconnects are widely used in
modern electrical systems and short-range communication
links, and show good performance at low speed. However,
traditional copper interconnects are facing difficulties such as
density, power dissipation, signal integrity and jitter as clock
speeds and wiring density increaseŒ1 5 . Optical interconnects
are proposed as an alternative solution to resolve the electrical
interconnect bottleneck and support high speed, low power dissipation and electromagnetic interference immune data communication.
Optical interconnects have potential benefits in interconnect density, energy and timing. Specifically, silicon-based
optical interconnects have received a lot of attention in recent yearsŒ6; 7 . The large refractive index contrast between silicon and cladding (SiO2 / enables silicon photonics devices
to become ultra-compact and suitable for large-scale, highdensity integration on-chip. Additionally, with the availability of complementary metal–oxide–semiconductor (CMOS)
foundries for silicon photonics fabrication, silicon photonics
show low cost and high integration capability with microelectronics compared to other materialŒ8; 9 . Silicon material is the
most promising candidate for monolithic integration of both
electronic and optic components on a single chip. All these advantages pave the way for realizing silicon-based low-cost and
large-scale integrated optoelectronic circuits, which will benefit communication networks, computing, sensing and nonlinear
systemsŒ10; 11 .
Pioneering and significant work has been done in the
field of silicon photonics. CMOS silicon light-emitting devices
(LEDs), silicon lasers, optical modulators, germanium (Ge)
photodetectors, silicon waveguide-based passive devices and
silicon photonic integration circuits have been demonstrated.
In this paper, we present an overview of the recent progress of
silicon photonics, and focus on our research contributions in
the field of silicon optoelectronic devices and optoelectronic
integrated circuits (OEICs). The paper is organized as follows:
the silicon LED and LED array fabricated by a standard CMOS
process without modification and post-process steps are discussed first in Section 2. In Section 3, we present a novel vertical grating coupler with large coupling tolerance. In Sections
4 and 5, we demonstrate the high-speed optical modulator and
photodetector. In Section 6, silicon photonic ICs and optoelectronic ICs are discussed. In Section 7, a conclusion and future
prospects are briefly given.
2. CMOS silicon light source
Silicon light sources are the main obstacle and a big challenge in silicon photonics integration circuits. Substantial efforts have been devoted to this field, utilizing technologies such
as porous SiŒ12 , Si superlattice structuresŒ13 , erbium impurity in siliconŒ14 and nano-precipitatesŒ15 . In 2005, the first
continuous-wave Raman silicon laser was demonstrated by Intel, which was a significant milestone in silicon-based lightemitting technologyŒ16 . But unfortunately, this approach utilizes nonstandard processing procedures and cannot be easily
* Project supported by the National Basic Research Program of China (No. 2011CBA00608), the National Natural Science Foundation
of China (Nos. 61178051, 61321063, 61335010, 61178048, 61275169), and the National High Technology Research and Development
Program of China (Nos. 2013AA013602, 2013AA031903, 2013AA032204).
† Corresponding author. Email: hdchen@semi.ac.cn
Received 11 September 2015
© 2015 Chinese Institute of Electronics
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Figure 1. (Color online) Demonstrated low-voltage Si-LED. (a) Cross-sectional view. (b) Microphotograph of the device. (c) Spectra with
increasing current. See Reference [24].
integrated into the present standard CMOS IC technology.
To integrate silicon light-emitting devices (Si-LEDs) into
mainstream silicon processes, researchers’ attention has been
mainly focused on light emission from the p–n junction in a
reverse-biased avalanche modeŒ17; 18 for many years. Remarkable works have been achieved in this area. Snyman et al., du
Plessis et al. and Morschbach et al. have demonstrated varied
reverse-biased Si-LEDs in standard CMOS technologyŒ19 21 .
An external quantum efficiency (EQE) of 5.8 10 6 was
achieved in 2005 using a wedge-shaped nC ppC junctionŒ22 .
To further improve the optical power, we proposed and demonstrated a wedge-shaped forward-biased pC –n Si-LED working
in carrier injection mode, which achieved an EQE of 8.3 10 6Œ23 . This is the highest EQE of forward-biased Si-LEDs
fabricated by the CMOS process.
The silicon LEDs mentioned above are based on avalanche
breakdown mode inducing high operating voltage, which is
not compatible with standard deep submicron CMOS technology. We demonstrated a low-voltage Si-LED fabricated with
0.35 m CMOS technology, as shown in Figure 1Œ24 . The device is working under Zener breakdown mode, thus the working voltage is reduced under 5 V which is compatible with a
0.35 m CMOS circuit power supply, while the power efficiency is improved. Comparing with a device working under
avalanche breakdown mode, the breakdown voltage is reduced
from 8.35 to 2.8 V and the EQE is increased from 7.6 10 8
to 2.06 10 8 .
To further investigate the electroluminescence phenomenon of Si-LED, a three-terminal device is proposed and
fabricated using standard 0.35 m CMOS technology, as
Figure 2. (a) Cross-sectional view of the three-terminal Si-LED. (b)
Electroluminescence spectra of the device in forward bias mode. (c)
Gate modulation effect on the output light intensity in the forward
mode. See Reference [25].
shown in Figure 2Œ25 . The device can emit light with a spectrum ranging from 500 to 1000 nm in reverse bias, and emit
light with a spectrum ranging from 900 to 1300 nm in forward
injection mode under a working voltage of 2 V. The EQEs of
the device under avalanche mode and forward injection mode
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Figure 3. (Color online) (a) Cross-sectional view of proposed SBD LED. (b) Optical micrograph of visible light emitting from SBD. (c) Electroluminescence emission spectra from SBD. See Reference [26].
Figure 4. (Color online) Micrograph of silicon LED display array displaying characters dynamically.
are 7.8 10 8 and 1.12 10 7 , respectively. Furthermore, the
modulation effect of gate voltage on the output light intensity is
clearly observed in forward injection mode, which implies that
this three-terminal device could work as a novel electro-optical
modulator.
We also proposed a new Si-LED based on the Schottky barrier diode (SBD) of the metal–semiconductor structure
and demonstrated the device through standard CMOS technologyŒ26 . The Schottky barrier is formed directly between the
metal and N-well in P-type silicon substrate. The device can
emit visible light with a wide flat emission spectrum under a
reverse breakdown voltage of 5.4 V as shown in Figure 3(b).
The demonstrated SBD LED shows the potential to utilize the
surface plasmon polariton resonance effect to enhance the light
emission rate by directly integrating a metal nanostructure into
the CMOS technology.
Since the silicon LED is fabricated by a standard CMOS
process, it has the advantage of monolithic integration with
the driver circuit. A novel display array composed of a p–n
junction LED and driver circuit is achieved using a standard
0.35 m CMOS process. The whole display array contains 16
16 cells with an LED and control circuit in each cell. The
control circuit comprises a 1-bit static random access memory,
high voltage switcher and switcher controller logic circuit. In
this way, each LED can be turned on and off independently and
set up to display characters, such as ‘China’, shown in Figure 4.
The result shows that by utilizing avalanche mode Si-LED, an
all-silicon digital display fabricated through standard CMOS
technology is achievable.
3. Light coupler
Although a silicon LED has been demonstrated, the properties of low optical power and broadband spectrum make it
difficult to realize a high-speed optical interconnect. An offchip laser is more feasible to provide a light source by fiber
coupling. Since the diameter of single-mode fiber is about
8 m while the size of a typical waveguide is only hundreds
of nanometers, the large size mismatch causes a big challenge
to couple light effectively from the fiber into the silicon waveguide.
Grating couplers are widely used to couple light from
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Figure 5. (Color online) (a) 3D schematic of the proposed bidirectional grating coupler. (b) Scanning electron microscope (SEM) image of the
grating region covered with silicon dioxide cladding. (c) Microscope photo of the fabricated device. (d) Electric intensity distribution of the
fiber incidence coupling at the peak coupling wavelength of 1557 nm. (e) Comparison between the simulated and measured coupling efficiency
of the bidirectional grating coupler. See Reference [32].
single-mode fiber to the silicon-on-insulator (SOI) photonic
chip due to their large alignment tolerance, wafer-scale testability and placement flexibility. To avoid large second-order
reflection, grating couplers are conventionally designed for interfacing with a tilted fiberŒ27 29 . The tilted fiber needs to be
carefully tuned and it is difficult to package except by using angle polishingŒ30 . To enable rapid wafer-scale testing and lowcost fiber packaging, a perfectly vertical coupling interface is
more advantageous. Grating reflectors and chirped gratings are
two possible solutions to vertical coupling by adding reflectors at one end of the grating or changing the grating periods intentionallyŒ31 . However, such methods need either additional deep etching steps or high-precision lithography, which
increase fabrication cost drastically and reduce fabrication tolerance. In our later research, a bidirectional grating coupler
for perfectly vertical coupling was proposed and demonstrated,
with high coupling efficiency and flat-top filtering characteristicsŒ32 .
The key component of the device is a uniform grating designed for perfectly vertical coupling. Unlike traditional grating couplers, both ends of the grating are connected to a tapered
waveguide mode converter. Therefore, the light can be coupled
and split into two directions for low-loss transmission. At the
output end, an optical combiner is utilized to collect the optical power of two waveguide arms. Because of the bidirectional
transmission behavior, this coupler shows strong misalignment
tolerance along the waveguide direction. As depicted in Figure 5(e), the simulation and measurement results show good
agreement in the curve trend. The measured peak efficiency
reaches 46% and the coupling efficiency curves at LP D 0 m
and LP D 1 m almost overlap, which verifies the strong misalignment tolerance of the coupler experimentally.
4. Silicon modulator
As a key building block of future silicon photonic interconnect systems, silicon optical modulators have attracted great attention over the past few yearsŒ33; 34 . Current high-speed silicon modulators are mostly based on a Mach–Zehnder interferometer (MZI) structure with a modulation mechanism of
free carrier dispersion effectŒ35; 36 . With a fast carrier depletion mechanism and traveling wave electrode design, a highspeed operation of over 40 Gb/s was achievedŒ37; 38 . To fur-
Figure 6. (Color online) Microscope photo of (a) the bidirectional
grating-based optical modulator, (b) tip coupler, (c) TiN terminator,
(d) multi-mode inferometer combiner and (e) bidirectional grating interface. See Reference [46].
ther improve the performance, several impressive works have
been performed to optimize the phase shifter, including diode
configurationŒ39; 40 , doping profileŒ41; 42 and traveling wave
electrode designŒ43 .
Although the performance of the devices has been greatly
promoted, the commercial application of silicon waveguide
modulators still faces many obstacles. One of the biggest challenges is the small misalignment tolerance which causes a
high packaging cost for optical coupling. Edge coupling is a
convenient method for silicon modulatorsŒ44; 45 , but it suffers from submicron misalignment tolerance and involves additional processes such as edge polishing. As for the traditional
grating coupler, although it shows medium misalignment tolerance, it is designed for tilted fiber coupling which needs angle
tuning and fiber polishing.
To achieve large misalignment tolerance and low-cost
fiber packaging of silicon modulators, we proposed and
demonstrated an optical modulator based on bidirectional grating with a large misalignment toleranceŒ46 . Figure 6 shows the
microscope photos of the device. As can be seen, the bidirectional grating (which acts as both a coupler and optical splitter) and the multi-mode interferometer (MMI) combiner build
up an MZI configuration. By introducing p–n phase shifters
to the two arms of the unbalanced MZI structure, a modulator
is built up as shown in Figure 6(a). The calculated and mea-
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Figure 7. (Color online) (a) Calculated normalized optical transmission of the modulator with different fiber positions. (b) Measured fiber to
fiber normalized optical transmission of the modulator with different fiber positions. See Reference [46].
When the misalignment increases to ˙2 m, the ERs fall to
5.1 dB and 6.27 dB, respectively. This modulator with characteristics of large misalignment tolerance is believed to provide
a promising solution for low-cost photonic packaging of modulators and photonic interconnects.
5. Ge photodetector
Figure 8. (Color online) Eye diagrams for fiber positions (a)–(e) varying in the x-direction with an unchanged y-coordinate of 0. (f)–(j) are
varying in the y-direction with an unchanged x-coordinate of 0. See
Reference [46].
sured normalized optical transmission spectra are depicted in
Figures 7(a) and 7(b). Due to the particular characteristics of
the bidirectional grating, the insertion loss and notch depth near
the resonant wavelength are quite robust to fiber misalignment.
This means the modulator is misalignment-tolerant near the
resonant wavelength, which is also the strong coupling wavelength of the grating.
Figure 8 shows the eye diagrams for different fiber positions. Along the waveguide direction (x-direction), the eye diagrams show strong misalignment tolerance as expected. With
fiber misalignment of ˙1 m and ˙2 m, the extinction ratio (ER) deterioration is only about 0.2 dB and 1.6 dB respectively. For comparison, the misalignment tolerance along the
grating direction (y-direction) was also investigated. Within a
misalignment of ˙1 m, the ER decreases by only 0.3 dB.
Ge photodetectors with high speed and high responsivity
have been proposedŒ47 49 . By embedding a p–i–n or metal–
semiconductor–metal (MSM) electrical configuration, most of
the devices can reach a bandwidth of several tens of GHz and
a responsivity near 1 A/WŒ49; 50 . A Ge waveguide photodetector (WGPD) can be integrated with other silicon waveguide
devices by evanescent coupling or butt couplingŒ48; 49 . As the
light absorption is perpendicular to the direction of electric current collection in WGPDs, the trade-off between quantum efficiency and bandwidth no longer exists. Figure 9 shows these
high performance Ge photodetectors with different structures.
Here we give a brief introduction of our preliminary results with a Ge WGPD. As shown in Figure 10, the device is
designed to be an evanescently coupled photodetector with interleaved lateral p–i–n configurations. The Ge waveguide is
500 nm thick with a footprint of 9 25 m2 . A silicon taper waveguide is employed as a mode converter to reduce the
reflection at the detector interface. For the p–i–n diode, the
pC /nC doping concentration is about 1019 cm 3 , and the width
of intrinsic Ge (i-Ge) is designed to be 1.5 m.
The WGPD is characterized both in dark current and responsivity. We measured the I –V curve of the device within
the voltage range of –3 to 1 V, as shown in Figure 11(a). The
dark currents at –1 V and –3 V were 254 nA and 1.35 A,
respectively. Considering the active area of the device, the
corresponding dark current densities were 113 mA/cm2 and
601 mA/cm2 , respectively. Figure 11(b) shows the measured
responsivity over the wavelength range from 1528 to 1580 nm
with a reverse bias of 1 and 3 V, respectively. A flat responsivity was obtained for the wavelength range out to 1565 nm,
which corresponds to the absorption edge of Ge grown on Si
with tensile-strain-induced bandgap narrowingŒ51 . The mean
values of the flat responsivity range reach as high as 1.21 A/W
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Figure 9. (Color online) Various types of germanium waveguide photodetectors. (a) Vertical coupling with lateral p–i–n configuration. (b) Butt
coupling with lateral p–i–n configuration. (c) Vertical coupling with vertical p–i–n configuration. See Reference [50].
Figure 10. (Color online) (a) Schematic layout of the germanium waveguide photodetector. (b) Cross-sectional view of the detector waveguide
configuration. See Reference [59].
Figure 11. Characteristics of the WGPD. (a) I –V curve of the WGPD. (b) Responsivity of the WGPD under different reverse bias voltages.
See Reference [59].
at –3 V bias, corresponding to a quantum efficiency of 97%.
Such high responsivity implies that the WGPD we designed
achieves full optical absorption in a Ge active layer.
6. Optoelectronic ICs
6.1. Monolithic integration
Monolithic integration has the advantage of fabricating
photonic devices and ICs by the same CMOS process, which
will merge photonics and electronics seamlessly. It utilizes
electronic and photonic devices together in a synergistic way to
achieve better performance than those based on a pure photonic
or electronic device. It can also provide better process control
at low cost, and reduce the parasitic parameters induced by the
packaging of discrete devices.
Several impressive works have been reported. Luxtera
CompanyŒ52; 53 reported an integrated four-channel parallel
optical transceiver built using a modified CMOS photonics
process, operating at 28 Gb/s per channel. The chip contains
all functionalities needed for an optical transceiver: transmitter
and receiver optics, electrical driver, receiver and control circuits. The transceiver is monolithically integrated; only light
sources are external to the chip. This is the world’s first mono-
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Figure 12. (Color online) Micrographs of fabricated monolithically
integrated transceiver chip. See Reference [53].
Figure 14. (Color online) (a) Schematic layout of the integrated photonic interconnect. (b) Cross-section diagram of the photonic components. See Reference [59].
Figure 13. (Color online) Microphotograph of a CMOS die showing
monolithically integrated CMOS and nanophotonics circuitry. (a) Optical image of transmitter (TX) consisting of CMOS driver circuitry
integrated with a ring modulator. (b) Optical image of the receiver
(RX) consisting of CMOS amplifiers integrated with a Ge waveguide
photodetector. See Reference [55].
lithically integrated transceiver chip beyond 100 Gb/s using silicon technology. Figure 12 shows a top view of the chip.
IBM has also developed a CMOS process that offers solutions to the close integration of electrical and optical functions in one technology platform. Combining optical devices
with CMOS electrical functions, dense electro-optical integration is achieved at chip-levelŒ54; 55 , as shown in Figure 13. Different optical and electrical blocks such as filters, modulators,
detectors, driver and receiver circuits are monolithically integratedŒ56 . The modulator and Ge photodetector show a –3 dB
cutoff frequency of 20 GHz and 40 GHz, respectivelyŒ55 . After
incorporation of CMOS ICs and photonics circuits, the transmitter and receiver exhibit an open eye diagram at 5 Gb/s.
MIT has developed a monolithically integrated optical receiver using a standard 45 nm SOI process with a power consumption of 52 fJ/bitŒ57 which meets the low power dissipation
requirement of optical interconnectsŒ5 . Oracle demonstrated a
fully integrated silicon photonic transceiver in a 130 nm CMOS
SOI process by using photonic microring resonator modulators. The transmitter and receiver are demonstrated to achieve
data rates of 25 Gb/s with a bit error rate of 10 12Œ58 . This is
the first monolithic silicon photonic transceiver demonstrated
in a CMOS SOI process with photonic ring modulators.
We also developed a photonic integration circuit based
on SOI substrate. We proposed and demonstrated a point-topoint on-chip optical interconnect by connecting a bidirectional
grating-based E–O modulator with a Ge WGPD, as Figure
14(a) shows. Figure 14(b) shows the cross-section diagrams of
all the photonic components with critical dimensions labeled,
such as the grating coupler, rib waveguide, modulator and Ge
WGPD.
The entire chip is fabricated on a 200 mm SOI wafer, using CMOS-compatible technology. Figure 15 shows the microscope photo of the integrated photonic link and the SEM
images of various components. The eye diagrams at 3 Gb/s
and 4 Gb/s of on-chip interconnects at different wavelengths of
1545 nm, 1548 nm and 1551 nm are achieved, which implies
that this photonic link has a broad working wavelength range.
Details of the design and fabrication of the modulator and Ge
WGPD can be found in our previous workŒ59; 60 . The demonstrated photonic interconnect shows great potential to serve as
a low-cost building block for developing scalable optical interconnection architectures in the next-generation on-chip optical
networks.
The monolithic integration approaches discussed above
are based on SOI substrate. But the state-of-the-art CMOS
technology is based on bulk silicon substrate or SOI substrate
with a thin buried oxide layer (thinner than 400 nm), which is
not sufficient to provide optical confinement of the waveguide
mode. A thicker buried oxide layer of more than 1 m must be
used to realize perfect optical confinement. Unfortunately, a
thicker buried oxide layer will induce short channel effectsŒ61
and thermal problemsŒ62 in the transistor, which results in per-
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Figure 15. (Color online) (a) Microscope photo of the integrated photonic interconnect. (b) SEM top images of the integrated germanium
waveguide photodetector. (c) Top view of the optical interface. (d) The gratings with silicon dioxide cladding layer. (e) The cross-sectional view
of the phase shifter with ground–signal–ground electrode pattern. (f) Zoomed cross-sectional view of the rib waveguide embedded in the phase
shifter. See Reference [59].
Figure 16. The cross-section of optoelectronic ICs. See Reference [63].
formance degradation of ICs. Hence, it is of great importance
to develop monolithic integration of electronics and photonics
using standard CMOS bulk silicon substrates.
In order to realize OEICs on bulk silicon substrate,
we designed silicon LEDs, a photodetector, waveguides and
driver/receiver circuits, and monolithically integrated them using a standard CMOS process without modification or postprocess stepsŒ63 . The cross-section of the monolithic OEIC is
shown in Figure 16. The light emitting from the LED transmits
through the silicon oxide waveguide to the photodiode region.
The waveguide used here is not the same as the traditional SOI
waveguide whose cladding refractive index is smaller than the
core. The SOI channel waveguide can achieve relatively high
transmission efficiency, but it cannot be fabricated by a standard bulk silicon CMOS process. Silicon dioxide and copper in
the standard CMOS process are employed as a core layer and a
cladding layer of the waveguide, respectively. The waveguide
structure shown in Figure 16 is constructed by four layers of
copper interconnection. The first and fourth metal layers are
used as bottom and top cladding layers. The second metal layer,
the third metal layer and the contacts between the different
metal layers define the lateral cladding. We also designed the
receiver circuit to handle the weak photocurrent of the photodetector. By monolithic integration of these photonic devices and
electrical circuits, on-chip optical interconnection is realized.
A microscope photo of the OEIC chip is shown in Figure 17. All of these optical components are covered by the
fourth metal layer. Test results show that the output of receiver
circuits depends directly on the illumination power, which is
proportional to the reverse bias current of the LED. It means
that on-chip optical interconnects in standard CMOS technol-
Figure 17. (Color online) Microphotograph of OEIC for on-chip interconnect. See Reference [63].
ogy are preliminarily realized by standard bulk CMOS processes without any modification or post-processing. To the best
of our knowledge, this is the first monolithic OEIC for on-chip
optical interconnection based on standard CMOS technology.
It is a promising way to provide a low-cost and high-yield solution for on-chip optical interconnects.
6.2. Hybrid integration
Since the widely used substrate of silicon photonics is SOI,
which differs from CMOS technology, monolithic integration
of electronics and photonics requires moderate process modification that needs close cooperation between microelectronics
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Figure 18. Top view of die to wafer assembly of electronic IC over
photonic IC. See Reference [65].
and optoelectronics. Process development also consumes a lot
of time and cost, which are not compatible with the time scale
of CMOS technology evolution. The compromised method is
to separate electronics from photonics while keeping a very
compact system size though the use of advanced packaging
technology such as 3D through-silicon-via integration and flipchip bonding.
STMicroelectronics developed hybrid integration of electronic and photonic ICs by 3D face-to-face integration (Figure
18) that were realized through a dense and reliable array of fine
pitch -Cu pillarsŒ64 . The substrate of electronic IC is bulk silicon and the substrate of photonics IC is SOI featuring 310 nm
silicon thickness with a buried oxide thickness of 720 nm. Both
1310 nm and 1490 nm photonic devices are supported in this
process. A hybrid integration optical transmitter and receiver
are demonstrated with a data rate of 25–28 Gb/sŒ65 .
IMEC reported a thermally controlled ring-based flipchip integrated CMOS Si-photonic transceiver with four channels operating at 20 Gb/sŒ66 . The CMOS chip is fabricated
by a 40 nm low-power CMOS process and the Si-photonic
chip is fabricated in the IMEC 200 mm pilot line using a
0.13 m CMOS processing moduleŒ67 . The flip-chip integrated transceiver is achieved on a printed circuit board (PCB)
with attached fiber array, as shown in Figure 19.
6.3. Post-CMOS integration
The post-CMOS integration approach is also called backend integration, and introduces new steps into the backend of
the CMOS process to manufacture photonic devicesŒ68 72 .
Employing an electro-optic polymer and silicon nitride waveguide, 40 Gb/s data rates have been demonstrated (Figure 20),
which could be integrated into the CMOS backend as discussed in Reference [72]. Although the additional process steps
will potentially increase the cost, the fabrication can be done
as a post-process on existing electronic designs and no modification will be made to the critical frontend steps of the
CMOS process. Moreover, with its inherent multi-layer characteristics, 3D integration of photonics and electronics could
be achieved through the backend approach, leading to high integration density and low costs.
Based on the backend integration approach, we proposed
a post-process flow to integrate the photonic layer into the
CMOS IC and through which we have experimentally demon-
Figure 19. (Color online) Si-photonics and CMOS chip pictures. (a)
130 nm SOI silicon photonic transceiver chip. (b) CMOS 40 nm lowpower transceiver chip. (c) Flip-chip integrated optical transceiver
demonstrator with attached fiber array, glued and wire-bonded to a
PCB. See Reference [66].
Figure 20. (Color online) Optical link based on electro-optic polymer
and silicon nitride waveguide. See Reference [72].
strated monolithic integration of tunable Si3 N4 microring filters with CMOS control circuits. The proposed integration approach adds a photonic layer on the CMOS ICs using a postprocess after the CMOS backend steps, as depicted in Figure 21. The IC die acts as a substrate of the whole chip. The
SiO2 layer, with a typical thickness of a few microns, provides
sufficient optical isolation. The photonic layer contains silicon
photonic devices with an additional dielectric layer on top to
protect the devices. Since the photonic layer is directly fabricated on the top surface of the CMOS backend, the fabrication
process needs to satisfy a strict thermal limit of 450 ıC to avoid
performance degradation of CMOS ICsŒ73 .
The 3D schematic of our post-CMOS integration chip is
shown in Figure 22(a). Si3 N4 microring filters are integrated
on the CMOS IC die manufactured on the CSMC 1 m CMOS
lineŒ74 . Micro-heaters and control circuits in IC die are used to
tune the resonance of filters, as depicted in Figure 22(b).
Microscope photos of the IC die before and after photonic
layer fabrication are shown in Figure 23. Above the circuits,
Si3 N4 microring filters can be clearly seen in Figure 23(b).
Cross-section images of the chip are shown in Figures 23(c)
and 23(d). The Si3 N4 waveguide and metal interconnects of
the ICs beneath the photonic layer are clearly shown in the images.
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Figure 21. (Color online) Cross-sectional schematic diagram illustrating backend integration of photonic devices and electronic circuits.
Figure 23. (Color online) Microscope photo of the CSMC commercial 1 m CMOS IC die (a) before and (b) after photonic layer fabrication. (c), (d) SEM images of the cross-section of CMOS IC die
with deposited SiO2 and Si3 N4 . (e) Normalized response spectra of
the Si3 N4 microring filter with different voltage applied on Vdd pin.
See Reference [74].
Figure 22. (Color online) (a) Structure and (b) schematic diagram of
the backend monolithic integrated Si3 N4 filter. See Reference [74].
Test results show that the resonance wavelength of Si3 N4
microring filters can be tuned by the control circuit on-chip.
Thanks to the control circuit and micro-heater on-chip, the
Si3 N4 microring filters show wide temperature tolerance,
which is the key to the commercial application of microringbased devices. To the best of our knowledge, this is the first experimental demonstration of monolithic integration of a Si3 N4
microring filter with bulk CMOS ICs utilizing a post-process.
The result shows that the post-CMOS integration approach for
integrating photonic layers on the backend of CMOS electronics provides a new way to realize integration of photonics and
electronics, and overcomes the obstacle previously caused by
the different substrates of photonic and electronic devices.
7. Summary and future prospects
In this paper, we reviewed the recent advances in siliconbased passive and active optical interconnect components. Recent progress and our research results on a silicon light source,
grating coupler, optical modulator, Ge photodetector and silicon OEICs are provided. Monolithic and hybrid silicon OEICs are demonstrated with high speeds of more than 25 Gb/s.
Specifically, these silicon photonic ICs show good performance and have potential for low-cost and high-volume production.
One of the biggest advantages of silicon photonics is its
compatibility with conventional electronic CMOS foundries.
The photonics and electronics will be merged seamlessly by
the CMOS process, and achieve better performance than those
based on pure photonic or electronic devices. The progress
made by intensive academic and industrial research on silicon
photonics utilizing a mature existing CMOS process paves the
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way for realizing extremely low cost and large scale siliconbased OEICs, which will benefit communication, sensing,
computing and nonlinear systems in the near future. To complete this step, several issues remain to be addressed:
(1) Optoelectronic integration. As the performance of discrete devices keeps developing, the optoelectronic integration
method becomes the main obstacle to optoelectronic convergence. As discussed above, frontend integration, backend integration and hybrid integration are the three main solutions,
and many achievements have been made so far. However, none
of them achieves a solution without a compromise of the performance between electronics and photonics. Therefore, several new technologies are emerging, such as plasmonic-based
technology, Si-organic technology and Si-graphene technology, which will positively impact CMOS silicon photonics.
(2) Packaging. To develop mature products of silicon photonics, new packaging challenges are emerging when dealing with optical coupling and thermal cooling. Optical fiber
is still the most appropriate medium to transmit optical data,
especially when external light source configuration is employed. Characteristics such as good thermal resistance, lowprofile geometry, compatibility with high-speed data rates and
high-efficiency optical coupling should be taken into account.
Therefore, advanced packaging technologies are desired to
achieve low-cost mass-production assembly processes. Entrepreneurs know this very well and have devoted much effort in this area in recent years. For example, utilizing accurate mechanical guiding structures, IBM is developing a selfaligned fiber packaging technology to realize passive alignment of fiber arrays with high coupling efficiencyŒ75 .
(3) Device modeling. Driven by economical concerns, the
move to fabless design company mode becomes more and
more obvious, and will benefit from existing CMOS foundries
for fabrication. For silicon photonics to be competitive within
this mode, standardization of the integration platform is urgently required. Therefore, the modeling of basic building
blocks of CMOS silicon photonics both in optics and electronics based on the fabrication platform is a fundamental work to
produce silicon photonic devices in large volumes with a high
yield.
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