Signal
Technologies
1
Gunning Transceiver Logic (GTL)
- evolution
¾ Evolved from BTL, the backplane transceiver logic, which in
turn evolved from ECL (emitter-coupled logic)
¾ Setup of an open collector bus system using BTL devices
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•
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A reduced voltage swing
An open collector output stage
The falling signal edge is actively generated by the driver and rising
edge is generated by the passive pull-up network
The resistor R in the passive pull-up network is matched to the
resistance of the loaded backplane
2
Gunning Transceiver Logic
¾ Open collector bus system using GTL devices
¾ GTL has a fast edge rate and reduced voltage output levels from BTL
¾ The GTL driver has an open collector output, but the diode in the open
collector output that is found in BTL is not present in GTL
¾ The receiver as with BTL is designed as a differential amplifier,
guaranteeing stable threshold voltages at the receiver
¾ A pull-up resistor R at the line end is matched to the loaded trace
impedance to avoid line reflections
3
Gunning Transceiver Logic Plus (GTLP)
¾ High-speed, high-performance backplane transceivers
¾ Operate like the GTL family except for two major differences:
• Optimized with slower edge rates for the distributed loads found in
multi-slot backplanes,
• Supports live insertion applications with internal pre-charge circuitry
to PCB
Simplified partial schematic of a typical GTLP devices
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•
to backplane
GTLP is commonly designed with two ports, an LVTTL/TTL I/O
which is referred to as the A Port or a GTLP I/O which is referred to as
the B Port
Both ports are bidirectional
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GTLP Device Features (1)
¾ Controlled edge rates
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Incorporates output edge control (OEC) circuitry to address the
output switching noise problem with high-speed devices
Edge control incorporates wave-shaping techniques that optimize
GTLP devices for driving backplanes
Control the output level transition to minimize switching noise and
EM interface and reduce signal-settling time
¾ GTLP transition waveform
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The area of the output transition are addressed by the GTLP output
control circuitry
The ability to vary rise and fall times allows adjusting for various far-5
end loads
GTLP Device Features (2)
¾ Bushold (A port)
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•
Designed to tolerate floating input conditions
hold an undriven data-bus line in a valid logic state
¾ Simplified schematic diagram of bushold circuitry
• Uses a low drive inverters in the device input
stage that provides feedback to the input of the
device and the bus
• When the signal driving the input is removed,
the inverter will maintain the last received valid
signal level on the device input and bus line until
it is overdriven by the next incoming signal
¾ Voltage-in versus current-in sweep of bushold device
• II(HOLD) is the bushold input minimum drive.
This is the minimum amount of current the circuit
is capable of supplying
• II(OD) is the bushold input over-drive current to
change state. This is the minimum amount of
current that is necessary to overcome the bushold
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circuit and cause the input to change states
GTLP Backplane Design Considerations
¾ Termination resistor should match the backplane impedance for best
signal integrity
¾ The impedance is a function of natural trace impedance (Z0), stub
length, connector impedance, device impedance, and card spacing
¾ Closer spacing reduces the effective impedance and requires a smaller
termination resistor
¾ RT vs. slot spacing with GTLP ¾ waveform with matched vs. overmedium and high drive devices
matched and under-matched termination
!
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GTLP Backplane
¾
Typical GTLP backplane
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The bus is pulled high to the termination voltage (VTT=1.5V) through the
termination resistance (RTT=22 Ohm) when the GTLP driver’s open drain
output stage is off and pulled low when GTLP driver’s open drain output
stage is on
The advantage of the open drain backplane is that there is no bus contention,
it is simple to implement and there is less power consumption
8
Low Voltage
Differential
Signalling (LVDS)
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Introduction
¾ LVDS allows data transmission at hundreds and even
thousands of megabits per second
¾ Its low swing and its current-mode driver outputs create
low noise and provide low power consumption across
large range of data rates
¾ LVDS drivers can transmit signal over long traces
¾ LVDS devices usually require controlled-impedance
circuit-board traces, connectors, and cables to maintain
signal integrity
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Scope of LVDS Applications
• The high-speed and low power/noise/cost benefits of LVDS
broaden the scope of LVDS applications far beyond those for
traditional technologies. The following table provides some
examples of LVDS applications.
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LVDS Principle of Operation (1)
¾ Simplified diagram of an LVDS driver and receiver connected via 100Ohm
differential impedance medium
Current source boosts PSRR
(a)
Current flowing from
the driver’s true output
down through the
100Ohm termination
resistor;
(b) Current flowing from
the driver’s inverted
output up through the
100Ohm termination
resistor
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LVDS Principle of Operation (2)
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•
•
LVDS outputs consist of a current source (nominal
3.5mA) which drives a differential trace or line. The
basic receiver has high dc input impedance, so the
majority of the driver current flows across the 100 Ohm
termination resistor, generating about 350mV across the
resistor and receiver input
When the driver switches, it changes the direction of
current flow across the resistor, thereby creating a valid
“one” or zero” logic state
Commutation of a single_current_source current to
make it flow in both directions gives LVDS power
advantage
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LVDS Principle of Operation (3)
¾ Voltages generated across the LVDS terminating resistor assuming no losses
or distortion over the interconnect between the driver and terminating resistor
at the receiver
VOD: differential output voltage
VOL/VOH: “single-ended” voltages because they
are measured with respect to ground
VOS: halfway between VOL and VOH
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LVDS Principle of Operation (4)
¾ Single-ended and differential LVDS waveforms generated when switching
from high to low and back to high.
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LVDS Principle of Operation (5)
¾ LVDS receivers can tolerate +/- 1V of common-mode voltage difference
between the driver and receiver
¾ This is useful in situations where there might be up to 1V of difference
between the drivers’ ground and receiver’s ground due to resistive voltage drops
over long backplane or cable distances, or due to ground potential variations from
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one chassis to another
LVDS Configurations (1)
¾ Point-to-point configuration. This provides the best signal quality due to the
clear path.
¾ Bidirectional half-duplex configuration allows bidirectional communication
over a single twisted pair. Data can flow in only one direction at a time.
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LVDS Configurations (2)
¾ Multi-drop configuration connects multiple receivers to a driver. This
configuration is useful in data distribution applications. In this
configuration, stub lengths must be as short as possible, although
acceptable stub lengths are always dependent upon the application.
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LVDS Summary
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LVDS Summary (continued)
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High-Speed Transceiver
Logic (HSTL)
Stub-Series Terminated
Logic (SSTL)
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Introduction
¾ HSTL and SSTL families are used primarily for
¾ Memory chip interfaces
¾ Parallel data in/out interfaces for SerDes devices
¾ Single ended or differential interfaces that operate at
frequencies above 200MHz
¾ HSTL accepts minimal input swing from 0.65V to
0.85V (nominally) with the output swing typically 0
to 1.5V
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Single HSTL Circuit
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HSTL I/O Levels
¾ Specification includes both dc and ac levels
¾ Devices switches state after crossing the ac threshold and
does not switch back as long as the input stays beyond the dc
threshold
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HSTL Output Buffers
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SSTL
¾ SSTL are particularly intended for single and Double
Data Rate (DDR) SDRAMS and support frequencies
above 333MHz
¾ Ideal for main memory applications with long
transmission line stubs due to trace routing of Dual Inline
Memory Modules (DIMMs)
¾ Long stubs are isolated from buses using an external stub
resistor
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SSTL DDR Memory System
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Emitter Coupled
Logic (ECL)
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Introduction
¾ “Emitter coupled” refers to the fact that emitters of a
driver stage constitute an output connecting to the next
stage
¾ A differential amplifier provides high impedance inputs
and voltage gain with the circuit
¾ Emitter follower output restores the logic levels and
provides low output impedance for strong line driving and
high fan-out
¾ Positive and negative supply voltages required for
standard ECL
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Applications and Uses
¾ Board-level applications:
• Clock and data distribution, backplane transmission,
multiplexing, translation (voltage level shifting and
interfacing to other logic families), state machines
¾ System applications:
• High-speed test equipment, optical networking
equipment, ultra high-speed terabit routers, network
attached storage devices, OC192 SONET, 10Gigabit
Ethernet, enterprise computing servers, and highperformance workstations
¾ Differential uses:
• Clock distribution and interfacing
¾ Single-ended uses:
• Logic circuits
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Basic Device Operation (1)
¾ ECL typical emitter follower output, termination and input
structure
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Basic Device Operation (2)
¾Circuit Operation
• The driver’s output stages are emitter follower circuits. They
provide level shifting from the differential amplifier to ECL output
levels and provide a low output impedance for driving
transmission lines
• The emitter follower output’s transistors operate in their active
regions with dc current flowing at all times. This increases
switching speeds and helps maintain fast turn-off times
• The ECL output impedance is low, typically on the order of
4-8 Ohm, which provides superior driving capability
• ECL input circuit is a current switching differential amplifier
with high input impedance. In order to provide adequate input
stage headroom, the common-mode voltage is around (Vcc – 1.3V)
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ECL Standards (1)
¾ Most ECL family devices adhere to one of two standards,
the 10K standard or the 100K standard
• The terms 10K and 100K specify whether the devices
adhere to the “10K” or the “100K” input and output dc
electrical characteristics (i.e., the signaling levels)
¾ Five kinds of ECL family outputs
• 10K/ 100K dc signaling levels (~800mV)
• CML dc signaling levels (~800mV, but also 400mV)
• Reduced swing output levels (~400, but also 200, 600mV)
• Vendor-specific variable, adjustable, or selectable output
levels (~0 to 800mV)
Note: output voltage values listed in parentheses are peak-topeak differential signal voltages
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10K is not temperature
compensated
100K is temperature
compensated
ECL Standards (2)
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ECL Interfaces
¾ Standard (a) single-ended ECL interconnect, (b) differential ECL
interconnect, and (c) differential driver with independent singleended receivers
¾ A typical ECL circuit interface may be defined as a differential
driver device sending two complementary signals over a pair of
standard, controlled impedance lines to an ECL differential receiver
device, as in (b).
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Advantages and Disadvantages of
Standard Interface
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Advantage of single-ended (SE) interconnects are decreased
board routing and reduced system power demand
Disadvantages of SE include higher jitter, phase error, and
duty cycle skew, high noise sensitivity, critically narrow
voltage margins, poor receiver sensitivity and higher EMI
emission
Differential interconnect advantages include high commonmode noise rejection, wide signal interface windows, high
receiver sensitivity and low EMI emission
Differential interconnect disadvantages include increased
board routing and increased system power dissipation
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Differential Interface (1)
¾ Differential signals are used in most ECL interfacing and
clock distribution applications because of their low skew
and high noise immunity
¾ The timing of 0-to-1 or 1-to-0 transition does not depend
critically on device voltage thresholds which may change
with temperature or between devices
¾ The differential definition of logical 0 and 1 provides an
outstanding noise immunity, since noise created by
power supply variations or coupled from external
sources tends to be a common-mode signal
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Differential Interface (2)
¾ A standard differential driver signal is characterized by a received signal
swing
¾ Receiver sensitivity is specified by data sheets as the peak-to-peak (Vpp)
input swing voltage
¾ Input swing greater than the allowed maximum may cause degraded
frequency performance and increase the input propagation delay
¾ Input swings less than the specification minimum will cause diminished
receiver output amplitude and possible errors
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Differential Interface (3)
¾ Differential input high noise immunity is illustrated in the following figure
¾ Each input signal to a differential receiver is characterized by a Vin high
voltage (VIH) level and a Vin low voltage (VIL). Proper operation is achieved
when the VIH level falls within spec limits, VIHCMR (voltage input high
common-mode range) minimum to maximum
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Curent Mode Logic
(CML)
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Introduction
¾ CML is ECL technologies that are being implemented in
many of the newest high-speed devices
¾ CML serial signaling rates typically range from 1Gbps to
over 10Gbps and higher and the data rate that CML can
support depends upon the manufacturing process
technology
¾ CML applications include: output/input stages of SERDES
transceivers, point-to-point configurations, SDH/SONET
transmission equipment, high-speed backplane
interconnects, high-speed serial links and others
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CML Output Structure
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•
Consists of a common-emitter
differential transistor pair with 50 Ohm
collector resistors, which can supply
source termination when driving 50
Ohm transmission lines
The driver’s constant-current sink
sinks the same current regardless of the
load placed upon the outputs or the
values of pull-ups or termination
resistors used (within limits)
The constant current sink in CML
structure creates less switching noise
so output rise and fall times of less
than 100ps are possible
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CML Input Structure
• As shown in this figure, the
CML input structure has a internal
50 Ohm input impedance for ease of
termination
• Some devices do not have such
internal termination resistors and
allow external termination resistor
to be used for greater flexibility
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A CML Specification Example
¾ The table lists key specifications
for a typical vendor’s implementation
• VTR and VCP specify the single-ended
true and complement voltage of the
driver output
• |VOD| is the driver’s differential
output voltage magnitude
• VOS is the driver’s common-mode
voltage
• RT is the termination resistor
• VID(min) the receiver’s differential
input threshold voltage
¾ Switching levels for a CML
800mV differential output example
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AC/DC–Coupled CML (1)
¾
AC - coupled CML circuit with two termination resistor pulled up to VT
¾
DC - coupled CML circuit with termination resistors pulled up to VCC
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AC/DC–Coupled CML (2)
¾
DC - coupled CML circuit with all resistors internal to the chips
¾
DC - coupled CML circuit with open-collector driver
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AC/DC–Coupled CML (3)
• CML output waveforms for AC and DC coupling (a) ACcoupled, loaded with internal 50 Ohm collector resistor and
(b) DC-coupled, loaded with 25 Ohm equivalent, internal
50Ohm collector resistor in parallel with 50 Ohm termination
resistor
(a)
(b)
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Difference Between CML and ECL
• The main difference between ECL and CML is that ECL
contains emitter follower circuits in the output stage and CML
does not. It results in the dc voltage level (common-mode dc
voltage) of the ECL outputs to be lower than the CML outputs
by approximately one diode voltage drop plus another 100mV
to 200mV
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Emphasis and Equalization
¾ Transmission media generally have a low-pass frequency
response, cause the distortion of signals at receive side
¾ A means of improving the signal quality is to transmit the
high-frequency components with a larger amplitude than the
low-frequency components
¾ One method by which higher frequencies are amplified
more prior to transmission is called pre-emphasis/deemphasis and sometimes, transmit equalization
¾ Amplification of the higher frequencies of a signal can also
be done at the receiver to open up the eye of the received
signal. The process is called equalization, or sometime as
receive equalization
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Pre-Emphasis/De-Emphasis
¾ Driver output voltages plotted as single-ended and referenced
to ground illustrating both pre-emphasis and de-emphasis
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Adaptive Equalization Example
¾ Adaptive cable equalizer consists of CML input/output buffer
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