APA2058
2.4W Stereo Fully Differential Audio Power Amplifier With Stereo Class AB
Cap-free Headphone Driver and LDO
Features
General Description
•
•
The APA2058 is a stereo fully differential audio power
amplifier with stereo Class-AB cap-free headphone driver
•
•
•
•
•
•
•
•
•
•
•
Meeting VISTATM Requirement
Fully Differential Power Amplifier with
and LDO available in a TQFN5X5-32A pins package.
The built-in gain setting at power amplifier can minimize
Excellent RF Rectification Immunity
No Output Capacitor Required for Head
the external component counts. For the flexible application,
the gain can be set to 4-steps, 10, 12, 15.6, and 21.6dB by
Phone Driver
Integrated LDO (Low Dropout Regulator) for
Audio Codec (3.3V)
gain control pins (GAIN0 and GAIN1). The power amplifier’s
fully differential architecture provides high PSRR, in-
Adjustable Gain Setting for Power Amplifier
creased immunity to noise and RF rectification.
AV=-1.5V/V Fixed Gain Setting for Headphone
The APA2058 power amplifiers are capable of driving
Driver
2.4W at VDD=5V into 4Ω speaker, the cap-free headphone
drivers can provide 180mW at HV DD=3.3V into 16Ω
Fast Start-up Time
headphones, and the LDO has a maximum 200mA(3.3V)
driver current for audio codec. The APA2058 provides ther-
Integrated De-Pop Circuitry
High PSRR (Power Supply Rejection Ratio)
mal and over-current protections.
The cap-free headphone driver eliminates the DC block-
Thermal and Over-Current Protections
Less External Components Required
ing capacitors at outputs, save the PCB space. The integration of fully differential power amplifier, cap-free head-
Space Saving Package
– TQFN5x5-32A
phone driver, and LDO is a best solution for VISTATM requirement and it can lower the total BOM costs.
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
Common Mode Rejection Ratio (dB)
•
•
•
+0
LCD Monitor
Notebook
Portable DVD
Simplified Application Circuit
Audio
Codec
Stereo
Speakers
-10
-20
-30
-40
VDD=5.0V
RL=4Ω
AV=10dB
Vin=0.2VPP
Ci=0.47µF
Input Short
AMP Mode
-50
-60
-70
-80
-90
-100
20
100
1k
10k 20k
Frequency (Hz)
Stereo
Headphone
LDO (Low Drop
-Out Regulator)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
1
www.anpec.com.tw
APA2058
Ordering and Marking Information
APA2058
Package Code
QB : TQFN5x5-32A
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APA2058 QB :
APA2058
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
17 HVDD
18 PVDD
20 ROUTP
19 ROUTN
22 HP_EN
21 PGND
24 BIAS
23 AMP_EN
Pin Configuration
LDO_EN 25
16 HP_LO
RIN_H 26
15 HP_RO
14 HVSS
LIN_H 27
GND 28
13 CVSS
TQFN5x5-32A
(Top View)
LDOUT 29
12 CPN
11 CGND
VDD 30
PVDD 8
LOUTN 7
PGND 5
LOUTP 6
LINP_A 3
9 NC
LINN_A 4
GAIN1 32
RINN_A 1
10 CPP
RINP_A 2
GAIN0 31
=Thermal-Pad (connected the Thermal-Pad to GND plane for better heat dissipation)
Absolute Maximum Ratings
Symbol
VDD
HVDD
VSS
(Note 1)
Parameter
Rating
Supply Voltage (VDD to GND, PVDD to PGND)
-0.3 to 6
Supply Voltage (HVDD to GND)
-0.3 to 6
Supply Voltage (HVSS, CVSS to GND)
-6 to +0.3
Input Voltage (RINN_A, RINP_A, LINN_A, LINP_A to GND)
Input Voltage (RIN_H, LIN_H to GND)
-0.3 to VDD+0.3
V
VSS-0.3 to HVDD+0.3
Input Voltage (GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN to GND)
Input Voltage (PGND, CGND to GND)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
Unit
-0.3 to VDD+0.3
-0.3 to +0.3
2
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APA2058
Absolute Maximum Ratings (Cont.)
Symbol
TJ
Parameter
Rating
Maximum Junction Temperature
Unit
150
TSTG
Storage Temperature Range
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
PD
(Note 1)
ο
-65 to +150
C
260
Power Dissipation
Internally Limited
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
TQFN5X5-32A
Thermal Resistance -Junction to Case
Unit
(Note 2)
40
ο
(Note 3)
TQFN5X5-32A
C/W
8
Note 2: Please refer to “ Layout Recommendation”, the Thermal-Pad on the bottom of the IC should soldered directly to the PCB’s
Thermal-Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz
copper thickness.
Note 3: The case temperature is measured at the center of the Thermal-Pad on the underside of the TQFN5X5-32A package.
Recommended Operating Conditions
Symbol
Parameter
Range
VDD
Supply Voltage
4.5 ~ 5.5
HVDD
Supply Voltage
3.0 ~ 5.5
VIH
High Level Input Voltage
GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN
2 ~ VDD
VIL
Low Level Input Voltage
GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN
0 ~ 0.5
VIC
Common Mode Input Voltage
ILDOUT
For Power Amplifier
0.5 ~ VDD-0.5
For Headphone Amplifier
HVSS ~ HVDD
Output Current (LDOUT)
0 ~ 200
TA
Ambient Temperature Range
-40 ~ 85
TJ
Junction Temperature Range
-40 ~ 125
COUT
LDO Output Capacitor (MLCC type)
1 ~ 100
RL
Speaker Resistance
4~
RL
Headphone Resistance
16 ~
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
3
Unit
V
mA
ο
C
µF
Ω
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APA2058
Electrical Characteristics
o
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted)
Symbol
Parameter
V AMP_EN =0V,
IDD(HVDD)
IDD(VDD)
Supply Current
VHP_EN=VLDO_EN=5V
IAMP(HVDD)
IAMP(VDD)
Power Amplifier Supply Current
IHP(VDD)
Headphone Driver Supply Current
LDO Supply Current
II
VHP_EN=0V
V AMP EN =5V,
ISD(HVDD)
ISD(VDD)
VLDO_EN=0V
V AMP_EN =VLDO_EN=5V,
ILDO(HVDD)
ILDO(VDD)
V AMP_EN =VHP_EN=VLDO_EN=0V
V AMP_EN =VHP_EN=5V,
IHP(HVDD)
Shutdown Current
Input Current
APA2058
Test Conditions
Unit
Min.
Typ.
Max.
HVDD
-
2.5
5
VDD
-
9
18
HVDD
-
0.1
0.2
VDD
-
4.5
11
HVDD
-
2.5
5
VDD
-
6
12
HVDD
-
0.1
0.2
VDD
-
0.4
0.65
HVDD
-
-
2
VDD
-
-
5
GAIN0, GAIN1, LDO_EN, AMP_EN,
HP_EN
-
-
1
CB=0.47µF
-
25
-
AV=10dB
-
76
-
AV=12dB
-
60
-
AV=15.6dB
-
40
-
VHP_EN=VLDO_EN=0V
mA
µA
SPEAKER MODE, AV =10dB
TSTART-UP
Ri
AV
VOS
PO
Start-Up Time from Shutdown
Input Resistor
Closed-Loop Gain
Output Offset Voltage
Output Power
AV=21.6dB
17
20
-
VGAIN0=VGAIN1=0V.
9.5
10
10.5
VGAIN0=0V, VGAIN1=VDD
11.5
12
12.5
VGAIN0=VDD, VGAIN1=0V
15.1
15.6
16.1
VGAIN0=VGAIN1=VDD.
21.1
21.6
22.1
RL=8Ω
-
5
20
THD+N=1%, fin=1kHz
RL=4Ω
RL=8Ω
1.9
1.3
-
1
-
2.4
1.5
-
Total Harmonic Distortion Plus
Noise
fin=1kHz
RL=4Ω, PO=1.4W
RL=8Ω, PO=0.9W
-
0.07
0.05
-
Channel Separation
fin=1kHz
RL=4Ω, Po=200mW
RL=8Ω, Po=130mW
-
-110
-110
-
PSRR
Power Supply Rejection Ratio
fin=217Hz, Vrr=0.2Vrms, RL=8Ω
-
-75
-
CMRR
Common Mode Rejection Ratio
fin=1kHz, Vin=0.2Vrms, RL=8Ω
-
-65
-
S/N
Signal-to-Noise Ratio
fin=20~20kHz With A-weighting Filter
RL=4Ω, PO=1.4W
RL=8Ω, PO=0.9W
-
100
100
-
Vn
Noise Output Voltage
fin=20~20kHz, With A-weighting Filter
RL=8Ω
-
22
-
Crosstalk
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
4
kΩ
dB
mV
W
THD+N=10%, fin=1kHz
RL=4Ω
RL=8Ω
THD+N
ms
%
dB
µVrms
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APA2058
Electrical Characteristics (Cont.)
o
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted)
Symbol
Parameter
APA2058
Test Conditions
Unit
Min.
Typ.
Max.
-
10
-
HEADPHONE MODE, AV = -1.5V/V, CPF=CPO=1µF(X5R type)
TSTART-UP
Start-Up Time from shutdown
Ri
Input Resistor
AV
Closed-Loop Gain
VOS
Output Offset Voltage
PO
Output Power
VO
THD+N
Crosstalk
PSRR
Output Swing Voltage
Total Harmonic Distortion
Plus Noise
Channel Separation
Power Supply Rejection
Ratio
S/N
Signal-to-Noise Ratio
Vn
Noise Output Voltage
CB=0.47µF
RL = 32Ω
THD+N=1%, fin=1kHz
RL=16Ω
RL=32Ω
THD+N=10%, fin=1kHz
RL=16Ω
RL=32Ω
THD+N=1%, fin=1kHz
RL=320Ω,
RL=10kΩ,
THD+N=10%, fin=1kHz
RL=320Ω,
RL=10kΩ,
fin=1kHz
RL=16Ω , PO=125mW
RL=32Ω, PO=88mW
RL=320Ω, VO=1.5V
RL=10kΩ, VO=1.6V
fin=1kHz
RL=16Ω , PO=16mW
RL=32Ω, PO=12mW
RL=320Ω, VO=0.22V
RL=10kΩ, VO=0.22V
fin=217Hz,Vrr=0.2Vrms
RL=32Ω,
fin=20~20kHz, With A-weighting Filter
RL=16Ω , PO=125mW
RL=32Ω, PO=88mW
RL=320Ω, VO=1.5V
RL= 10kΩ, VO=1.6V
fin=20~20kHz, With A-weighting Filter
RL=32Ω
ms
17
20
-
kΩ
-1.45
-1.5
-1.55
V/V
-
1
5
mV
140
120
-
100
180
160
-
150
2.0
2.1
-
2.45
2.6
-
1.8
-
-
-
-
-
0. 03
0. 02
0. 005
0. 004
-82
-82
-77
-77
-80
99
100
100
100
mW
V
-
%
-
-
dB
-
-
15
-
µVrms
-
-
200
mA
3.2
3.3
3.4
V
LDO (LOW DROP-OUT REGULATOR)
IO
Output Current
VO
Output Voltage
IO=1mA
Line Regulation
IO=1mA, VDD=4.5V to 5.5V
-
1.5
5
mV
Load Regulation
IO=1mA to 200mA
-
0.03
0.1
mV/mA
Power Supply Rejection
Ratio
IO=1mA,fin=120Hz,Vrr=0.2Vrms
-
-50
-
dB
-
50
-
kΩ
-
450
-
kHz
PSRR
RDIS
Discharge Resistor
CHARGE PUMP, CPF=CPO=1µF(X5R type)
FOSC
Oscillator Frequency
REQ
Equivalent Resistance
CVss
Negative Output Voltage
RDIS
Discharge Resistor
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
No load
5
-
10
-
Ω
-5.1
-5
-4.9
V
-
5
-
kΩ
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APA2058
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
THD+N vs. Frequency
THD+N vs. Output Power
1
PO=0.14W
0.1
VDD=4.5V
0.1
VDD=5.5V
100m
1
PO=1.4W
0.01 VDD=5.0V
RL=4Ω
Ci=0.47µF
AV=10dB
BW<22kHz
AMP Mode
0.001
20
100
VDD=5.0V
0.01
10m
PO=0.7W
THD+N (%)
THD+N (%)
10 R =4Ω
L
fin=1kHz
Ci=0.47µF
AV=10dB
BW<22kHz
1 AMP Mode
5
Output Power (W)
Common Mode Rejection Ratio (dB)
Crosstalk (dB)
+0
-60
-80
Right to Left
-100
Left to Right
-120
20
100
1k
-20
-30
-40
-50
-60
-70
-80
-90
-100
10k 20k
VDD=5.0V
RL=4Ω
AV=10dB
Vin=0.2VPP
Ci=0.47µF
Input Short
AMP Mode
-10
20
100
Frequency (Hz)
THD+N vs. Frequency
RL=8Ω
fin=1kHz
Ci=0.1µF
AV=10dB
BW<22kHz
AMP Mode
VDD=4.5V
0.01
VDD=5.0V
VDD=5.5V
10m
PO=0.09W
0.1
0.1
0.01
10k 20k
1
THD+N (%)
THD+N (%)
1
1k
Frequency (Hz)
THD+N vs. Output Power
10
10k 20k
CMRR vs. Frequency
Crosstalk vs. Frequency
+0 TT TTTTT
VDD=5.0V
R =4Ω
-20 A L=10dB
V
Ci=0.47µF
-40 PO=200mW
AMP Mode
-140
1k
Frequency (Hz)
100m
1
0.001
5
Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
PO=0.45W
PO=0.9W
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
BW<22kHz
AMP Mode
20
100
1k
10k 20k
Frequency (Hz)
6
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
CMRR vs. Frequency
+0
Common Mode Rejection Ratio (dB)
-60
-80
Right to Left
-100
Left to Right
-120
-140
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
100
1k
VDD=5.0V
RL=8Ω
AV=10dB
Vin=0.2VPP
Ci=0.47µF
Input Short
AMP Mode
10k 20k
20
100
+22
+200
+21
+180
Phase
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
AMP Mode
+7
10
100
1k
10k
200k
Gain (dB)
Gain (dB)
+9
+220
Phase (deg)
Gain
+8
+220
+20
+180
Phase
+160
+19
+140
+18
VDD=5.0V
RL=8Ω
AV=21.6dB
Ci=0.47µF
AMP Mode
10
100
Output Noise Voltage vs.
Frequency
-20
Left channel
-40
Crosstalk (dB)
Output Noise Voltage (Vrms)
Right channel
10k
200k
+140
VDD=5.0V
HVDD=3.3V
RL=4Ω(AMP)
RL=10kΩ(HP)
PO=200mW(AMP)
AMP(active) mode
HP mode
-60
-80
Left(AMP) to Right(HP)
-100 Right(AMP) to Right(HP)
-120
-140
100
1k
Crosstalk vs. Frequency
+0
VDD=5.0V
RL=8Ω
AV=10dB
Cin=0.47µF
A-Wighting
AMP Mode
20
+160
Frequency (Hz)
10µ
1µ
+200
Gain
Frequency (Hz)
50µ
10k 20k
Frequency Response
Frequency Response
+11
+10
1k
Frequency (Hz)
Frequency (Hz)
Phase (deg)
Crosstalk (dB)
Crosstalk vs. Frequency
+0 TTTTTTT
VDD=5.0V
R =8Ω
-20 A L=10dB
V
Ci=0.47µF
-40 PO=130mW
AMP Mode
1k
10k 20k
20
100
Right(AMP) to Left(HP)
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
Left(AMP) to Left(HP)
7
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
THD+N vs. Output Voltage
10
10
VDD=5.0V
HVDD=3.3V
fin=1kHz
Ci=1µF
BW<22kHz
In Phase
HP Mode
0.1
1
THD+N (%)
1
THD+N (%)
THD+N vs. Output Power
RL=16Ω
RL=32Ω
0.01
VDD=5.0V
HVDD=3.3V
RL=16Ω
fin=1kHz
Ci=1µF
BW<22kHz
HP Mode
In Phase
0.1
Mono
RL=320Ω
RL=10KΩ
0.001
0
500m
1
1.5
2
2.5
0.01
3
10m
100m
THD+N vs. Frequency
Crosstalk vs. Frequency
1
+0
VDD=5.0V
HVDD=3.3V
RL=16Ω
Ci=1µF
BW<22kHz
HP Mode
0.1
-20
PO=13mW
-40
Crosstalk (dB)
THD+N (%)
500m
Output Power (W)
Output Voltage (Vrms)
PO=63mW
PO=125mW
0.01
VDD=5.0V
HVDD=3.3V
RL=16Ω
PO=16mW
Ci=1µF
HP Mode
-60
Right to Left
-80
Left to Right
-100
-120
0.001
-140
20
100
1k
10k 20k
20
100
THD+N vs. Output Power
THD+N (%)
1
THD+N vs. Frequency
VDD=5.0V
HVDD=3.3V
RL=32Ω
fin=1kHz
Ci=1µF
BW<22kHz
HP Mode
0.1
10k 20k
1
In Phase
THD+N (%)
10
1k
Frequency (Hz)
Frequency (Hz)
Mono
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
BW<22kHz
HP Mode
0.1
PO=9mW
PO=88mW
0.01
PO=44mW
0.01
10m
100m
0.001
300m
Output Power (mW)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
20
100
1k
10k 20k
Frequency (Hz)
8
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
Output Noise Voltage vs.
Frequency
Crosstalk vs. Frequency
50µ
+0
-20
Crosstalk (dB)
-40
Output Noise Voltage (Vrms)
VDD=5.0V
HVDD=3.3V
RL=32Ω
PO=12mW
Ci=1µF
HP Mode
Right to Left
-80
Left to Right
-100
-120
20
Right channel
10µ
-60
-140
Left channel
100
1k
VDD=5.0V
HDD=3.3V
RL=32Ω
Ci=1µF
A-Weighting
HP Mode
1µ
10k 20k
20
100
Frequency (Hz)
+220
Gain
+0 T
+200
+2
+180
Phase
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
HP Mode
+0
10
100
-40
Crosstalk (dB)
+3
Phase (deg)
Gain (dB)
-20
+1
-60
Left(HP) to Right(AMP)
-80
Right(HP) to Left(AMP)
-120
10k
VTDD=5.0V
HVDD=3.3V
RL=8Ω(AMP)
RL=16Ω(HP)
PO=16mW(HP)
AMP Mode
HP(active) Mode
-100
+160
1k
-140
+140
200k
Right(HP) to Right(AMP)
Left(HP) to Left(AMP)
20
100
Frequency (Hz)
THD+N vs. Frequency
10k 20k
Crosstalk vs. Frequency
+0
VDD=5.0V
HVDD=3.3V
RL=320Ω
Ci=1µF
BW<22kHz
HP Mode
-20
-40
Crosstalk (dB)
THD+N (%)
1k
Frequency (Hz)
1
0.1
10k 20k
Crosstalk vs. Frequency
Frequency Response
+4
1k
Frequency (Hz)
VO=0.15V
0.01
VDD=5.0V
HVDD=3.3V
RL=320Ω
VO=0.22Vrms
Ci=1µF
HP Mode
-60
Right to Left
-80
Left to Right
-100
VO=0.75V
-120
VO=1.5V
0.001
20
100
-140
1k
10k 20k
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
9
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
THD+N vs. Frequency
1
Crosstalk vs. Frequency
+0
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=1µF
BW<22kHz
HP Mode
-40
Crosstalk (dB)
THD+N (%)
0.1
VDD=5.0V
HVDD=3.3V
RL=10kΩ
VO=0.22Vrms
Ci=1µF
HP Mode
-20
VO=0.16V
0.01
-60
Right to Left
-80
Left to Right
-100
VO=1.6V
-120
VO=0.8V
0.001
20
100
1k
-140
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs.
Frequency
Frequency Response
+4
50µ
+220
+3
Left channel
Gain (dB)
Right channel
10µ
VDD=5.0V
HDD=3.3V
RL=10kΩ
Ci=1µF
A-Weighting
HP Mode
1µ
20
+200
+2
+180
Phase
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=0.47µF
HP Mode
+1
100
1k
+0
10k 20k
Phase (deg)
Output Noise Voltage (Vrms)
Gain
10
100
+160
1k
+140
200k
10k
Frequency (Hz)
Frequency (Hz)
AMP Attenuation vs. Frequency
HP Attenuation vs. Frequency
+0
-10
AMP Attenuation (dB)
-30
-40
-50
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
VO=2Vrms (AMP enable)
AMP Mode (disable)
HP Attenuation (dB)
-20
-60
-70
-80
Left channel
-90
Right channel
-10
20
-30
-40
-50
VDD=5.0V
HVDD=3.3V
RL=32Ω
Ci=1µF
VO=1Vrms (HP enable)
HP Mode (disable)
-60
-70
-80
-90
-100
Right channel
-110
-110
Left channel
-120
-120
-100
20
100
1k
10k 20k
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
10
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
PSRR vs. Frequency
HP Attenuation vs. Frequency
-20 TT
+0
-10
AMP Attenuation (dB)
-20
-30
-40
-50
Power Supply Rejection Ratio (dB)
VDD=5.0V
HVDD=3.3V
RL=10kΩ
Ci=1µF
VO=1Vrms (HP enable)
HP Mode (disable)
-60
Right channel
-70
-80
Left channel
-90
VDD=5.0V
RL=8Ω
AV=10dB
Ci=0.47µF
Vrr=0.2Vrms
AMP Mode
-30
-40
-50
-60
-70
-80
-90
-100
-100
-110
-110
-120
T
20
100
1k
-120
10k 20k
Vrr:Ripple Voltage on VDD
20
100
-70
-80
-90
-100
-110
Vrr:Ripple Voltage on HVDD
20
100
1k
-90
-100
-110
Vrr:Ripple Voltage on HVDD
20
100
1k
10k 20k
PSRR vs. Frequency
LDO Output Voltage vs. Supply
Voltage
3.35
VDD=5.0V
IO=10mA
Vrr=0.2Vrms
LDO Mode
3.34
-50
-60
-70
1k
10k 20k
3.31
3.30
IO=100mA
IO=10mA
3.29
IO=200mA
3.28
3.27
3.25
4.5
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
3.32
3.26
Vrr:Ripple Voltage on VDD
100
LDO Mode
3.33
-40
20
-80
Frequency (Hz)
-30
-80
-70
Frequency (Hz)
Output Voltage (Volt)
Power Supply Rejection Ratio (dB)
-20
-20 TTT TT TT
VDD=5.0V
-30
HVDD=3.3V
RL=10kΩ
-40
Ci=1µF
Vrr=0.2Vrms
-50
HP Mode
-60
-120
10k 20k
+0
-10
10k 20k
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
PSRR vs. Frequency
-20TTTTT TT T
VDD=5.0V
-30 HV =3.3V
DD
RL=32Ω
-40
Ci=1µF
-50 Vrr=0.2Vrms
HP Mode
-60
-120
1k
Frequency (Hz)
Frequency (Hz)
4.7
4.9
5.1
5.3
5.5
Supply Voltage (Volt)
11
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
LDO Drop-Out Voltage vs. Output
Current
0.15
2.0
1.8
1.6
0.12
Power Dissipation (W)
Drop-Out Voltage (Volt)
LDO Mode
Power Dissipation vs. Output
Power
0.09
0.06
0.03
1.4
VDD=5.5V
1.2
VDD=5.0V
1.0
VDD=4.5V
0.8
0.6
RL=4Ω
fin=1kHz
Mono
AMP Mode
0.4
0.2
0
0
0.1
0.2
0.0
0.0
0.3
0.5
1.0
Output Current (A)
1.5
2.0
2.5
3.0
Output Power (W)
Power Dissipation vs. Output
Power
300
1.0
Power Dissipation vs. Output
Power
0.9
250
Power Dissipation (mW)
Power Dissipation (W)
0.8
0.7
RL=16Ω
200
0.6
VDD=5.5V
0.5
150
VDD=5.0V
0.4
VDD=4.5V
0.3
100
RL=8Ω
fin=1kHz
Mono
AMP Mode
0.2
0.1
0.0
0.0
0.5
1.0
RL=32Ω
1.5
VDD=5.0V
HVDD=3.3V
fin=1kHz
Mono
HP Mode
50
0
2.0
0
25
50
Output Power vs. Supply Voltage
RL=4Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
1.8
2.4
2.2
THD+N=10%
2.0
175
200
RL=8Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
1.6
THD+N=10%
1.4
1.2
THD+N=1%
1.8
1.6
150
2.0
Output Power (W)
Output Power (W)
2.6
100 125
Output Power vs. Supply Voltage
3.0
2.8
75
Output Power (mW)
Output Power (W)
THD+N=1%
1.0
1.4
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
0.8
4.5 4.6 4.7
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
4.8 4.9 5.0 5.1 5.2
5.3 5.4 5.5
Supply Voltage (V)
Supply Voltage (V)
12
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25°C, unless otherwise noted.)
Supply Current vs. Output Power
0.8
0.7
0.45
VDD=5.0V
0.6
0.5
0.4
0.3
RL=4Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
0.2
0.1
0.0
0.0
0.5
1.0
VDD=5.5V
0.40
VDD=4.5V
Supply Current (A)
Supply Current (A)
Supply Current vs. Output Power
0.50
VDD=5.5V
1.5
2.0
2.5
VDD=5.0V
0.35
VDD=4.5V
0.30
0.25
0.20
RL=8Ω
AV=10dB
fin=1kHz
Mono
AMP Mode
0.15
0.10
0.05
0.00
0.0
3.0
0.5
Output Power vs. Load Resistance
1.5
2.0
Output Power vs. Load Resistance
2.6
250
VDD=5.0V
AV=10dB
fin=1kHz
Mono
AMP Mode
2.2
2.0
1.8
1.6
THD+N=10%
1.4
VDD=5.0V
HVDD=3.3V
fin=1kHz
Mono
HP Mode
200
Output Power (W)
2.4
Output Power (W)
1.0
Output Power (W)
Output Power (W)
1.2
1.0
150
THD+N=10%
100
THD+N=1%
50
0.8
THD+N=1%
0.6
11
Supply Current (mA)
10
4
8
12
16
20
24
28
0
10
32
Supply Current (IVDD) vs. Supply
Voltage (VDD)
Supply Current (IHVDD) vs. Supply
Voltage (HVDD)
3.0
HVDD=3.3V
No Load
2.5
AMP,HP enable
(IHVDD=2.2mA)
7
6
1000
Load Resistance (Ω)
9
8
100
Load Resistance (Ω)
Supply Current (mA)
0.4
AMP enable
(IHVDD=0.1mA)
HP enable
(IHVDD=2.2mA)
1.5
AMP,HP enable
(IVDD=9.3mA)
HP enable
(IVDD=5.0mA)
1.0
0.0
3.3
4
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AMP enable
(IVDD=4.9mA)
3.4
3.5
3.6
Supply Voltage(V)
Supply Voltage(V)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
2.0
0.5
5
VDD=5.0V
No Load
13
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APA2058
Operating Waveforms
Power On
Power Off
VDD
VDD
1
1
2
2
VROUT
VROUT
3
3
VHP_RO
VHP_RO
CH1: VDD, 2V/Div, DC
CH2: VROUT, 20mV/Div, DC
CH3: VHP_RO, 20mV/Div, DC
CH1: VDD, 2V/Div, DC
TIME: 5ms/Div
TIME: 20ms/Div
CH2: VROUT, 20mV/Div, DC
CH3: VHP_RO, 20mV/Div, DC
Speaker Enable
Speaker Disable
VAMP_EN
VAMP_EN
1
1
VOUTP
VOUTP
2
2
CH1: VAMP_EN, 2V/Div, DC
CH1: VAMP_EN, 2V/Div, DC
CH2: VOUTP, 1V/Div, AC
CH2: VOUTP, 1V/Div, AC
TIME: 5ms/Div
TIME: 1ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
14
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APA2058
Operating Waveforms (Cont.)
Headphone Disable
Headphone Enable
VHP_EN
VHP_EN
1
1
VHP_RO
VHP_RO
2
2
CH1: VHP_EN, 2V/Div, DC
CH1: VHP_EN, 2V/Div, DC
CH2: VHP_LO, 1V/Div, AC
CH2: VHP_LO, 1V/Div, AC
TIME: 5ms/Div
TIME: 1ms/Div
LDO Power Off
LDO Power On
VDD
VDD
1
1
VLDOUT
VLDOUT
2
2
IO=120mA
IO=120mA
CH1: VDD, 2V/Div, DC
CH1: VDD, 2V/Div, DC
CH2: VLDOUT, 1V/Div, DC
CH2: VLDOUT, 1V/Div, DC
TIME: 100µs/Div
TIME: 20ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
15
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APA2058
Operating Waveforms (Cont.)
LDO Enable
LDO Disable
VLDO_EN
V LDO_EN
1
1
VLDOUT
V LDOUT
2
2
IO=120mA
IO=120mA
CH1: VLDO_EN, 2V/Div, DC
CH1: VLDO_EN, 2V/Div, DC
CH2: VLDOUT, 1V/Div, DC
CH2: VLDOUT, 1V/Div, DC
TIME: 1ms/Div
TIME: 1ms/Div
LDO Load Transient
LDO Line Transient
1
VDD
ILDOUT
1
2
VLDOUT
VLDOUT
2
CH1: ILDOUT, 200mA/Div, DC
CH2: VLDOUT, 5mV/Div, DC
VLDOUT Offset = 3.3V
TIME: 200µs/Div
CH1: VDD, 1V/Div, DC
VDD Offset = 5.5V
CH2: VLDOUT, 10mV/Div, DC
VLDOUT Offset = 3.3V
TIME: 200µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
16
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APA2058
Operating Waveforms (Cont.)
GSM Power Supply Rejection vs. Frequency
GSM Power Supply Rejection vs. Time
1
AMP Output Voltage (dBV)
-50
VROUT
2
VHP_RO
3
CH1: V DD, 500mV/Div, DC
VDD Offset = 5.0V
CH2: V ROUT , 20mV / Div, DC
-100
-150
+0
Supply Voltage (dBV)
+0
VDD
-50
-100
-150
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
CH3: VHP_RO , 20mV / Div, DC
TIME: 2ms/Div
+0
-50
HP Output Voltage (dBV)
-100
-150
+0
Supply Voltage (dBV)
GSM Power Supply Rejection vs. Frequency
-50
-100
-150
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
17
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APA2058
Pin Description
PIN
I/O/P
FUNCTION
NO.
NAME
1
RINN_A
I
The inverting input pin of right channel power amplifier.
2
RINP_A
I
The non-inverting input pin of right channel power amplifier.
3
LINP_A
I
The non-inverting input pin of left channel power amplifier.
4
LINN_A
I
The inverting input pin of left channel power amplifier.
5,21
PGND
P
Power amplifier’s ground.
6
LOUTP
O
The positive output pin of left channel power amplifier.
7
LOUTN
O
The negative output pin of left channel power amplifier.
8,18
PVDD
P
Power amplifier’s supply voltage pin, connect this pin to VDD.
9
NC
-
No Connection.
10
CPP
I/O
11
CGND
P
12
CPN
I/O
Charge pump flying capacitor negative connection.
13
CVSS
O
Charge pump output pin, connect this pin to the HVSS.
Charge pump flying capacitor positive connection.
Charge pump’s ground.
14
HVSS
P
Headphone driver’s negative supply voltage pin, connect this pin to CVSS.
15
HP_RO
O
The output pin of right channel headphone driver.
16
HP_LO
O
The output pin of left channel headphone driver.
17
HVDD
P
Headphone driver’s positive supply voltage pin.
19
ROUTN
O
The negative output pin of right channel power amplifier.
20
ROUTP
O
The positive output pin of right channel power amplifier.
22
HP_EN
I
Headphone drivers enable input pin; High=Enable.
23
AMP_EN
I
Power amplifiers enable input pin; Low=Enable.
24
BIAS
P
Bias voltage for power amplifiers.
25
LDO_EN
I
LDO (Low Drop-Out Regulator) enables input pin; High=Enable.
26
RIN_H
I
The input pin of right channel headphone driver.
27
LIN_H
I
The input pin of left channel headphone driver.
28
GND
P
Control block’s ground, connect this pin to CGND and PGND.
29
LDOUT
O
LDO (Low Drop-Out Regulator)’s output pin.
30
VDD
P
Control block and LDO supply voltage pin, connect this pin to PVDD.
31
GAIN0
I
Control pin for internal gain setting, MSB, Bit 1.
32
GAIN1
I
Control pin for internal gain setting, LSB, Bit 0.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
18
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APA2058
Block Diagram
240kΩ
LOUTP
LINN_A
LINP_A
LOUTN
GAIN1
PVDD
Gain
Control
GAIN0
PGND
ROUTN
RINP_A
RINN_A
ROUTP
30kΩ
20kΩ
-
LIN_H
HP_LO
+
HVDD
GND
HVSS
+
HP_RO
20kΩ
RIN_H
VDD
PVDD
LDO
Charge
Pump
30kΩ
AMP_EN
CPP
HP_EN
Control
CPN
LDO_EN
BIAS
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
VDD
LDOUT
19
CVSS
CGND
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APA2058
Typical Application Circuit
Differential input mode
VDD
Regulator Output
CO2 CO1
Ci5*
1µF
Gnd
1µF
Gain
Control
(Amplifier)
Ci1 RINN_A
0.47µF
Ci2 RINP_A
0.47µF
Ci3 LINP_A
0.47µF
Ci4 LINN_A
0.47µF
Right
Channel
Input Signal
(Amplifier)
Left
Channel
Input Signal
(Amplifier)
26 RIN_H
27 LIN_H
29 LDOUT
28 GND
Headphone
Driver Input
Signals
Regulator
Enable
Ci6*
1µF
CB
1
24 BIAS
2
23 AMP_EN
3
22 HP_EN
4
21 PGND
APA2058
Gnd
20 ROUTP
LOUTP 6
19 ROUTN
LOUTN 7
18 PVDD
PVDD 8
17 HVDD
VDD
Gnd
Power
Amplifier
Enable
Headphone
Driver Enable
0.47µF
PGND 5
Gnd
30 VDD
31 GAIN0
32 GAIN1
0.1µF 2.2µF
25 LDO_EN
CS3
VDD
HVDD
CPO
1µF
HP_LO 16
HP_RO 15
CS5
0.1µF
2.2µF
Gnd
Headphone
Jack
1µF
HVSS 14
CPN 12
CPF
CVSS 13
0.1µF 10µF
CGND 11
NC 9
CS1
CS2
CPP 10
CS4
VSS
Gnd
Tip
Sleeve
Ring
Single-ended input mode
VDD
Regulator Output
CO2 CO1
Ci5*
1µF
Gnd
1µF
Gain
Control
(Amplifier)
Ci1
Right
Channel
GndC
Input Signal
i2
(Amplifier)
Ci3
Left
Channel
Ci4
Input Signal
(Amplifier) Gnd
Gnd
26 RIN_H
27 LIN_H
28 GND
29 LDOUT
30 VDD
31 GAIN0
32 GAIN1
0.1µF 2.2µF
25 LDO_EN
CS3
RINN_A 1
Headphone
Driver Input
Signals
Regulator
Enable
Ci6*
1µF
24 BIAS
0.47µF
CB
Gnd
Power
Amplifier
Enable
Headphone
Driver Enable
0.47µF
RINP_A 2
23 AMP_EN
0.47µF
LINP_A 3
22 HP_EN
0.47µF
LINN_A 4
21 PGND
APA2058
0.47µF
PGND 5
LOUTP 6
19 ROUTN
LOUTN 7
18 PVDD
PVDD 8
17 HVDD
VDD
Gnd
20 ROUTP
VDD
HVDD
CPO
1µF
HP_LO 16
HP_RO 15
HVSS 14
VSS
Gnd
Note *：If using MLCC type capacitor for low
frequency performance, 3.3µF is recommended.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
Tip
Sleeve
20
CS5
0.1µF
2.2µF
Gnd
Headphone
Jack
1µF
CPN 12
CPF
CVSS 13
0.1µF 10µF
CGND 11
CS1
CPP 10
CS2
NC 9
CS4
Ring
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APA2058
Function Description
Fully Differential Amplifier
The Cap-free headphone drivers use a charge pump to
The APA2058’s power amplifier is a fully differential
amplifier with differential inputs and outputs. The fully
invert the positive power supply (VDD) to negative power
supply (VSS) (see Figure 1). The headphone amplifiers
differential amplifier has some advantages versus traditional amplifier. Firstly, don’t need the input coupling ca-
operate at this bipolar power supply, and the outputs reference refers to the ground. This feature eliminates the
pacitors because the common-mode feedback will compensate the input bias. The inputs can be biased from
output capacitor that using in conventional single-ended
headphone amplifiers. In addition, the power supply rail
0.5V to VDD-0.5V, and the outputs are still biased at midsupply voltage of the power amplifier. If the inputs are
for Cap-free headphone drivers has almost 1.5X compare to the single power supply rail headphone drivers.
biased out of the input range, the coupling capacitors are
required. Secondly, the fully differential amplifier has out-
Thermal Protection
The thermal protection circuit limits the junction temperature of the APA2058. When the junction tempera-
standing immunity against supply voltage ripple (217Hz)
caused by GSM RF transmitters’ signal, which is better
ture exceeds TJ = +150oC, a thermal sensor turns off the
amplifier, allowing the devices to cool. The thermal sen-
than the typical audio amplifier.
Gain Setting Function
For the convenient uses, the APA2058’s power amplifiers
provide four gain setting options by GAIN0 and GAIN1
sor allows the amplifier to start-up after the junction temperature down about 125 oC. The thermal protection is
designed with a 25 o C hysteresis to lower the average TJ
during continuous thermal overload conditions, increas-
pins.
ing lifetime of the ICs.
GAIN0
GAIN1
AV(dB)
Ri (kΩ)
Rf (kΩ)
0
0
10
76
240
Over-Current Protection (OCP)
0
1
12
60
240
1
0
15.6
40
240
• The power amplifier monitors the output buffers’current.
1
1
21.6
20
240
When the over current occurs, the output buffers’current
will be reduced and limited to a fold-back current level.
The power amplifier will go back to normal operation until
the over-current current situation has been removed. In
Headphone Mode Operation
VOUT
Conventional Headphone Driver
HVDD
addition, if the over-current period is long enough and the
IC’s junction temperature reaches the thermal protection
HVDD/2
threshold, the IC enters thermal protection mode.
• The LDO regulator provides a current-limit circuitry,
which monitors and controls P-channel MOS’s gate
Gnd
voltage, limiting the output current to 0.4A. For reliable
operation, the device should not be operated in current-
HVDD
VOUT
limit for extended period. When the output voltage drops
below 0.6V, which is caused by the over load or short
circuit, the internal short circuit current-limit circuitry limits the output current down to 250mA. The short circuit
Gnd
current-limit is used to reduce the power dissipation during short circuit condition. The short circuit current-limit
Cap-free Headphone Driver
VSS
has a blanking time feature after the under-voltage lockout threshold is reached, therefore, it will avoid the output
Figure 1: The Cap-Free Headphone Driver’s Operation
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
causing short circuit current-limit protection during startup; the blanking time is about 600µs.
21
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APA2058
Function Description (Cont.)
Over-Current Protection (OCP) (Cont.)
• The charge pump monitors the output voltage (V
SS
). In
addition, it has an over voltage protection to avoid over
current occuring on headphone driver’s output. When the
output voltage (VSS) is greater than –2V, the charge pump
will turn off the charge pump’s output. The charge pump’s
output will turn on again if the situation has been removed.
Typical under voltage protection threshold is -2V with
0.5V hysteresis.
Low Drop-Out (LDO) Regulator
The LDO regulator’s output provides maximum 200mA
drive capacity for external audio codec. A 2.2µF decoupling
capacitor with 0.1µf capacitor (filtering the high frequency
noise) is recommended at LDO regulator’s output. The
LDO regulator has built-in under-voltage lockout circuits
to keep the output shuting off until internal circuitry is operating properly. The under-voltage lockout function initiates a soft-start process after input voltage exceeds its
rising under-voltage lockout threshold during power on.
The internal soft-start circuit controls the rise rate of the
output voltage and limits the current surge during startup. Approximate 20µs delay time after the VDD is over the
under-voltage lockout threshold; the LDO regulator’s output voltage starts the soft-start. The typical soft-start interval is about 130µs and the under-voltage lockout threshold is 2.5V with 0.15V hysteresis.
Enable Mode
The APA2058 provides the independent enable control
functions and allows user disable any main circuit blocks
when not in using, and these can save the power
consumption. In addition, if either the power amplifier or
the headphone driver is disabled, the released time will
happen immediately when enable the power amplifier or
the headphone driver. However, if both the power amplifier and the headphone driver are disabled at the same
time, the released time will be the TSTART-UP Time when
enable one of them. Disable all blocks ( V AMP_EN =5V,
VHP_EN= VLDO_EN=0V), The APA2058 enters the shutdown
mode, and only consumption 5µA(Max.) at VDD supply current and 2µA(Max.) at HVDD supply current.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
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APA2058
Application Information
Windows VistaTM Premium Mobile Requirement
Device Type
Requirement
Value
Full Scale Output voltage
THD+N
Analog Line Output Jack
(RL=10kΩ)
Line output cross-talk
Noise level during system
activity
Full Scale Output voltage
Analog Headphone Output
Jack
(RL=320Ω)
THD+N
Headphone output cross-talk
Noise level during system
activity
Full Scale Output voltage
Analog Headphone Output
Jack
(RL=32Ω)
2.3Vrms
-70dB
20Hz~20kHz
-70dB
20Hz~20kHz
≤-65dBFS
100Hz~20kHz
≤-50 dB
100Hz~15kHz
≤-80dBFS
A-weighting
≥0.3Vrms
-78dB
100Hz~20kHz
-75 dB
100Hz~15kHz
-100dBFS
A-weighting
2.0Vrms
-68dB
100Hz~20kHz
-70 dB
100Hz~15kHz
≤-45dBFS
100Hz~20kHz
≤-50dB
100Hz~15kHz
≤-80dBFS
A-weighting
THD+N
Headphone output cross-talk
Noise level during system
activity
APA2058 typical performance
≥0.707Vrms
≤-65dBFS
20Hz~20kHz
≤-50dB,
20Hz~15kHz
≤-80dBFS
A-weighting
≥0.707Vrms
-100dBFS A-weighting
2.3Vrms
-100dBFS A-weighting
Input Capacitor (Ci)
leakage tantalum or ceramic capacitor is the best choice.
In the typical application, an input capacitor, Ci, is required
When polarized capacitors are used, the positive side of
the capacitors should face the amplifiers’ inputs in most
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
applications because the DC level of the amplifiers’ inputs are held at VDD/2. Please note that it is important to
minimum input impedance Ri form a high-pass filter with
the corner frequency is determined in the following
equation:
fC(highpass ) =
1
2 πR iC i
confirm the capacitor polarity in the application.
Power Supply Decoupling Capacitor, Cs
(1)
The APA2058 is a high-performance CMOS audio ampli-
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the circuit.
fier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) to be
Consider the example where Ri is 20kΩ and the specification calls for a flat bass response down to 40Hz. The
as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length
equation is reconfigured as below :
1
Ci =
2 π R i fc
between the amplifier and the speaker.
The optimum decoupling is achieved by using two different types of capacitors that target on different types of
(2)
Consider the variation of input resistance (Ri), the value
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
of Ci should be 0.2µF. Therefore, a value in the range
from 0.22µF to 1.0µF would be chosen. A further consid-
equivalent-series- resistance (ESR) ceramic capacitor,
(0.1µF typically) placed as close as possible to the device
eration for this capacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the
VDD lead works best.
load.
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom, es-
For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near
the audio power amplifier is recommended.
pecially in high gain applications. For this reason, a lowCopyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
23
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APA2058
Application Information (Cont.)
Charge Pump Flying Capacitor (CPF)
2. The output traces should be short, wide ( >50mil), and
The flying capacitor affects the load transient of the charge
pump. If the capacitor’s value is too small, it will degrade
symmetric.
3. The input trace should be short and symmetric.
the charge pump’s current driver capability and the performance of headphone amplifier. Increasing the flying
4. The power trace width should greater than 50 mil.
5. The TQFN5x5-32A thermal pad should be soldered
capacitor’s value will improve the load transient of charge
pump. Recommend using the low ESR ceramic capaci-
on PCB, and the ground plane needs solded mask (to
avoid short circuit) except the thermal pad area.
tors (X5R type is recommended) above 1µF.
Charge Pump Output Capacitor (CPO)
The output capacitor’s value affects the power ripple directly at VSS. Increasing the value of output capacitor will
reduce the power ripple. The ESR of output capacitor affects the load transient of VSS. Low ESR and greater than
1µf ceramic capacitor (X5R type is recommended) is
recommendation.
Layout Recommendation
ThermalVia
diameter
0.3mm X 9
1.15mm
0.25mm
3.6mm
4.1mm
0.5mm
3.6mm
Solder Mask
to Prevent
Short Circuit
TQFN5X5-32A Land Pattern
Recommendation
Ground
plane for
ThermalP
AD
Figure 5. TQFN5x5-32A Land Pattern Recommendation
1. All components should be placed close to the APA2058.
For example, the input capacitor (Ci) should be close
to APA2058’s input pins to avoid causing noise coupling to APA2058’s high impedance inputs; the
decoupling capacitor (CS ) should be placed by the
APA2058’s power pin to decouple the power rail noise.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
24
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APA2058
Package Information
TQFN5x5-32A
D
b
E
A
D2
A1
A3
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN5x5-32A
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
4.90
5.10
0.193
0.201
D2
3.10
3.50
0.122
0.138
E
4.90
5.10
0.193
0.201
3.50
0.122
0.138
0.45
0.014
E2
3.10
e
0.50 BSC
L
0.35
K
0.20
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
0.020 BSC
0.018
0.008
25
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APA2058
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN5x5-32A
A
H
T1
C
12.4+2.00 13.0+0.50
-0.00
-0.20
d
D
1.5 MIN.
20.2 MIN.
W
E1
12.0±0.30 1.75±0.10
F
330.0±2.00
50 MIN.
5.5±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±0.20
5.30±0.20
1.30±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TQFN5x5-32A
Tape & Reel
2500
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
26
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APA2058
Taping Direction Information
TQFN5x5-32A
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
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APA2058
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak
(Tp)*
package
body
Temperature
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
28
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APA2058
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Feb., 2010
29
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