CDB4396/7
Evaluation Board for CS4396 and CS4397
Features
Description
l Demonstrates recommended layout and
The CDB4396/7 evaluation board is an excellent means
for quickly evaluating the CS4396 or CS4397 24bit192 kHz D/A converters. The board accepts SPDIF and
SACD inputs and, with an analog output interface, presents line level signals via RCA connectors. Evaluation
requires an analog signal analyzer and a digital signal
source.
grounding arrangements
l CS8414 receives AES/EBU, S/PDIF, & EIAJ340 Compatible Digital Audio
l Supports 32kHz - 192kHz PCM Audio and
SACD Audio
l Requires only a digital signal source for a
The CS8414 digital audio receiver I.C. provides the syscomplete Digital-to-Analog Converter system tem timing and data signals necessary to operate the
Digital-to-Analog converter and will accept AES/EBU,
l Included Wall Mount power supply
SPDIF and EIAJ compatible audio data. The evaluation
board may also be configured to accept external timing
signals for operation in a user application during system
development in PCM and DSD modes.
ORDERING INFORMATION
CDB4396C.0
CDB4397C.0
Evaluation Board
Evaluation Board
I
BLOCK DIAGRAM
POWER SUPPLY
REGULATION
CS8414
ANALOG
FILTER
INPUT
SELECTOR
EXT.
PCM/DSD
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4396/7
ANALOG
FILTER
MODE
SELECTOR
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 2000
(All Rights Reserved)
DEC ‘00
DS288DB1B1
1
CDB4396/7
TABLE OF CONTENTS
1. CDB4396C.0 SYSTEM OVERVIEW ......................................................................................... 3
2. CS4396 AND CS4397 DIGITAL TO ANALOG CONVERTER ................................................. 3
3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3
4. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT .............................................. 3
5. MODE CONTROL ..................................................................................................................... 3
6. AUTOMATIC MODE SWITCHING ........................................................................................... 3
7. OUTPUT FILTER ...................................................................................................................... 4
8. POWER SUPPLIES ................................................................................................................. 4
9. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 4
10. CS4396/CS4397 MODE SETTINGS (SW2) ........................................................................... 5
LIST OF FIGURES
Figure 1. System Schematic ........................................................................................................... 7
Figure 2. Output Stage Schematic .................................................................................................. 8
Figure 3. Power Supply ................................................................................................................... 9
Figure 4. Component Placement................................................................................................... 10
Figure 5. Top - Layer 1 .................................................................................................................. 11
Figure 6. Layer 2 ........................................................................................................................... 12
Figure 7. Layer 3 ........................................................................................................................... 13
Figure 8. Layer 4 ........................................................................................................................... 14
Figure 9. Layer 4 ........................................................................................................................... 14
LIST OF TABLES
Table 1. Single Speed (16 to 50 kHz) Digital Interface Format Options.......................................... 5
Table 2. Single Speed (16 to 50 kHz) De-Emphasis Options ......................................................... 5
Table 3. Double Speed (50 to 100 kHz) Sample Rate Mode Options ............................................. 5
Table 4. Quad Speed(100 to 200 kHz) Sample Rate Mode Options .............................................. 5
Table 5. 8x Interpolated Input Mode Options (CS4397 only) .......................................................... 5
Table 6. Direct Stream Digital Options (CS4397 only) ................................................................... 5
Table 7. SWITCH S2 MODE SETTINGS TABLE............................................................................ 6
Table 8. AUTOMATIC MODE OPERATION SETTINGS ................................................................ 6
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including
use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS288DB1B1
CDB4396/7
1.
CDB4396C.0 SYSTEM OVERVIEW
The CDB4396C.0 evaluation board is an excellent
means of quickly evaluating the CS4396 or
CS4397 24 bit - 192 kHz audio D/A converters.
The evaluation board features a CS8414 digital audio input interface receiver, an analog output buffer/filter, and on board power supply regulation to
be used with a supplied AC Wall Mount power
supply. The CS8414 provides an easy interface to
32 kHz to 96 kHz digital audio signal sources. The
evaluation board also allows the user to supply external PCM data and DSD data through a 10-pin
header for system development.
2. CS4396 AND CS4397 DIGITAL TO
ANALOG CONVERTER
Please refer to either the CS4396 or CS4397 product datasheet for a complete detailed description of
these components.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 1. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock
(FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in
the CS8414 datasheet.
4. EXTERNAL DIGITAL AUDIO DATA
AND DSD INPUT PORT
The evaluation board has been designed to allow
interfacing to external systems via the 10-pin
header, JP1. This header allows the evaluation
board to accept externally generated clocks and data.
The port is activated by setting the “MODE” Control Switch “ S2” position 6 “INT/EXT” switch to
the closed position.
This port accepts PCM data, DSD data or data
from an external 8X interpolator such as an HDCD
DS288DB1B1
PMD100 or PMD200. Notice that the board has
provisions for terminating this input port for proper
signal integrity using resistors R20 through R24.
The board also features automatic mode switching
between this port and the SPDIF port when used
with a SACD player. See Section 6- “Automatic
Mode Switching” for a complete description of this
feature.
5. MODE CONTROL
The board utilizes a Dip Switch, “S2” to allow the
user to select various operational modes of the
CS4396 or CS4397. These modes include selection of the Digital Interface Format, De-emphasis,
Sample Rate modes, Internal-External Digital Audio Data, PCM-DSD Automatic Mode Switching,
64x - 128x DSD Data, +3 V/+5 V Digital Supply
voltage selection, and Mute control. See Tables 1
through 8 for a complete description of how the
switch settings set the different operating modes of
the CS4396/7. To manually set the CS4396/7
modes, set S2 position 7 to open and use S2 positions 1 through 5 to set the various modes. To set
the board into “Automatic Mode Switching” set the
S2 position 7 to the closed position. See Table 8 for
PCM-DSD settings that are set in Automatic Mode
by circuitry U2, U3, U4, U7. When using the
CS4397 with a DSD source, two input clock frequencies are possible, either 64 or 128x and are
selectable by S2 position 8 The DSD clock mode,
256fs or 384fs is selectable by resistor stuffing option R19. The external mute circuitry is enabled by
setting S2 position 10 to closed.
6. AUTOMATIC MODE SWITCHING
The board features an automatic PCM or DSD input data switching mode for use with an external
SACD player. When used with an external SACD
player that has both a SPDIF output connected to
J1 (U5) and DSD data output connected to the JP1
port, will allow the board to switch automatically
between the two.
3
CDB4396/7
Theory of operation - When an SACD player
switches from playing a CD to a DSD disc, the SPDIF output data is disabled, the internal circuitry
(U6, U2, U3, U4, U7) detects loss of an SPDIF
source and automatically switches the Digital Data
Input path (U8) to the DSD input port JP1. This
feature can also be controlled from an external control signal by removing R60 and inputting a control
signal into JP2. Logic low = PCM mode, Logic
high = DSD mode. (For use only with the CS4397)
7. OUTPUT FILTER
The CDB4396C.0 output filter is a single op-amp
circuit that combines a balanced to single-ended
converter and 2-pole output filter. This topology
was chosen to demonstrate a low-cost design implementation, however, the trade-off is a slightly
compromised noise performance. Other output circuit topologies are available that optimize noise
and distortion but at a higher cost.
The circuit was designed such that the user can select between DC coupled or AC coupled modes. To
select AC coupling, remove Jumpers J2, J4, J5 and
J7. The board also allows the user to test other opamps by replacing the socketed op-amps with ones
of their choice. Also surface mount op-amps can be
tested by removing the socketed op-amps and soldering down the surface mount versions to SKT1X,
SKT3X or SKT2X. This may involve the need to
remove socket pins 2,3,4 on SKT1 and SKT3 and
pins 1,2,3 on SKT2 to get the IC body to mount
flush.
8. POWER SUPPLIES
The CDB4396C.0 comes supplied with an external
14 VAC Wall Mount power supply for convenience in setup, and to make measurements easier
by eliminating ground loop problems between lab
power supplies and measurement equipment. The
external 14 VAC voltage supplied at J11 is rectified, filtered and regulated to produce ±12 volts by
regulators U13 and U14. The CDB4396A.0 evalu-
4
ation board can also be powered by an external lab
power supply by connecting +12 vdc to connector
J8, and -12 vdc to connector J10. J9 is the Ground
connection. Up to ±13 volts is allowed before reverse voltage protection diodes D3 and D4 will
clamp the input voltage.
The CDB4396C.0 uses separate voltage regulation
for the digital control circuitry and for the digital
power section and analog section for the CS4396 CS4397. The digital power for the CS4396 CS4397 is user selectable by switch S2 position 9.
The (default) open position sets the voltage regulator VREG2 to +5.0 volts, the closed position sets
the voltage regulator to +3.3 volts.
9. GROUNDING AND POWER SUPPLY
DECOUPLING
For the user to be able to realize the high performance capabilities of the CS4396/7, it is recommended to pay careful attention to PC board layout,
grounding, and placement of the power supply and
decoupling capacitors. It is recommended when
doing the PC board layout to use one ground plane
underneath the part and for this ground plane to be
the analog ground plane. The digital ground pin
connection (pin 9) should tie to the analog ground
plane and to the digital ground plane. This should
be the “star” ground connection of the analog and
digital ground planes. Please review the attached
PC board photo plots for an example of the suggested grounding method.
It is also recommended to pay careful attention to
the placement of the decoupling capacitors tied to
VREF (pin 28). This pin requires a very low impedance path to ground at high frequencies as this
pin draws high frequency current pulses at 6 MHz.
It is important to place the .01 uF capacitor and
100 uF capacitor right next to the pin. Keep the
connecting trace as short as possible. A low ESR
electrolytic or tantalum for the 100 uF is recommended.
DS288DB1B1
CDB4396/7
10. CS4396/CS4397 MODE SETTINGS (SW2)
M4
M1
(DIF1)
0
0
1
1
0
0
0
0
M0
(DIF0)
0
1
0
1
DESCRIPTION
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Table 1. Single Speed (16 to 50 kHz) Digital Interface Format Options
M3
(DEM1)
0
0
1
1
M2
(DEM0)
0
1
0
1
DESCRIPTION
32 kHz De-Emphasis
44.1 kHz De-Emphasis
48 kHz De-Emphasis
De-Emphasis Disabled
Table 2. Single Speed (16 to 50 kHz) De-Emphasis Options
M4
1
1
1
1
M3
1
1
1
1
M2
1
1
1
1
M1
0
0
1
1
M0
0
1
0
1
DESCRIPTION
Left Justified up to 24-bit data, Format 0
I2S up to 24-bit data, Format 1
Right Justified 16-bit data, Format 2
Right Justified 24-bit data, Format 3
Table 3. Double Speed (50 to 100 kHz) Sample Rate Mode Options
M4
1
1
1
1
M3
1
1
1
1
M2
0
0
0
0
M1
0
0
1
1
M0
0
1
0
1
DESCRIPTION
Left Justified up to 24-bit data, Format 0
I2S up to 24-bit data, Format 1
Right Justified 16-bit data, Format 2
Right Justified 24-bit data, Format 3
Table 4. Quad Speed(100 to 200 kHz) Sample Rate Mode Options
M4
1
M3
0
M2
0
1
0
0
M1
0
(DIR)
0
(DIR)
M0
0
1
DESCRIPTION
Right Justified 20-bit data
Right Justified 24-bit data
Table 5. 8x Interpolated Input Mode Options (CS4397 only)
M4
1
M3
0
M2
1
1
0
1
M1
0
(DSD_R)
0
(DSD_R)
M0
0
1
DESCRIPTION
64x Oversampled DSD
128x Oversampled DSD
Table 6. Direct Stream Digital Options (CS4397 only)
DS288DB1B1
5
CDB4396/7
SWITCH S2
POSITION 1
MO - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK
POSITION 2
M1 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK
POSITION 3
M2 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK
POSITION 4
M3 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK
POSITION 5
M4 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK
POSITION 6
INT/EXT - SETS THE INPUT MUX TO THE CS8414 OR TO JP1 - OPEN=CS8414
POSITION 7 PCM/DSD-SETS THE BOARD TO AUTO MODE-SWITCHES BETWEEN PCM AND DSD-OPEN=DISABLED
POSITION 8
64/128X - SETS THE CLOCK MODE FOR DSD - OPEN =128X
POSITION 9
+3V/+5V - SETS THE DIGITAL POWER SUPPLY TO +3 OR +5 VOLTS - OPEN = +5V
POSITION 10
MUTE - ENABLES THE EXTERNAL MUTE CIRCUITRY - OPEN = DISABLED
DEFAULT
ALL SWITCHES IN OPEN POSITION
Table 7. SWITCH S2 MODE SETTINGS TABLE
- MODE TABLE AUTO SWITCHING
PCM
DSD
M0 = 1 M0 = 1
M1 = 0
M1=DSD_R
M2 = 1 M2 = 0
M3 = 1 M3 = 0
M4 = 0 M4 = 1
LRCLK = 0 = 256FS
LRCLK = 1 = 384FS
Table 8. AUTOMATIC MODE OPERATION SETTINGS
6
DS288DB1B1
DS288DB1B1
HDR1
SPDIF/DSD
+5V
VD+3/+5
VD+3/+5
VD+3/+5
1
2
VD+3/+5
1
.
.
C8
External Digital Audio IIs/DSD
HDR5X2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0-4
GND
R21
N.S.
R22
N.S.
R23
N.S.
R24
N.S.
U8
QS3384
(L=CONNECT)
5%
5%
5%
5%
5%
VD+3/+5
(L=PCM)
.
VCC
INT/EXT
U10
NC7SZ374
C22
VD+3/+5
.1UF
VD+3/+5
C21
.1UF
0805
+
5
1
2
3
.
3
.
4
VCC
2
R17
10K
RES_0603
5%
U11
0805
GND
-
2
3
5
.
GND
1K
M3
4 R5
RES_0805 5%
U4
NC7SZ125
+
.
-
1
.
/INT/EXT 2
1
1K
M4
4 R4
RES_0805 5%
U3
NC7SZ125
.
3
5
.
VCC
.
3
.
5
.
.
1
.
+
PCM/DSD
VD+3/+5
C5
.1UF
0805
20
19
18
17
16
15
14
13
12
11
R6
10K
RES_0603 5%
R9
10K
RES_0603 5%
R11
10K
RES_0603 5%
R12
10K
RES_0603 5%
R13
10K
RES_0603 5%
R15
10K
RES_0603 5%
R18
10K
RES_0603 5%
C6
10UF
CSP_3528
(DEFAULT = OPEN)
M0
M1
M2
M3
M4
INT/EXT
PCM/DSD
64/128X
+3V/+5V
+3V/+5V
/MUTE_CNTRL
IN2
GND
IN1
SEL
VCC
OUT
6
5
4
MCLK
2
B0
5
B1
6
B2
9
B3
10
B4
15
B5
16
B6
19
B7
20
B8
23
B9
13
B5-9
24
VCC
R20
N.S.
6
5
4
GND
PCM/DSD
S1
PTS645TL50
LRCLK SDATA
-
+
NC7SZ04
U9
(H=IN2)
64/128X
VD+3/+5
SEE NOTE #1
RES_0603
5%
C7
.1UF
0805
3
1
4
2
+5VA
C9
.01UF
CSN_0603
U1
M1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/RST
M4 (AD0/CS)
M3 (AD1/CDIN)
M2 (SCL/CCLK)
M0 (SDA/CDOUT)
DGND1
VDD1
VDD2
DGND2
MCLK
SCLK
LR(CLK MODE)
SDATA (DSD_L)
M1 (DSD_R)
VREF
FILT +
FILT CM OUT
AOUT L AOUT L+
VA
AGND1
AOUT R+
AOUT R AGND2
/MUTE C
C/H
/MUTE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C10
100UFSMT
25V
C11
.01UF
CSN_0603
C12
100UFSMT
25V
CM
AOUT_LEFTAOUT_LEFT+
C13
.01UF
C14
10UF
CSP_3528
AOUT_RIGHT+
AOUT_RIGHT/MUTE_CNTRL
+5VA
CS4397KS
VD+3/+5
L3
47UH
R25
1K
R26
1K
R27
1K
R28
1K
5%
5%
5%
5%
S3
PTS645TL50
DAC MUTE
VD+3/+5
R30 100
.1UF
0805
C18
10UF
C19
.01UF
3
1
4
2
/INT/EXT
+5VA
R29
10K
R31
10K
5%
/MUTE
5%
4
R71
1.0K
RES_0603
1%
R10 100
VD+3/+5
C17
GND
SCK
R70
1.0K
RES_0603
1%
DAC RESET
R7
10K
RES_0603
5%
Input Mux/Level Shifter
3
4
7
8
11
14
17
18
21
22
1
12
SDATA
LRCLK
SCK
MCLK
DSD_R
CP /OE
GND VCC
D
Q
.
5
R8 470 C4 .068UF
RES_0805 0805
5%
S2
1
2
3
4
VD+3/+5
5
6
7
8
9
/MUTE
10
R19
N.S.
RES_0805
5%
1
2
3
-
VD+3/+5
JP1
1
3
5
7
9
PCM/DSD
(L=ENABLE)
47UH
VD+3/+5
2
4
6
Input8
10
2
+5VA
CS8414-CS
(DSD CLK MODE)
LOW = 256fs
HIGH = 384fs
U7
NC7SZ125
VCC
1K
M1
4 R3
RES_0805 5%
U2
NC7SZ125
+
L2
2
.01UF
R16
0805
75
RES_0805
5%
GND
-
+5V
ON
J1
SPDIF IN
2
C20
.1UF
0805
5%
C15
C16
.01UF 10UF
CSP_3528
2
C3
.1UF
0805
PCM/DSD
VCC
1K INT/EXT
4 R2
RES_0805 5%
1
Q1
MMBT2907A L
3
.01UF
0805
6
5
4
2
CASE2
CASE1
GND2
GND1
+5V
1
+
5
OUT
SPDIF IN
GREEN LED
SPDIF ENABLED
28
C
ERR
27
CD/F1
CE/F2
26
CC/F0
SDATA
25
CB/E2
ERF
24
CA/E1
M1
23
/C0/E0
M0
22
VDD
VA+
21
DGND
AGND
20
RXP
FILT
19
RXN
MCK
18
FSYNC
M2
17
SCK
M3
16
CS12/FCK
SEL
15
U
CBL
3
C2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R60
0
RES_0805
5%
D1
U6
GND
5
.1UF
0805
-
1
RESET PIN?
C1
3
2
5
VCC
(L=PCM)
.
U5
TORX173
VCC
.
R1
560
RES_0805
5%
47UH
3
+5V
L1
MUT E
R33
10K
RES_0603
5%
- MODE TABLE AUTO SW ITCHING
NOTE 1: USE THESE RESISTORS FI USING
PCM AND DSD MODES
-12V
DSD
PCM
NC7SZ157
U12
NC7SZ04
C23
.1UF
0805
=
=
=
=
=
1
0
1
1
0
Figure 1. System Schematic
M0 = 1
M1 = DSD_R
M2 = 1
M3 = 0
M4 = 1
lrclk = 0 = 256fs
lrclk = 1 = 384fs
7
CDB4396/7
M0
M1
M2
M3
M4
8
R34
1K
R35
N.S.
OS 1
RN55
1%
2
C32
5600PF
R43
1K
RN55
1%
C30
.1UF
C33
1500PF
0805
MUTE
MUT E
OS 1
RN55
1%
R42
1K
0805
5%
-12V
.
1
Q2
2SC3 326
OS 1
LL+
-12V
C31
5600PF
SKT1X
1
1
2
2
3
3
4
4
8
7
6
5
8
7 +12V
6L_OU T
5 OS 2
DUAL_FTPRN T
‘
‘
1
100UF 25V
J3
2
.
3
AOUT_L EFT+
R39
560
~
1
RN55
1%
SKT1
LT1028
6
2
SINGLE AND DUAL OP-AMPS
ARE SUPPORTED
0805
1%
3
RN55
1%
7
5
R40
1K
RN55
1%
C28
470PF
R41
499
C27
5600PF
0805
4
1
8
C29
RN55
1%
+12V
OS 2
AOUT_LE FT100UF
25V
OS 2
C25
.1UF
R38
499
NOTE:
THE FILTER OP-AMPS ARE DUAL
FOOTPRINT - DIP8 AND SO-8
-12V
R36
N.S.
2
‘
R37
1K
C26
0805
1%
1500PF
C24
2
1
‘
J2
JUMPER
C34 .1UF
J4
JUMPER
SKT2X
L_O UT
LL+
-12V
1
2
3
4
L_OU T1
L2
L+
3
-12V 4
0805
SKT2
1
2
3
4
8
7
6
5
8
7
6
5
C35
+12V
R_OUT
RR+
1
2
3
4
8
7
6
5
+12V
8
7 R_OUT
R6
R+
5
DUAL_FTPRN T
SKT
SKT3X
.1UF
0805
R44
1K
2
1
R53
1K
RN55
1%
RN55
1%
6
MUTE
C42
.1UF
OS 3
C45
1500PF
0805
J6
1%
RN55
2
1
-12V
R52
1K
0805
5%
.
.
~
3
1
R49
560
2
R51
499
C44
5600PF
0805
1%
SKT3
LT1028
Q3
2SC3326
C43
5600PF
‘
RN55
1%
R46
N.S.
OS 4
3
RN55
1%
AOUT_RIG HT+
100UF 25V
8
+12V
7
6 R_OUT
OS 4
5
2
C40
470PF
0805
7
5
C39
5600PF
1500PF
C37
.1UF +12V
4
1
8
RN55
1%
R50
1K
C41
8
7
6
5
DUAL_FTPRN T
0805
1%
OS 4
AOUT_RIGHT 100UF 25V
1
2
3
4
OS 3
‘
‘
1
2
R48
499
R47
1K
C38
1
2
3
4
-12V
C36
‘
R45
N.S.
RN55
1%
J5
JUMPER
OS 3
RR+
-12V
J7
JUMPER
DS288DB1B1
DC OFFSET CAN BE ADJUSTED FOR BY ADDING
RESISTORS R35, R36 AND R45, R46
Figure 2. Output Stage Schematic
CDB4396/7
NOTE:
THE CIRCUIT IS SHOWN DC COUPLED.
TO MAKE AC COUPLED -REMOVE JUMPERS J2, J4, J5, J7
2
4
3
ADJ
+12V
VD+3/+5
+5VA
-12V
D4
1
P6K E13
2
4
3
1
D3
2
+12V
1
1
1
+12V
VREG 1
LT1117
SO T223
ADJ
VREG 2
LT1117
SO T223
-12VDC
OUT
TAB
IN
J10
GND
1
J9
OUT
TAB
IN
DS288DB1B1
J8
+12VDC
2
1
R55
TB D
R56
330
5%
1%
C46
47UF
25V
R57
110
1%
C49
10UF
CSP_ 3528
C50
10UF
CSP_ 3528
P6K E13
C52
100UF
25V
C53
100UF
25V
+3V/+5V
R59
330
C51
RES_ 0805 47UF
1%
25V
R54
110
1%
C47
10UF
CSP_3 528
R58
560
RES_0 805 5%
C48
10UF
CSP_ 3528
D2
GREEN LED
POWE R
+3V/+5V
U13
LM 317T
+12V
+5V
+20V
3
2
1
2 1
J11
D6
K
+12V
1N4003T
C55
4700UF
25V
1
POWERJAC
ADJ
3
2
1
VIN
VOUT
C54
4700UF
25V
1
1N4003T
ADJ
2
D5
OUT
TAB
IN
VREG 3
LT1117
SO T223
CDB4396/7
2
4
3
+20V
R63
953
1%
C56
47UF
25V
R61
110
1%
R66
R65
330
110
C62
RES_0 80510UF
1%
1%
CSP_3 528
C60
10UF
CSP_3 528
C61
10UF
CSP_3 528
C57
10UF
CSP_ 3528
-20V
VIN
VOUT
3
2
1
ADJ
U14
LM 337T
-12V
-20V
R64
953
1%
Figure 3. Power Supply
R62
110
1%
C59
10UF
CSP_3 528
9
CDB4396/7
C58
47UF
25V
10
CDB4396/7
DS288DB1B1
Figure 4. Component Placement
DS288DB1B1
11
CDB4396/7
Figure 5. Top - Layer 1
Figure 6. Layer 2
CDB4396/7
12
DS288DB1B1
Figure 7. Layer 3
CDB4396/7
DS288DB1B1
13
Figure 8. Layer 4
CDB4396/7
14
DS288DB1B1
• Notes •