Lecture #39
ANNOUNCEMENTS
• Pick up graded HW assignments and exams (278 Cory)
• Lecture #40 will be the last formal lecture. Class on Friday
will be dedicated to a course review (with sample problems).
• Discussion sections this week will cover sample problems
(review for the final exam)
• Deadline for “Best Tutebot” contest: 12/4 at 8 PM.
• Prof. King will hold extra office hours this Thursday afternoon
OUTLINE
» Transistor scaling
» Silicon-on-Insulator technology
» Interconnect scaling
Reading (Rabaey et al.): Sections 2.5.1, 3.5, 5.6
EECS40, Fall 2003
Lecture 39, Slide 1
Prof. King
Transistor Scaling
Average minimum L of MOSFETs vs. time
• Steady advances in
manufacturing technology
(particularly lithography)
have allowed for a steady
reduction in transistor size.
~13% reduction/year
(0.5× every 5 years)
• How should transistor
dimensions and supply
voltage (VDD) scale
together?
EECS40, Fall 2003
Lecture 39, Slide 2
Prof. King
1
Scenario #1: Constant-Field Scaling
• Voltages and MOSFET dimensions are scaled
by the same factor S >1, so that the electric
field remains unchanged
xj
VDD
tox / S
xj / S
VDD / S
L/S
Doping NA
NA × S
S ≅ 1.4
EECS40, Fall 2003
Lecture 39, Slide 3
Prof. King
Impact of Constant-Field Scaling
(a) MOSFET gate capacitance:


L  W   ε ox  Cgate

′ = L′W ′Cox
′ =    ⋅ 
Cgate
=
S
 S  S   tox 
S


(b) MOSFET drive current:
 W  V −V 2 I
W′
2
′ ∝ Cox
′
′ − VT′ ) ≅ (SCox ) S  DD T  ∝ DSAT
(VDD
I DSAT
 L  S 
L′
S
 S
(c) Intrinsic gate delay :
′ VDD
′
(Cgate / S )(VDD / S ) =  CgateVDD  • 1
Cgate
=
 I

′
(I DSAT / S )
I DSAT
 DSAT  S
9 Circuit speed improves by S
EECS40, Fall 2003
Lecture 39, Slide 4
Prof. King
2
Impact of Constant-Field Scaling (cont’d)
(d) Device density:
area required per transistor ∝ W ′L′
# of transistors per unit area ∝
S2
1
1
=
=
W ′L′ (W / S )(L / S ) WL
(e) Power dissipated per device:
I
 V  P
′ = I DSAT
′ ⋅VDD
′ =  DSAT  ⋅  DD  = peak
Ppeak
2
 S  S  S
(f) Power density:
′ ⋅
Ppeak
 Ppeak
1 Ppeak 
1
=
= 2 ⋅ 
W′L′ S  (W / S )(L / S )  WL
9 Power consumed per function is reduced by S2
EECS40, Fall 2003
Lecture 39, Slide 5
Prof. King
VT Scaling
• Low VT is desirable for high ON current:
IDSAT ∝ (VDD - VT)η
1<η<2
• But high VT is needed for low OFF current:
log IDS
Low VT
High VT
IOFF,low VT
IOFF,high VT
0
EECS40, Fall 2003
Lecture 39, Slide 6
VT cannot be
aggressively
scaled down!
VGS
Prof. King
3
• Since VT cannot be scaled down aggressively,
the power-supply voltage (VDD) has not been
scaled down in proportion to the MOSFET
channel length:
EECS40, Fall 2003
Lecture 39, Slide 7
Prof. King
Scenario #2: Generalized Scaling
• MOSFET dimensions are scaled by a factor S >1;
Voltages (VDD & VT) are scaled by a factor U >1
L′ = L / S ; W′ = W / S ; t′ox = tox / S
V′DD = VDD / U
Note: U is slightly smaller than S
(a) MOSFET drive current:
 W  V − V 2 SI
W′
′ ∝ Cox
′
′ − VT′ )2 ≅ (SCox ) S  DD T  ∝ DSAT
(VDD
I DSAT
 L  U 
L′
U2
 S
(b) Intrinsic gate delay:
′ VDD
′
(Cgate / S )(VDD / U ) =  CgateVDD  • U
Cgate
=
 I
 2
′
I DSAT
SIDSAT / U 2
 DSAT  S
(
EECS40, Fall 2003
)
Lecture 39, Slide 8
Prof. King
4
Impact of Generalized Scaling
(c) Power dissipated per device:
 SI
  VDD  SPpeak
′ = I DSAT
′ ⋅VDD
′ =  DSAT
Ppeak
⋅
=
2  
3
 U  U  U
(d) Power dissipated per unit area:
′ ⋅
Ppeak
 S 3 Ppeak Ppeak
1 SPpeak 
1

=
=
⋅
>
W′L′ U 3  (W / S )(L / S )  U 3 WL WL
• Reliability (due to high E-fields) and power density are issues!
EECS40, Fall 2003
Lecture 39, Slide 9
Prof. King
Intrinsic Gate Delay (CgateVDD / IDSAT)
0.85V
VDD=0.75V
EECS40, Fall 2003
Lecture 39, Slide 10
Prof. King
5
Silicon-on-Insulator (SOI) Technology
TSOI
• Transistors are fabricated in a thin single-crystal Si layer
on top of an electrically insulating layer of SiO2
9
9
9
8
Simpler device isolation Æ savings in circuit layout area
Low pn-junction & wire capacitances Æ faster circuit operation
No “body effect”
Higher cost
EECS40, Fall 2003
Lecture 39, Slide 11
Prof. King
Interconnect Scaling
Relevant parameters:
• wire width W
• wire length L
• wire thickness H
• wire resistivity ρ
• wire-to-wire spacing Z
• inter-level dielectric (ILD)
• thickness tILD
• permittivity εILD
Z
L
ρ
W
EECS40, Fall 2003
Lecture 39, Slide 12
H
ρ
tILD
Prof. King
6
For “local” (relatively short) interconnects:
• W, Z and tILD scale down by S
• H is not scaled
– avoids significantly increasing Rwire, but increases crosstalk
• L scales down by a factor SL ≤ S
Wire capacitance scales by a factor εc / SL , where εc
accounts for the impact of fringing & interwire capacitances
For short & medium-length wires, the resistance of the
driving logic gate dominates the wire resistance
(i.e. Rdr >> Rwire), so that the wire delay scales by εc / SL
EECS40, Fall 2003
Lecture 39, Slide 13
Prof. King
Global Interconnects
• For global interconnects (long wires used to route VDD,
GND, and voltage signals across a chip), the wire resistance
dominates the resistance of the driving logic gate
(i.e. Rwire >> Rdr)
Æ RwireCwire ∝ L2
• The length of the longest wires on a chip increases slightly
(~20%) with each new technology generation. In order to
minimize increases in global interconnect delay, the crosssectional area of global interconnects has not been scaled,
i.e. W and H are not scaled down for global interconnects
=> Place global interconnects in separate planes of wiring
EECS40, Fall 2003
Lecture 39, Slide 14
Prof. King
7
Interconnect Technology Trends
• Reduce the inter-layer dielectric permittivity
– “low-k” dielectrics (εr ≅ 2)
• Use more layers of wiring
− average wire length is reduced
− chip area is reduced
wire delay
increases
gate delay
Intel 0.13µm Process (Cu)
Source: Intel Technical Journal 2Q02
EECS40, Fall 2003
Lecture 39, Slide 15
Prof. King
8