TS4984
2 x 1W Stereo audio power amplifier
with active low standby mode
■
Operating from VCC=2.2V to 5.5V
■
1W output power per channel @ VCC=5V,
THD+N=1%, RL=8Ω
10nA standby current
62dB PSRR @ 217Hz with grounded inputs
High SNR: 100dB(A) typ.
Near-zero pop & click
Available in QFN16 4x4 mm, 0.5mm pitch,
leadfree package
■
■
■
■
■
Pin Connections (top view)
TS4984IQ — TQFN16 4x4mm
Description
The TS4984 has been designed for top of the
class stereo audio applications. Thanks to its
compact and power dissipation efficient QFN
package, it suits various applications.
VO-L VO+L VCC1 VCC2
16 15
With a BTL configuration, this Audio Power
Amplifier is capable of delivering 1W per channel
of continuous RMS output power into an 8Ω load
@ 5V.
IN- L
IN+ L
14
13
1
12
STBY
2
11
BYPASS R
BYPASS L
3
10
IN+ R
NC
4
9
IN- R
An externally controlled standby mode control
reduces the supply current to less than 10nA per
channel. The device also features an internal
thermal shutdown protection.
5
6
7
8
GND1 GND2 VO+R VO-R
The gain of each channel can be configured by
external gain setting resistors.
Applications
■
■
Cellular mobile phones
Notebook computers & PDAs
■
■
LCD monitors & TVs
Portable audio devices
Order Codes
Part Number
Temperature Range
Package
Packaging
Marking
TS4984IQT
-40, +85°C
QFN
Tape & Reel
K984
January 2005
Revision 1
1/29
TS4984
1
Typical Application
Typical Application
Figure 1 shows a schematic view of a typical audio amplification application using the TS4984. Table 1
describes the components used in this typical application.
Figure 1: Typical application schematic
Cfeed-L
Rfeed-L
22k
+
VCC
13
14
Cs
1u
Cin-L
Rin-L
GND
100n
1
IN-L
-
2
IN+L
+
VCC2
Input L
VCC1
U1
22k
VO-L
16
VO+L
15
VO-R
8
VO+R
7
VCC
1
2
3
12
Standby
3
Bypass L
Bias
AV = -1
Neg. Output L
Pos. Output L
+
+
Cb
1u
Wire optional
Internal connection
Cin-R
Rin-R
Input R
GND
100n
10
IN+R
+
9
IN-R
-
22k
AV = -1
Bypass R
Neg. Output R
Pos. Output R
GND1
GND2
6
+
5
11
TS4984
Cfeed-R
Rfeed-R
22k
Table 1: External component descriptions
Components
RIN L,R
Inverting input resistors which sets the closed loop gain in conjunction with Rfeed. These resistors
also form a high pass filter with CIN (fc = 1 / (2 x Pi x RIN x CIN)).
CIN L,R
Input coupling capacitors which blocks the DC voltage at the amplifier input terminal.
RFEED L,R
Feedback resistors which sets the closed loop gain in conjunction with RIN.
CS
Supply Bypass capacitor which provides power supply filtering.
CB
Bypass pin capacitor which provides half supply filtering.
AV L, R
2/29
Functional Description
Closed loop gain in BTL configuration = 2 x (RFEED / RIN) on each channel.
Absolute maximum ratings and operating conditions
2
TS4984
Absolute maximum ratings and operating conditions
Table 2: Key parameters and their absolute maximum ratings
Symbol
VCC
Vi
Parameter
Supply voltage 1
2
Value
Unit
6
V
Input Voltage
Operating Free Air Temperature Range
GND to VCC
V
Toper
-40 to + 85
°C
Tstg
Storage Temperature
-65 to +150
°C
Maximum Junction Temperature
150
°C
120
Pd
Thermal Resistance Junction to Ambient
QFN16
Power Dissipation
Internally Limited
ESD
3
2
kV
200
200mA
V
Tj
Rthja
ESD
Human Body Model
Machine Model
Latch-up Immunity
°C/W
1) All voltages values are measured with respect to the ground pin
2) The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V
3) The voltage value is measured with respect from pin to supply
Table 3: Operating conditions
Symbol
Parameter
VCC
Supply Voltage
VICM
Common Mode Input Voltage Range
VSTB
Standby Voltage Input:
Device ON
Device OFF
RL
Load Resistor
RTHJA
Unit
V
1.2V to VCC
V
1.35 ≤ VSTB ≤ VCC
GND ≤ VSTB ≤ 0.4
V
≥4
Ω
≥1
MΩ
Thermal Shutdown Temperature
150
°C
Thermal Resistance Junction to Ambient
QFN161
QFN162
45
85
°C/W
ROUTGND Resistor Output to GND (VSTB = GND)
TSD
Value
2.2 to 5.5
1) When mounted on a 4-layer PCB with via
2) When mounted on a 2 layer PCB
3/29
TS4984
3
Electrical characteristics
Electrical characteristics
Table 4: Electrical characteristics for VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
ICC
ISTANDBY
Parameter
Supply Current
No input signal, no load
Standby Current 1
No input signal, Vstdby = GND, RL = 8Ω
Voo
Output Offset Voltage
No input signal, RL = 8Ω
Pout
Output Power
THD = 1% Max, F = 1kHz, RL = 8Ω
THD + N
PSRR
Min.
0.8
Total Harmonic Distortion + Noise
Po = 1Wrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω
Power Supply Rejection Ratio2
RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded
F = 217Hz
F = 1kHz
55
55
Typ.
Max.
7.4
12
10
1000
1
10
mA
nA
mV
1
W
0.2
%
dB
62
64
Channel Separation, RL = 8Ω
F = 1kHz
F = 20Hz to 20kHz
-92
-70
TWU
Wake-Up Time (Cb = 1µF)
90
TSTDB
Standby Time (Cb = 1µF)
10
Crosstalk
Unit
dB
130
ms
µs
VSTDBH
Standby Voltage Level High
1.3
V
VSTDBL
Standby Voltage Level Low
0.4
V
ΦM
Phase Margin at Unity Gain
RL = 8Ω, CL = 500pF
65
Degrees
GM
Gain Margin
RL = 8Ω, CL = 500pF
15
dB
GBP
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
1) Standby mode is activated when Vstdby is tied to Gnd.
2) All PSRR data limits are guaranteed by production sampling tests
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
4/29
Electrical characteristics
TS4984
Table 5: Electrical characteristics for VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
ICC
ISTANDBY
Parameter
Min.
Supply Current
No input signal, no load
Standby Current 1
No input signal, Vstdby = GND, RL = 8Ω
Voo
Output Offset Voltage
No input signal, RL = 8Ω
Pout
Output Power
THD = 1% Max, F = 1kHz, RL = 8Ω
THD + N
Total Harmonic Distortion + Noise
Po = 400mWrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω
PSRR
Power Supply Rejection Ratio2
RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded
F = 217Hz
F = 1kHz
300
55
55
Typ.
Max.
6.6
12
10
1000
1
10
mA
nA
mV
450
mW
0.1
%
dB
61
63
Channel Separation, RL = 8Ω
F = 1kHz
F = 20Hz to 20kHz
-94
-68
TWU
Wake-Up Time (Cb = 1µF)
110
TSTDB
Standby Time (Cb = 1µF)
10
Crosstalk
Unit
dB
140
ms
µs
VSTDBH
Standby Voltage Level High
1.2
V
VSTDBL
Standby Voltage Level Low
0.4
V
ΦM
Phase Margin at Unity Gain
RL = 8Ω, CL = 500pF
65
Degrees
GM
Gain Margin
RL = 8Ω, CL = 500pF
15
dB
GBP
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
1) Standby mode is activated when Vstdby is tied to Gnd
2) All PSRR data limits are guaranteed by production sampling tests
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
5/29
TS4984
Electrical characteristics
Table 6: Electrical characteristics for VCC = +2.6V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
ICC
ISTANDBY
Parameter
Min.
Supply Current
No input signal, no load
Standby Current 1
No input signal, Vstdby = GND, RL = 8Ω
Voo
Output Offset Voltage
No input signal, RL = 8Ω
Pout
Output Power
THD = 1% Max, F = 1kHz, RL = 8Ω
THD + N
Total Harmonic Distortion + Noise
Po = 200mWrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω
PSRR
Power Supply Rejection Ratio2
RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded
F = 217Hz
F = 1kHz
200
55
55
Typ.
Max.
6.2
12
10
1000
1
10
mA
nA
mV
250
mW
0.1
%
dB
60
62
Channel Separation, RL = 8Ω
F = 1kHz
F = 20Hz to 20kHz
-95
-68
TWU
Wake-Up Time (Cb = 1µF)
125
TSTDB
Standby Time (Cb = 1µF)
10
Crosstalk
Unit
dB
150
ms
µs
VSTDBH
Standby Voltage Level High
1.2
V
VSTDBL
Standby Voltage Level Low
0.4
V
ΦM
Phase Margin at Unity Gain
RL = 8Ω, CL = 500pF
65
Degrees
GM
Gain Margin
RL = 8Ω, CL = 500pF
15
dB
GBP
Gain Bandwidth Product
RL = 8Ω
1.5
MHz
1) Standby mode is activated when Vstdby is tied to Gnd
2) All PSRR data limits are guaranteed by production sampling tests
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
6/29
Electrical characteristics
TS4984
Figure 5: Open loop frequency response
Figure 2: Open loop frequency response
0
60
Gain
40
80
-120
-20
-80
40
Phase
20
Phase (°)
Gain (dB)
-80
-60
0.1
-40
60
Phase
0
-40
Gain
-40
Phase (°)
Gain (dB)
20
0
100
-120
0
Vcc = 5V
RL = 8Ω
Tamb = 25°C
1
-160
-20
10
100
1000
-200
10000
-40
0.1
-160
Vcc = 5V
CL = 560pF
Tamb = 25°C
1
10
Frequency (kHz)
100
1000
-200
10000
Frequency (kHz)
Figure 6: Open loop frequency response
Figure 3: Open loop frequency response
0
60
0
100
Gain
80
40
-120
-20
-80
40
Phase
20
Phase (°)
Gain (dB)
-80
Phase (°)
Gain (dB)
Phase
0
-60
0.1
-40
60
20
-40
Gain
-40
-120
0
-160
Vcc = 3.3V
RL = 8Ω
Tamb = 25°C
1
-20
10
100
1000
-200
10000
-40
0.1
-160
Vcc = 3.3V
CL = 560pF
Tamb = 25°C
1
10
Frequency (kHz)
100
1000
-200
10000
Frequency (kHz)
Figure 7: Open loop frequency response
Figure 4: Open loop frequency response
0
60
0
100
Gain
80
40
-120
-20
-80
40
Phase
20
Phase (°)
Gain (dB)
-80
Phase (°)
Gain (dB)
Phase
0
-60
0.1
-40
60
20
-40
Gain
-40
-120
0
-160
Vcc = 2.6V
RL = 8Ω
Tamb = 25°C
1
-20
10
100
Frequency (kHz)
1000
-200
10000
-40
0.1
-160
Vcc = 2.6V
CL = 560pF
Tamb = 25°C
1
10
100
1000
-200
10000
Frequency (kHz)
7/29
TS4984
Electrical characteristics
Figure 8: Power supply rejection ratio (PSRR)
vs. frequency
Figure 11: Power supply rejection ratio (PSRR)
vs. frequency
0
PSRR (dB)
-20
-30
-40
-10
Vcc :
2.2V
2.6V
3.3V
5V
PSRR (dB)
-10
0
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = Cin = 1µF
RL >= 4Ω
Tamb = 25°C
100
1000
10000
Frequency (Hz)
-60
100000
Figure 9: Power supply rejection ratio (PSRR)
vs. frequency
1000
10000
Frequency (Hz)
100000
0
Vripple = 200mVpp
Av = 5
Input = Grounded
Cb = Cin = 1µF
RL >= 4Ω
Tamb = 25°C
-10
Vcc :
2.2V
2.6V
3.3V
5V
-20
PSRR (dB)
PSRR (dB)
100
Figure 12: Power supply rejection ratio
(PSRR) vs. frequency
0
-20
Vcc = 5, 3.3, 2.5 & 2.2V
-50
-60
-10
-30
-40
-50
-70
-20
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = 0.1µF, Cin = 1µF
RL >= 4Ω
Tamb = 25°C
-30
-40
-30
Vripple = 200mVpp
Rfeed = 22kΩ
Input = Floating
Cb = 1µF
RL >= 4Ω
Tamb = 25°C
Vcc = 2.2, 2.6, 3.3, 5V
-40
-50
-60
-50
-60
-70
100
1000
10000
Frequency (Hz)
-80
100000
-10
Vcc :
2.2V
2.6V
3.3V
5V
-20
PSRR (dB)
PSRR (dB)
Vripple = 200mVpp
Av = 10
Input = Grounded
Cb = Cin = 1µF
RL >= 4Ω
Tamb = 25°C
-30
-40
-30
Vripple = 200mVpp
Rfeed = 22kΩ
Input = Floating
Cb = 0.1µF
RL >= 4Ω
Tamb = 25°C
Vcc = 2.2, 2.6, 3.3, 5V
-40
-50
-60
-70
-50
100
8/29
100000
0
0
-20
1000
10000
Frequency (Hz)
Figure 13: Power supply rejection ratio
(PSRR) vs. frequency
Figure 10: Power supply rejection ratio
(PSRR) vs. frequency
-10
100
1000
10000
Frequency (Hz)
100000
-80
100
1000
10000
Frequency (Hz)
100000
Electrical characteristics
TS4984
Figure 17: Power supply rejection ratio
(PSRR) vs. DC output voltage
Figure 14: Power supply rejection ratio
(PSRR) vs. DC output voltage
0
0
Vcc = 5V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 2
Tamb = 25°C
PSRR (dB)
-20
-30
-10
-20
PSRR (dB)
-10
-40
-50
-60
-60
-4
-3
-2
-1
0
1
2
3
Differential DC Output Voltage (V)
4
-70
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
5
Differential DC Output Voltage (V)
Figure 18: Power supply rejection ratio
(PSRR) vs. DC output voltage
Figure 15: Power supply rejection ratio
(PSRR) vs. DC output voltage
0
0
Vcc = 5V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 5
Tamb = 25°C
-20
-10
PSRR (dB)
-10
PSRR (dB)
-40
-50
-70
-5
-30
-20
-40
-50
-50
-4
-3
-2
-1
0
1
2
3
Differential DC Output Voltage (V)
4
-60
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
5
Differential DC Output Voltage (V)
Figure 19: Power supply rejection ratio
(PSRR) vs. DC output voltage
Figure 16: Power supply rejection ratio
(PSRR) vs. DC output voltage
0
0
Vcc = 5V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
-20
-10
PSRR (dB)
-10
-30
-20
Vcc = 3.3V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
-30
-40
-40
-50
-5
Vcc = 3.3V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 5
Tamb = 25°C
-30
-40
-60
-5
PSRR (dB)
-30
Vcc = 3.3V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 2
Tamb = 25°C
-4
-3
-2
-1
0
1
2
3
Differential DC Output Voltage (V)
4
5
-50
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Differential DC Output Voltage (V)
9/29
TS4984
Electrical characteristics
Figure 20: Power supply rejection ratio
(PSRR) vs. DC output voltage
Figure 23: Power supply rejection ratio
(PSRR) at f=217Hz vs. bypass
capacitor
0
PSRR (dB)
-20
-30
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 2
Tamb = 25°C
Av=10
Vcc:
2.6V
3.3V
5V
-30
PSRR at 217Hz (dB)
-10
-40
-50
-40
-50
-60
-70
Av=2
Vcc:
2.6V
3.3V
5V
Av=5
Vcc:
2.6V
3.3V
5V
-60
-70
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
2.5
1
Bypass Capacitor Cb ( F)
Differential DC Output Voltage (V)
Figure 21: Power supply rejection ratio
(PSRR) vs. DC output voltage
Figure 24: Output power vs. power supply
voltage
0
-20
2.00
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 5
Tamb = 25°C
RL = 4Ω
1.75 F = 1kHz
BW < 125kHz
1.50 Tamb = 25°C
THD+N=10%
1.25
Pout (W)
PSRR (dB)
-10
Tamb=25°C
-80
0.1
-30
-40
1.00
0.75
0.50
-50
THD+N=1%
0.25
-60
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
0.00
2.5
2.5
3.0
3.5
Differential DC Output Voltage (V)
Figure 22: Power supply rejection ratio
(PSRR) vs. DC output voltage
5.0
5.5
1.75
Vcc = 2.6V
Vripple = 200mVpp
RL = 8Ω
Cb = 1µF
AV = 10
Tamb = 25°C
RL = 8Ω
1.50 F = 1kHz
BW < 125kHz
1.25 Tamb = 25°C
Pout (W)
PSRR (dB)
-20
4.5
Figure 25: Output power vs. power supply
voltage
0
-10
4.0
Vcc (V)
-30
THD+N=10%
1.00
0.75
0.50
-40
THD+N=1%
0.25
-50
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
Differential DC Output Voltage (V)
10/29
2.0
2.5
0.00
2.5
3.0
3.5
4.0
Vcc (V)
4.5
5.0
5.5
Electrical characteristics
TS4984
Figure 29: Output power vs. load resistor
Figure 26: Output power vs. power supply
voltage
0.7
1.0
RL = 16Ω
F = 1kHz
0.8 BW < 125kHz
Tamb = 25°C
0.7
THD+N=10%
THD+N=10%
0.5
0.6
0.5
0.4
0.3
0.4
0.3
THD+N=1%
0.2
0.2
2.5
3.0
3.5
4.0
Vcc (V)
4.5
5.0
0.0
5.5
0.55 RL = 32Ω
F = 1kHz
0.50
BW < 125kHz
0.45 Tamb = 25°C
0.40
12
16
20
Load resistance
24
28
32
THD+N=10%
0.30
0.25
0.35
0.30
0.25
0.20
0.15
0.20
0.15
0.10
THD+N=1%
0.10
THD+N=1%
0.05
0.05
0.00
2.5
3.0
3.5
4.0
Vcc (V)
4.5
5.0
5.5
0.00
THD+N=10%
1.25
Vcc = 5V
F = 1kHz
BW < 125kHz
Tamb = 25°C
1.00
0.75
0.50
THD+N=1%
4
8
Power Dissipation (W)
1.75
1.50
4
16
20
24
Load Resistance (W)
28
12
16
20
Load resistance
24
28
32
Vcc=5V
2.4 F=1kHz
THD+N<1%
2.0
RL=4Ω
1.6
1.2
32
RL=8Ω
0.8
0.4
12
8
Figure 31: Power dissipation vs. output power
Figure 28: Output power vs. load resistor
0.25
Vcc = 2.6V
F = 1kHz
BW < 125kHz
Tamb = 25°C
0.35
THD+N=10%
Pout (W)
Pout (W)
8
0.40
0.60
Pout (W)
4
Figure 30: Output power vs. load resistor
Figure 27: Output power vs. power supply
voltage
0.00
THD+N=1%
0.1
0.1
0.0
Vcc = 3.3V
F = 1kHz
BW < 125kHz
Tamb = 25°C
0.6
Pout (W)
Pout (W)
0.9
0.0
0.0
RL=16Ω
0.2
0.4
0.6
0.8
1.0
Output Power (W)
1.2
11/29
TS4984
Electrical characteristics
Figure 32: Power dissipation vs. output power
Figure 35: Clipping voltage vs. power supply
voltage and load resistor
0.9
Vcc=3.3V
F=1kHz
1.0 THD+N<1%
Tamb = 25 C
0.8
Vout1 & Vout2
Clipping Voltage Low side (V)
Power Dissipation (W)
1.2
RL=4Ω
0.6
RL=8Ω
0.4
0.2
0.7
0.5
RL = 8Ω
0.4
0.3
0.2
0.0
0.1
RL = 4Ω
0.6
0.1
RL=16Ω
0.0
0.0
0.8
0.2
0.3
0.4
Output Power (W)
0.5
0.6
Figure 33: Power dissipation vs. output power
RL = 16Ω
2.5
3.0
3.5
Vcc (V)
4.0
4.5
5.0
Figure 36: Current consumption vs. power
supply voltage
Power Dissipation (W)
0.7
Vcc=2.6V
0.6 F=1kHz
THD+N<1%
No Loads
Tamb=25°C
0.5
RL=4Ω
0.4
0.3
RL=8Ω
0.2
0.1
0.0
0.00
RL=16Ω
0.04
0.08
0.12
0.16
0.20
0.24
Output Power (W)
0.28
Figure 34: Clipping voltage vs. power supply
voltage and load resistor
Figure 37: Current consumption vs. standby
voltage at Vcc=5V
1.0
Vout1 & Vout2
Clipping Voltage High side (V)
Tamb = 25 C
0.9
RL = 4Ω
0.8
0.7
0.6
RL = 8Ω
0.5
0.4
RL = 16Ω
0.3
Vcc = 5V
No Loads
Tamb=25°C
0.2
2.5
12/29
3.0
3.5
Vcc (V)
4.0
4.5
5.0
Electrical characteristics
TS4984
Figure 38: Current consumption vs. standby
voltage at Vcc=3.3V
Figure 41: THD+N vs. output power
10
THD+N (%)
1
Vcc = 3.3V
No Loads
Tamb=25°C
RL = 4Ω
F = 20Hz
Av = 2
Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc=2.2V
Vcc=2.6V
Vcc=3.3V
0.1
Vcc=5V
0.01
1E−3
0.01
0.1
1
Pout (W)
Figure 39: Current consumption vs. standby
voltage at Vcc=2.6V
Figure 42: THD+N vs. output power
10
THD+N (%)
1
RL = 8Ω
F = 20Hz
Av = 2
Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc=2.2V
Vcc=2.6V
Vcc=3.3V
0.1
Vcc=5V
0.01
Vcc = 2.6V
No Loads
Tamb=25°C
1E−3
1E−3
0.01
0.1
1
Pout (W)
Figure 40: Current consumption vs. standby
voltage at Vcc=2.2V
Figure 43: THD+N vs. output power
10
THD+N (%)
1
RL = 16Ω
F = 20Hz
Av = 2
Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc=2.2V
Vcc=2.6V
Vcc=3.3V
0.1
Vcc=5V
0.01
Vcc = 2.2V
No Loads
Tamb=25°C
1E−3
1E−3
0.01
0.1
1
Pout (W)
13/29
TS4984
Electrical characteristics
Figure 47: THD+N vs. output power
Figure 44: THD+N vs. output power
10
10
RL = 4Ω
F = 20kHz
Av = 2
Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc = 2.2V
Vcc = 2.6V
Vcc = 3.3V
THD+N (%)
THD+N (%)
RL = 4Ω
F = 1kHz
Av = 2
1 Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc = 5V
0.1
Vcc = 2.2V
Vcc = 2.6V
Vcc = 3.3V
Vcc = 5V
1
0.01
1E−3
0.01
0.1
0.1
1E−3
1
0.01
0.1
Pout (W)
Figure 48: THD+N vs. output power
Figure 45: THD+N vs. output power
10
10
Vcc = 2.2V
Vcc = 2.6V
Vcc = 3.3V
THD+N (%)
THD+N (%)
RL = 8Ω
F = 1kHz
Av = 2
1 Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc = 5V
0.1
0.01
1E−3
1
RL = 8Ω
F = 20kHz
Av = 2
Cb = 1µF
BW < 125kHz
Tamb = 25°C
Vcc = 2.2V
Vcc = 2.6V
Vcc = 3.3V
Vcc = 5V
0.1
0.01
0.1
1
1E−3
0.01
0.1
Pout (W)
Figure 49: THD+N vs. output power
10
10
Vcc = 2.2V
Vcc = 2.6V
THD+N (%)
THD+N (%)
1
Pout (W)
Figure 46: THD+N vs. output power
RL = 16Ω
F = 1kHz
Av = 2
1 Cb = 1µF
BW < 125kHz
Tamb = 25°C
1
Pout (W)
Vcc = 3.3V
Vcc = 5V
0.1
RL = 16Ω
F = 20kHz
Av = 2
Cb = 1µF
BW < 125kHz
1 Tamb = 25°C
Vcc = 2.2V
Vcc = 2.6V
Vcc = 3.3V
Vcc = 5V
0.1
0.01
1E−3
0.01
0.1
Pout (W)
14/29
1
1E−3
0.01
0.1
Pout (W)
1
Electrical characteristics
TS4984
Figure 53: SIgnal to noise ratio vs. power supply
Figure 50: THD+N vs. frequency
with unweighted filter (20Hz to 20kHz)
Signal to Noise Ratio (dB)
THD + N (%)
100
RL=4Ω
Av=2
0.1 Cb = 1µF
Bw < 125kHz
Tamb = 25°C
Vcc=5V, Po=1W
Vcc=2.2V, Po=40mW
95
RL=16Ω
RL=8Ω
90
RL=4Ω
Av = 2
Cb = 1µF
THD+N < 0.7%
Tamb = 25°C
0.01
20
100
1000
Frequency (Hz)
Signal to Noise Ratio (dB)
THD + N (%)
Vcc=5V, Po=O.8W
1000
Frequency (Hz)
RL=16Ω
RL=4Ω
75
2.5
3.0
Av = 10
Cb = 1µF
THD+N < 0.7%
Tamb = 25°C
3.5
4.0
4.5
5.0
Figure 55: SIgnal to noise ratio vs. power
supply with A weighted filter
105
Signal to Noise Ratio (dB)
THD + N (%)
5.0
Power Supply Voltage (V)
Vcc=5V, Po=O.5W
Vcc=2.2V, Po=70mW
0.01
1000
Frequency (Hz)
10000 20k
RL=16Ω
100
RL=8Ω
RL=4Ω
95
90
100
4.5
RL=8Ω
10000 20k
Figure 52: THD+N vs. frequency
20
4.0
80
70
RL=16Ω
0.1 Av=2
Cb = 1µF
Bw < 125kHz
Tamb = 25°C
3.5
85
0.01
100
3.0
Figure 54: SIgnal to noise ratio vs. pwr supply
with unweighted filter (20Hz to 20kHz)
Vcc=2.2V, Po=70mW
20
2.5
Power Supply Voltage (V)
Figure 51: THD+N vs. frequency
RL=8Ω
0.1 Av=2
Cb = 1µF
Bw < 125kHz
Tamb = 25°C
85
10000 20k
2.5
3.0
Av = 2
Cb = 1µF
THD+N < 0.7%
Tamb = 25°C
3.5
4.0
4.5
5.0
Power Supply Voltage (V)
15/29
TS4984
Electrical characteristics
Figure 59: Crosstalk vs. frequency
Figure 56: SIgnal to noise ratio vs. power
supply with A weighted filter
0
90
Crosstalk (dB)
Signal to Noise Ratio (dB)
95
RL=16Ω
RL=8Ω
85
RL=4Ω
Av = 10
Cb = 1µF
THD+N < 0.7%
Tamb = 25°C
80
2.5
3.0
3.5
4.0
4.5
Vcc = 2.6V
-20 Av = 2
Pout = 180mW
RL = 8 Ω
-40 BW < 125kHz
Tamb = 25 C
-60
-80
-100
-120
5.0
100
1000
Frequency (Hz)
Power Supply Voltage (V)
0
0
Vcc = 5V
-20 Av = 2
Pout = 1W
RL = 8 Ω
-40
BW < 125kHz
Tamb = 25 C
-60
Vcc = 2.2V
Av = 2
Pout = 70mW
RL = 8 Ω
-40 BW < 125kHz
Tamb = 25 C
-60
-20
L to R
Crosstalk (dB)
Crosstalk (dB)
10000
Figure 60: Crosstalk vs. frequency
Figure 57: Crosstalk vs. frequency
R to L
-80
-100
-120
-120
1000
Frequency (Hz)
R to L
L to R
-80
-100
100
10000
100
1000
Frequency (Hz)
10000
Figure 61: Output noise voltage, device ON
Figure 58: Crosstalk vs. frequency
50
Vcc = 3.3V
-20 Av = 2
Pout = 300mW
RL = 8 Ω
-40
BW < 125kHz
Tamb = 25 C
-60
L to R
Output Noise Voltage ( Vrms)
0
Crosstalk (dB)
R to L
L to R
R to L
-80
-100
Vcc = 2.2V to 5V
Cb = 1µF
RL = 8Ω
Tamb = 25°C
45
40
35
Unweighted Filter
30
25
20
A Weighted Filter
15
-120
10
100
16/29
1000
Frequency (Hz)
10000
2
4
6
Closed Loop Gain
8
10
Electrical characteristics
TS4984
Figure 63: Power derating curves
QFN16 Package Power Dissipation (W)
Output Noise Voltage ( Vrms)
Figure 62: Output noise voltage, device in
standby
3.00
2.75
2.50
2.25
Unweighted Filter
2.00
A Weighted Filter
1.75
1.50
1.25
1.00
0.75 Vcc = 2.2V to 5V
0.50 Cb = 1µF
RL = 8Ω
0.25 Tamb = 25°C
0.00
2
4
3.5
2.5
Mounted on 2-layer PCB
2.0
1.5
1.0
0.5
0.0
6
8
10
Mounted on 4-layer PCB with via
3.0
No Heat sink
0
25
50
75
100
Ambiant Temperature ( C)
125
150
Closed Loop Gain
17/29
TS4984
4
Application Information
Application Information
The TS4984 integrates two monolithic power amplifiers with a BTL (Bridge Tied Load) output type
(explained in more detail in Section 4.1). For this discussion, only the left-channel amplifier will be
referred to.
Referring to the schematic in Figure 64, we assign the following variables and values:
Vin = IN-L
Vout1 = VO-L, Vout2 = VO+R
Rin = Rin-L, Rfeed = Rfeed-L
Cfeed = Cfeed-L
Figure 64: Typical application schematic - left channel
Cfeed = Cfeed-L
VCC
+
Rfeed = Rfeed-L
Cs
1u
Input L Cin = Cin-L
Vin- = IN-L
-
Vin+= IN+L
+
VCC2
VCC1
TS4984
Rin = Rin-L
GND
Vout 1= VO-L
RL
Standby
Bias
AV = -1
Vout 2 = VO+L
+
+
Bypass
Cb
1u
4.1 BTL configuration principle
BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output
amplifiers. Thus, we have:
Single-ended output 1 = Vout1 = Vout (V),
Single-ended output 2 = Vout2 = -Vout (V), Vout1 - Vout2 = 2Vout (V)
The output power is:
2
( 2V outRMS )
P out = ------------------------------------RL
For the same power supply voltage, the output power in a BTL configuration is four times higher than the
output power in a single-ended configuration.
18/29
Application Information
TS4984
4.2 Gain in typical application schematic
The typical application schematic (Figure 64) is shown on page 18.
In the flat region (no Cin effect), the output voltage of the first stage is:
R feed
V ou t 1 = ( – V in ) --------------R in
(V)
For the second stage: Vout2 = -Vout1 (V)
The differential output voltage is:
R feed
V out 2 – V ou t 1 = 2V in --------------R
(V)
in
The differential gain, referred to as Gv for greater convenience, is:
V out 2 – V out 1
R feed
G v = ------------------------------------ = 2 --------------R in
V in
Vout2 is in phase with Vin and Vout1 is phased 180° with Vin. This means that the positive terminal of the
loudspeaker should be connected to Vout2 and the negative to Vout1.
4.3 Low and high frequency response
In the low frequency region, Cin starts to have an effect. Cin forms with Rin a high-pass filter with a -3dB
cut-off frequency:
1
F CL = -------------------------- (Hz)
2πR in C in
In the high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel with
Rfeed. It forms a low-pass filter with a -3dB cut-off frequency. FCH is in Hz.
1
F CH = ---------------------------------------2πR feed C feed
(Hz)
19/29
TS4984
Application Information
The following graph (Figure 65) shows an example of Cin and Cfeed influence.
Figure 65: Frequency response gain versus Cin & C feed
10
5
Gain (dB)
0
Cfeed = 330pF
Cfeed = 680pF
-5
Cfeed = 2.2nF
Cin = 470nF
-10
-15
Cin = 22nF
-20
Cin = 82nF
-25
10
Rin = Rfeed = 22kΩ
Tamb = 25°C
100
1000
Frequency (Hz)
10000
4.4 Power dissipation and efficiency
Hypotheses:
l Voltage and current in the load are sinusoidal (Vout and Iout).
l Supply voltage is a pure DC source (Vcc).
Regarding the load we have:
V out = V PEAK sinωt
(V)
and
V out
I out = -------------RL
(A)
and
V PE AK 2
P out = ------------------------2R L
(W)
Therefore, the average current delivered by the supply voltage is:
V PEAK
I CC
= 2 ------------------(A)
AV G
π RL
The power delivered by the supply voltage is:
P
20/29
su pply
= V CC ⋅ I CC
A VG
(W)
Application Information
TS4984
Then, the power dissipated by each amplifier is:
P
diss
= P
sup ply
2 2 V CC
P d iss = ------------------------ ⋅
π RL
(W)
– P out
P out – P out
(W)
and the maximum value is obtained when:
∂P d iss
--------------------- = 0
∂P out
and its value is:
2
2V cc
P dissmax = -----------π2RL
Note:
(W)
This maximum value is only depending on power supply voltage and load values.
The efficiency, η, is the ratio between the output power and the power supply:
π V PEAK
P o ut
η = --------------------- = ------------------------P supply
4V CC
The maximum theoretical value is reached when VPEAK = VCC, so that:
π
----- = 78.5%
4
The TS4984 has two independent power amplifiers, and each amplifier produces heat due to its power
dissipation. Therefore, the maximum die temperature is the sum of the each amplifier’s maximum power
dissipation. It is calculated as follows:
Pdiss L = Power dissipation due to the left channel power amplifier.
Pdiss R = Power dissipation due to the right channel power amplifier.
Total Pdiss = P diss L + Pdiss R (W)
In most cases, Pdiss L = Pdiss R, giving:
Total P
d iss
= 2P
dissL
(W)
or, stated differently:
4 2 V CC
Total P diss = ------------------------ P out – 2P out
π RL
(W)
21/29
TS4984
Application Information
4.5 Decoupling the circuit
Two capacitors are needed to correctly bypass the TS4984. A power supply bypass capacitor CS and a
bias voltage bypass capacitor CB.
CS has particular influence on the THD+N in the high frequency region (above 7 kHz) and an indirect
influence on power supply disturbances. With a value for CS of 1 µF, you can expect similar THD+N
performances to those shown in the datasheet. For example:
l In the high frequency region, if CS is lower than 1 µF, it increases THD+N and disturbances on the
power supply rail are less filtered.
l On the other hand, if CS is higher than 1 µF, those disturbances on the power supply rail are more
filtered.
Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR
(with input grounded and in the lower frequency region), in the following manner:
l If C b is lower than 1µF, THD+N increases at lower frequencies and PSRR worsens.
l If C b is higher than 1µF, the benefit on THD+N at lower frequencies is small, but the benefit to PSRR
is substantial.
Note that C in has a non-negligible effect on PSRR at lower frequencies. The lower the value of Cin, the
higher the PSRR.
4.6 Wake-up time, TWU
When the standby is released to put the device ON, the bypass capacitor C b will not be charged
immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly until the Cb
voltage is correct. The time to reach this voltage is called wake-up time or TWU and specified in electrical
characteristics table with Cb = 1 µF.
If Cb has a value other than 1 µF, please refer to the graph in Figure 66 to establish the wake-up time
value.
Due to process tolerances, the maximum value of wake-up time could be establish by the graph in
Figure 67.
Figure 66: Typical wake-up time vs. Cb
Tamb=25°C
600
Startup Time (ms)
500
400
Vcc=2.6V
300
200
Vcc=5V
Note:
22/29
500
Vcc=2.6V
400
300
200
Vcc=5V
100
100
0
Tamb=25°C
Vcc=3.3V
Vcc=3.3V
Max. Startup Time (ms)
600
Figure 67: Maximum wake-up time vs. Cb
0.1
1
2
3
Bypass Capacitor Cb ( F)
4
4.7
0
0.1
1
2
3
Bypass Capacitor Cb ( F)
4
4.7
Bypass capacitor Cb as also a tolerance of typically +/-20%. To calculate the wake-up time with this tolerance,
refer to the previous graph (considering for example for Cb = 1 µF in the range of 0.8 µF ≤ 1 µF ≤ 1.2 µF).
Application Information
TS4984
4.7 Shutdown time
When the standby command is set, the time required to put the two output stages in high impedance and
the internal circuitry in shutdown mode is a few microseconds.
Note:
In shutdown mode, Bypass pin and Vin- pin are short-circuited to ground by internal switches. This allows for
the quick discharge of the Cb and Cin capacitors.
4.8 Pop performance
Pop performance is intimately linked with the size of the input capacitor Cin and the bias voltage bypass
capacitor Cb.
The size of Cin is dependent on the lower cut-off frequency and PSRR values requested. The size of Cb
is dependent on THD+N and PSRR values requested at lower frequencies.
Moreover, Cb determines the speed with which the amplifier turns ON. In order to reach near zero pop
and click, the equivalent input constant time is:
tin = (Rin + 2 kΩ) x Cin (s) with Rin ≥ 5 kΩ
must not reach the τin maximum value as indicated in the graph below in Figure 68.
Figure 68: τin max. versus bypass capacitor
160 Tamb=25°C
Vcc=3.3V
in max. (ms)
120
Vcc=2.6V
80
40
0
Vcc=5V
1
2
3
Bypass Capacitor Cb ( F)
4
By following previous rules, the TS4984 can reach near zero pop and click even with high gains such as
20 dB.
Example calculation
With R in = 22 kΩ and a 20 Hz, -3 db low cut-off frequency, Cin = 361 nF. So, Cin =390 nF with standard
value which gives a lower cut-off frequency equal to 18.5 Hz. In this case, (Rin + 2 kΩ) x Cin = 9.36 ms.
When referring to the previous graph, if Cb =1 µF and Vcc = 5 V, we read 20 ms max. This value is twice
as high as our current value, thus we can state that pop and click will be reduced to its lowest value.
Minimizing both Cin and the gain benefits both the pop phenomena, and the cost and size of the
application.
23/29
TS4984
Application Information
4.9 Application example: Differential-input BTL power stereo amplifier
The schematic in Figure 69 shows how to design the TS4984 to work in differential-input mode. For this
discussion, only the left-channel amplifier will be referred to.
Let:
R1R = R2L = R1, R2R = R2L = R2
CinR = C inL = Cin
The gain of the amplifier is:
R2
G vdif = 2 × ------R1
In order to reach the optimal performance of the differential function, R1 and R2 should be matched at 1%
maximum.
Figure 69: Differential input amplifier configuration
R2L
VCC
+
R1L
Cs
IN-L
VCC2
CinL
VCC1
Neg. Input LEFT
TS4984
VO-L
Pos. Input LEFT
CinL
R1L
IN+L
+
R2L
LEFT Speaker
8 Ohms
-
StandBy
StandBy
Control
Bias
AV = -1
BypassL
VO+L
+
R2R
Pos. Input RIGHT
CinR
R1R
IN+R
+
VO-R
IN-R
Neg. Input RIGHT
CinR
-
R1R
RIGHT Speaker
8 Ohms
AV = -1
BypassR
+
+
R2R
24/29
GND2
GND1
Cb
VO+R
Application Information
TS4984
The value of the input capacitor CIN can be calculated with the following formula, using the -3dB lower
frequency required (where FL is the lower frequency required):
C IN ≈
Note:
1
(F )
2 π R 1 FL
This formula is true only if:
1
(Hz )
FCB =
2 π (R 1 + R 2 ) C B
is 5 times lower than FL.
The following bill of materials is provided as an example of a differential amplifier with a gain of 2 and a
-3 dB lower cut-off frequency of about 80 Hz.
Table 7: Example of a bill of material
Designator
Part Type
R1L = R1R
20kΩ / 1%
R2L = R2R
20kΩ / 1%
CinR = CinL
100nF
Cb=CS
1µF
U1
TS4984
25/29
TS4984
Application Information
4.10 Demoboard
A demoboard for the TS4984 is available.
For more information about this demoboard, please refer to Application Note AN2049, which can be
found on www.st.com.
Figure 70 shows the schematic of the demoboard. Figure 71, Figure 72 and Figure 73 show the
component locations, top layer and bottom layer respectively.
Figure 70: Demoboard schematic
C1
R1
VCC
Vcc
+
GND
C7
1u
R2
GND
1
IN-L
-
2
IN+L
+
14
13
C2
VCC1
Neg. Input L
VCC2
Cn1
U1
Cn2
C3
R3
Pos. Input L
C9
100nF
VO-L
16
VO+L
15
VO-R
8
VO+R
7
GND
R4
Cn3
VCC
Cn8
Jumper J1
1
2
3
12
Bias
AV = -1
Bypass L
Neg. Output L
Pos. Output L
+
+
3
Cn4
-
Standby
C8
1u
R7
Pos. Input R
C4
R5
GND
10
IN+R
+
IN-R
-
Cn5
C5
Neg. Input R
R6
9
GND
Cn6
Cn7
AV = -1
Bypass R
R8
26/29
GND2
GND1
5
C6
Neg. Output R
+
6
11
*
Pos. Output R
Application Information
Figure 71: Components location
TS4984
Figure 72: Top layer
Figure 73: Bottom layer
27/29
TS4984
5
Package Mechanical Data
Package Mechanical Data
5.1 Dimensions of QFN16 package
DIMENSIONS
REF
A
A1
A3
b
D
D2
E
E2
e
K
L
r
*
* The Exposed Pad is connected to Ground.
mm
MIN.
TYP.
MAX.
0.8
0.9
1.0
0.02
0.05
0.20
0.18
0.25
0.30
3.85
4.0
4.15
2.1
3.85
2.6
4.0
2.1
2.6
0.50
0.2
0.30
0.40
0.11
5.2 Footprint recommended data
A
FOOTPRINT DATA
mm
E
A
B
C
F
B
D
G
C
28/29
D
E
F
G
4.15
5.0
5.0
0.5
0.35
0.45
2.70
0.22
0.50
TS4984
6
Revision History
Revision History
Date
Revision
01 Jan 2005
1
Description of Changes
First Release
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