834 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 8, AUGUST 2009
Abstract —This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gateto-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated
Fowler–Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.
Index Terms —Memories, thin film transistors.
According to the basic operation principle of memory devices, a gate read voltage V read between two distinct threshold voltages is applied to measure the corresponding current and identify the status of the memory device [5]. However, several studies have reported that a high gate-induced drain leakage
(GIDL) current could cause misidentification of that status in SONOS memory devices, because some carriers generated from GIDL would flow to Si substrate and result in V t disturbance, and the large GIDL current would cause read error in memory array [6]–[10]. Therefore, for SONOS TFTs, this problem will be more serious due to the significant trap-assisted
GIDL current. In addition, the leakage current also causes high power consumption [11].
In this letter, we utilized band-to-band hot hole injection to suppress the trap-assisted GIDL current caused by the trapped electrons in the gate-to-drain overlap region.
I. I NTRODUCTION
P OLYSILICON thin-film transistors (poly-Si TFTs) have attracted much attention for use in active-matrix liquidcrystal displays (LCDs) since they can be integrated with peripheral driving circuits because of their high effect mobility and driving current [1]. In order to simplify process complexity and lower cost, previous studies have proposed a system-onpanel (SOP) display technology with high-performance poly-
Si TFTs designed as functional devices on an LCD panel as controller and memory [2]–[4]. SOP technology is primarily focused on portable electronics; thus, low power consumption is required to ensure long battery life. As is well known, nonvolatile memory is widely utilized for data storage in various portable electronics due to its advantages of low power consumption and nonvolatility.
Manuscript received May 4, 2009. First published July 17, 2009; current version published July 27, 2009. This work was supported in part by the
National Science Council of the Republic of China under Contracts NSC-97-
3114-M-110-001 and 97-2112-M-110-009-MY3. The review of this letter was arranged by Editor J. K. O. Sin.
T.-C. Chen and S.-C. Chen are with the Department of Physics, National
Sun Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail: a49136@yahoo.
com.tw; scchen0921@gmail.com).
T.-C. Chang is with the Department of Physics, National Sun Yat-
Sen University, Kaohsiung 80424, Taiwan, and also with the Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University,
Kaohsiung 80424, Taiwan (e-mail: tcchang@mail.phys.nsysu.edu.tw).
F.-Y. Jian is with the Department of Electro-Optical Engineering,
National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail: fyjian.tw@yahoo.com.tw).
C.-S. Lin is with the Department of Electrical Engineering, National Sun
Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail: uk0601@gmail.com).
M.-H. Lee, J.-S. Chen, and C.-C. Shih are with the AU Optronics
Corporation, Hsinchu 30078, Taiwan (e-mail: Vincent.MH.Lee@auo.com;
Jim.Shone.Chen@auo.com; Matt.Shih@auo.com).
Digital Object Identifier 10.1109/LED.2009.2023827
II. E XPERIMENT
In this letter, n-channel SONOS TFTs with top gate and overlap structures were fabricated on a Corning1737 glass substrate.
The detailed fabrication procedures are as follows. The silicon oxide buffer layer and a 50-nm-thick undoped amorphous-Si
(a-Si) film were deposited sequentially by plasma-enhanced chemical vapor deposition (PECVD) at 380
◦
C, followed by dehydrogenation via furnace annealing process at 450
◦
C. Then, the a-Si film was crystallized by a 308-nm XeCl excimer laser with a line-shaped beam power of 350 mJ/cm
2
. After the active region was patterned by plasma dry etching, the source/drain (S/D) regions were defined by a mask and formed by a mass-separated ion implanter technique. Next, a 70-nmthick ONO multilayer gate dielectric consisting of bottom oxide (10 nm)/silicon nitride (20 nm)/top oxide (40 nm) was deposited by PECVD. The source and drain overlap region was formed after ONO stacking. Then, MoW was sputtered and patterned as a gate metal. The SONOS-TFT dimensions were L = 6 μ m and W = 30 μ m, and the overlap length was
0.75
μ m. The normalized I
D
– V
G measurement conditions are that the gate voltage is swept from
−
10 to 10 V and the drain voltage is set to 0.1 V. Here, the normalized drain current is defined as I
D
/ ( W/L ) , and all the measurements are at 30
◦
C environment.
III. R ESULT AND D ISCUSSION
Fig. 1(a) shows the normalized current–voltage ( I – V ) characteristics of the n-channel poly-Si SONOS TFTs after
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CHEN et al.
: IMPROVEMENT OF MEMORY STATE MISIDENTIFICATION 835
Fig. 1.
(a) Normalized V
G
– I
D characteristics of SONOS TFT at initial erased and programmed states. The inset shows the energy band diagram operated at off state in (solid line) initial state and (dotted line) program state. (b) Normalized current–voltage ( I – V ) characteristics after repeated FN program and erase operations.
Fig. 2.
(a) Normalized V
G
– I
D characteristics of programmed state after electrical stress with V
G inset schematic diagram of SONOS-TFT cross section shows hot hole injection. (b) Normalized I
D
=
– V
−
G
25 V and V
D
= 10 V with source common for 0.1 s. The characteristic after stress at 85
◦
C for 1000 s.
a conventional Fowler–Nordheim (FN) erase operation at
V
G
= −
40 V and program operation at V
G
= 40 V. Clearly, the leakage current increases significantly after program operation.
As is well understood, under the OFF -state operation (a positive bias is applied to the drain, and a negative bias is applied to the gate), the trap-assisted GIDL is the main mechanism for leakage current in poly-Si TFTs [12]. For the programmed state, the energy band bending in the overlap region under OFF state is more pronounced due to the larger vertical field enhanced by the trapped electrons, as shown in the inserted band diagram with the dotted lines indicating the enhancement. Therefore, the larger number of electrons tunneling to the conduction band results in a larger leakage current. For the erase state, the small amount of holes trapped in the nitride layer can suppress the energy band bending. Thus, the leakage current decreased after performing the erase operation. Fig. 1(b) shows the normalized
I
D
– V
G characteristics after repeated FN program ( for 0.05 s) and erase ( V
G
V
G
= 40 V
= − 40 V for 2 s) operations; the result shows that the trap-assisted GIDL phenomenon after program is repeatable and the erase characteristics are not affected.
According to the basic operation principle of nonvolatile memory devices, the noticeable leakage current contributed by the electrons trapped in the nitride would possibly lead to more power consumption and serious signal misidentification. In order to avoid these issues, we propose band-to-band hot hole injection to reduce the trap-assisted GIDL current.
Fig. 2(a) shows the normalized transfer I
D
– V
G curves at the programmed state before and after electrical stress with V
GS
−
25 V and V
DS
=
=
10 V for 0.1 s. The results reveal that the leakage current after stress is significantly suppressed by an order of about 2.5. During the electrical stress, holes generated by band-to-band tunneling can obtain kinetic energy in the depletion region due to the lateral field and then are injected into the nitride layer due to the vertical field [13]. The injected holes can reduce the vertical electrical field near the overlap region; thus, the leakage current induced by trapped electrons can be effectively suppressed [shown in the inset of Fig. 2(a)], in order to verify that the injected holes could stably be stored in the nitride layer. The stressed normalized I
D at 85
◦
– V
G characteristic
C for 1000 s is shown in Fig. 2(b), and the result shows that there is no obvious change in the leakage current, indicating that the injected holes could stably be stored in the nitride layer.
Moreover, the phenomenon after stress reveals that, in addition to leakage current, the threshold voltage swing, and on-current are unchanged.
( V
T
) , subthreshold
Fig. 3 shows the normalized I
D
– V
G characteristics without stress and with stress after 10 and 100 FN erase ( V
G
=
−
40 V for 2 s) and program ( V
G
= 40 V for 0.05 s) operations. The FN
E/P operations can be iterated to verify whether the influence of the electrical stress is sustainable. The result indicates that the suppressed leakage current, even after 100 E/P operation cycles, is still unchanged because the injected holes remain in the
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836 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 8, AUGUST 2009 trap-assisted GIDL. The experimental results clearly show that the suppression of the leakage current depends on the band-toband hot holes resulting from the vertical field—the larger the vertical field, the more hot holes are injected, and the greater the suppression. Because the injected hot holes are stored not only near the nitride layer and tunnel oxide interface but also throughout the depth of the nitride layer, the suppressant effect is sustained even after 100 iterative program/erase operations.
Therefore, such an electrical stress method is quite promising both due to its effectiveness and because it requires no additional fabrication processes.
Fig. 3.
Normalized V
G
– I
D characteristics before and after stress with 10 and
100 iterations of FN erased and programmed operations.
A CKNOWLEDGMENT
Part of the work mentioned in this letter was performed at
AU Optronics Corporation.
Fig. 4.
V
DS
Normalized
= 5 V.
V
G
– I
D characteristics of programmed state before electrical stress and after electrical stress at V
GS from
−
10 to
−
20 V, with nitride layer, and the erase characteristics are not affected even after stress with 100 E/P operations. However, the electrons trapped during FN E/P operations do not entirely recombine with the injected hot holes. The physical position of the injected holes is not completely consistent with the programmed electrons because the injected hot holes are stored not only near the nitride layer and tunnel oxide interface but also throughout the depth of the nitride layer [as shown in the inserted diagram of Fig. 2(a)] [14]. In addition, despite the fact that the hot holes are injected near but not in the overlap region, the hole distribution spreads horizontally into the overlap region and acts to aid suppression. Therefore, the leakage current after
100 E/P operation cycles is almost invariable.
To realize the influence of stress voltage on the suppressed leakage current, the normalized I – V characteristics of the programmed state with different voltages were also performed
( V
GS was varied from − 10 to − 20 V, and V
DS was fixed at 5 V), as shown in Fig. 4. As the negative gate voltage increased, the vertical field in the gate-to-drain overlap region and the energy band bending increased; thus, more holes can be generated and injected into the nitride layer, resulting in a lower leakage current.
IV. C ONCLUSION
In this letter, we used band-to-band hot hole injection to reduce the high electrical field caused by the programmed electrons in the gate-to-drain overlap region and reduce the
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