IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 9, SEPTEMBER 2010
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Hetero-Gate-Dielectric Tunneling
Field-Effect Transistors
Woo Young Choi, Member, IEEE, and Woojun Lee
Abstract—A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal–oxide–
semiconductor field-effect transistor due to its immunity to
short-channel effects. However, TFETs have suffered from low
ON -current, severe ambipolar behavior, and gradual transition
between ON- and OFF-states. To address those issues, the authors
have proposed hetero-gate-dielectric TFETs. The proposed device
enhances ON-current, suppresses ambipolar behavior, and makes
abrupt ON–OFF transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of
the conduction band edge at the tunneling junction.
Index Terms—Ambipolar behavior, gate insulator, heterogate-dielectric, subthreshold swing (SS), tunneling field-effect
transistor (TFET).
I. I NTRODUCTION
R
ECENTLY, various kinds of novel electron devices have
been studied to overcome the scaling limit of MOSFETs
[1]–[3]. Among them, a tunneling field-effect transistor (TFET)
is considered one of the most promising alternatives since it
is immune to subthreshold swing (SS) degradation at shortchannel length. On the other hand, it has been reported that
TFETs have low ON-current Ion , which limits operation speed,
and severe ambipolar behavior, which increases leakage current
Iamb [4], [5]. Additionally, it is problematic that the SS values
of experimentally demonstrated silicon TFETs are larger than
expected values. In theory, the SS of silicon TFETs can be
reduced smaller than 60 mV/dec at room temperature, which
is the minimal SS of conventional MOSFETs. However, only
a few research groups have succeeded in demonstrating sub60-mV/dec SS at room temperature experimentally [6], [7].
Thus, to improve Ion and SS, a high-k material has been
introduced as a gate insulator [8]. However, using a high-k
material as a gate insulator may increase leakage current Iamb
due to severe ambipolar behavior. To alleviate ambipolar behavior, TFETs without gate–drain overlap have been proposed
[9]. However, this approach actually increases drain-to-source
channel length, which significantly reduces chip density.
In this brief, we have proposed hetero-gate-dielectric TFETs
(HG TFETs) for higher Ion , lower Iamb , and smaller SS without
Manuscript received February 9, 2010; revised May 18, 2010; accepted
May 20, 2010. Date of publication July 15, 2010; date of current version
August 20, 2010. This work was supported by the National Research Foundation of Korea, funded by the Ministry of Education, Science and Technology,
under Grants 2009-0082439 and 2009-0084522. The review of this brief was
arranged by Editor C. McAndrew.
The authors are with the Department of Electronic Engineering, Sogang
University, Seoul 121-742, Korea (e-mail: wchoi@sogang.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2052167
Fig. 1. Schematic of the proposed HG TFET. The HG TFET features different
gate insulators at the source (high-k material) and drain (silicon oxide) sides.
Since gate-to-channel coupling strength is different between channel regions
overlapped by the high-k material and silicon oxide, HG TFETs have a
local minimum of Ec at the tunneling junction, which improves Ion and SS.
In addition, because low-k silicon oxide is located at the drain side where
ambipolar behavior occurs, Iamb can be suppressed.
sacrificing chip density, as shown in Fig. 1. The HG TFET features different gate dielectric materials at the drain and source
sides, which can be formed by isotropic etching of silicon
oxide followed by high-k material deposition. The proposed
HG TFETs will be compared with two kinds of conventional
devices, namely, TFETs that use only silicon oxide as a gate
insulator (SiO2 -only TFETs) and TFETs that use only a high-k
material as a gate insulator (high-k-only TFETs). The SiO2 only TFET corresponds to the HG TFET whose length of
silicon oxide under the gate, i.e., LSiO2 , is equal to the gate
length LG , whereas the high-k-only TFET corresponds to the
HG TFET whose length of high-k material under the gate,
i.e., Lhigh-k , is equal to LG . The HG TFET is expected to
show higher Ion and smaller SS than the SiO2 -only and high-konly TFETs by modifying the band energy structure. A high-k
material partially located at the source side induces a local minimum of the conduction band edge Ec at the tunneling junction,
which will be discussed later from the following sections. In
addition, since silicon oxide whose relative permittivity is low
is located at the drain side, ambipolar behavior can effectively
be suppressed, which lowers Iamb .
II. R ESULTS AND D ISCUSSION
To evaluate the merits of the proposed HG TFET, it has been
compared with the SiO2 -only and high-k-only TFETs by twocarrier and 2-D device simulation using Silvaco ATLAS [10]. A
nonlocal band-to-band tunneling model has been used [10]. In
simulation, LG is 50 nm, which is equal to the sum of LSiO2 and
Lhigh-k . In addition, the physical thickness of the gate insulator,
i.e., tins , and that of the silicon-on-insulator (SOI) layer, i.e.,
tSOI , are 2 and 30 nm, respectively. The relative permittivity of
the high-k material is assumed to be 25, which refers to that
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 9, SEPTEMBER 2010
Fig. 2. (a) Transfer curves of the HG, SiO2 -only, and high-k-only TFETs in
the case of n-type doped polysilicon gates. HG TFETs follow SiO2 -only TFETs
at low VG and high-k-only TFETs at high VG . (b) Transfer curves of the HG,
SiO2 -only, and high-k-only TFETs when the gate workfunction is adjusted so
that Vonset is 0 V for fair comparison. HG TFETs have the highest Ion due to
their smallest SS.
of HfO2 . The channel doping concentration is 1016 cm−3 . An
abrupt junction profile is assumed. In addition, we assume that
the interface between the high-k material and silicon oxide is
abrupt. It is reasonable considering that the diffusion length of
Hf into SiO2 is only ∼0.035 nm when the device is annealed
at 1000 ◦ C for 5 s [11]. Ion is defined as the drain current ID
when both the gate voltage VG and the drain voltage VD are
1 V, and Iamb is defined as ID when VG is −0.2 V and VD is
1 V. SS is defined as an average slope when ID increases from
1 fA/μm to 1 nA/μm. The onset voltage Vonset is defined as
VG when ID is 1 fA/μm at 1-V VD .
Fig. 2(a) compares the transfer characteristics of the HG
TFET whose Lhigh-k is 6 nm with those of the SiO2 -only and
high-k-only TFETs in the case of n-type doped polysilicon
gates. Due to the heterogeneous gate dielectric, HG TFETs
follow SiO2 -only TFETs at low VG and high-k-only TFETs at
high VG . It is because the ON-state is determined at the sourceto-channel region overlapped by the high-k material, whereas
the OFF-state ambipolar behavior is determined at the drain-tochannel region overlapped by silicon oxide. It should also be
noted that the minimal leakage current level is determined by
reverse-biased p-i-n diode leakage. For fair comparison, from
now on, the gate workfunction will be adjusted so that Vonset
becomes 0 V. The value of gate workfunction is ∼4.37 eV,
which is attainable by using metal gates [12]. Fig. 2(b) shows
a redrawn version of Fig. 2(a) when the gate workfunction is
adjusted. It shows that HG TFETs have higher Ion than high-k
TFETs, whereas they have as low Iamb as SiO2 -only TFETs,
which leads to high a ON–OFF current ratio. It is because
HG TFETs have smaller SS than SiO2 -only and high-k-only
TFETs, which can be explained as follows: Fig. 3(a) shows that
HG TFETs have a local minimum of Ec due to different gate-tochannel coupling strength between channel regions overlapped
by the high-k material and silicon oxide. Fig. 3(b) compares HG
TFETs with high-k-only TFETs in terms of source-to-channel
tunneling barrier width as a function of VG . HG TFETs show
a more abrupt change and a lower value of tunneling barrier
width than high-k-only TFETs. It is because the tunneling
barrier of HG TFETs abruptly narrows when a local minimum
of Ec is aligned with the valence band edge Ev of the source,
as shown in the inset of Fig. 3(b). In the case of SiO2 -only
Fig. 3. (a) Band diagram of the HG TFET whose Lhigh-k is 6 nm when VG
is 0 V and VD is 1 V. (b) Source-to-channel tunneling barrier width of the HG
TFET whose Lhigh-k is 6 nm compared with that of the high-k-only TFET.
The band diagram located in the box in (a) is magnified into two inset figures
in (b) depending on VG .
Fig. 4. (a) Ion and SS and (b) Iamb of HG TFETs depending on Lhigh-k
compared with those of SiO2 -only and high-k-only TFETs. SiO2 -only and
high-k-only TFETs correspond to HG TFETs whose Lhigh-k ’s are 0 and
50 nm, respectively.
and high-k-only TFETs, source-to-channel tunneling barrier
width gradually decreases since Ec gradually decreases from
the source-to-channel region. On the other hand, in the case of
HG TFETs, when the gate is biased around Vonset , tunneling
barrier width is almost the same as that of high-k-only TFETs
because a local minimum of Ec is not aligned with Ev of the
source. It means that a local minimum of Ec has not been
involved in the band-to-band tunneling process yet when VG
is around Vonset . However, as VG becomes higher, a local
minimum of Ec is shifted downward and eventually aligned
with Ev of the source. Therefore, when VG exceeds Vonset , the
length of the tunneling path abruptly decreases because bandto-band tunneling between a local minimum of Ec and Ev of
the source begins to dominate the whole tunneling process.
To optimize the design of HG TFETs, Lhigh-k has been optimized. Fig. 4(a) shows Ion and SS as a function of Lhigh-k . Note
that HG TFETs whose LSiO2 or Lhigh-k is 50 nm correspond to
SiO2 -only or high-k-only TFETs, respectively. It is observed
that Lhigh-k can be optimized in terms of SS and Ion . The
optimization process is related to the depth and width of the
conduction band well where a local minimum of Ec is located.
As Lhigh-k decreases, the conduction band well becomes shallower, which makes band-to-band tunneling difficult to occur.
On the contrary, as Lhigh-k increases, the conduction band well
becomes wider, which leads to a less abrupt transition between
OFF- and ON -states. When Lhigh-k is optimized around 6 nm,
CHOI AND LEE: HETERO-GATE-DIELECTRIC TFETs
the optimized HG TFETs show ∼60% smaller SS and ∼30%
higher Ion than high-k-only TFETs. In addition, the HG TFETs
show ∼80% smaller SS and two orders of magnitude higher Ion
than SiO2 -only TFETs. Further improvement is expected if the
relative permittivity of the high-k material increases. Fig. 4(b)
shows Iamb as a function of Lhigh-k . Iamb abruptly decreases as
Lhigh-k decreases from 50 to 40 nm. It is explained by the fact
that Iamb is originated from ambipolar behavior at the drain
side. When the high-k material is replaced by silicon oxide
at the drain side, the Iamb of the HG TFET becomes almost
the same as that of the SiO2 -only TFET. Compared with highk-only TFETs, HG TFETs show seven orders of magnitude
lower Iamb .
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[8] A. Vandooren, R. Rooyackers, D. Leonelli, F. Iacopi, E. Kunnen,
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III. C ONCLUSION
HG TFETs have been proposed for high performance and
low-power consumption. In addition, device design has been
optimized by modulating Lhigh-k . By using a local minimum
of Ec at the tunneling junction and placing silicon oxide whose
relative permittivity is low at the drain side, the optimized
HG TFETs showed improved device performance than conventional TFETs such as SiO2 -only and high-k-only TFETs in
terms of Ion , SS, and Iamb .
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Woo Young Choi (S’05–M’10) was born in
Incheon, Korea, in 1978. He received the B.S., M.S.,
and Ph.D. degrees from Seoul National University,
Seoul, Korea, in 2000, 2002, and 2006, respectively.
From 2006 to 2008, he was with the Department
of Electrical Engineering and Computer Sciences,
University of California, Berkeley, as a Postdoctor.
Since 2008, he has been a member of the faculty
of Sogang University, Seoul, Korea, where he is
currently an Assistant Professor with the Department of Electronic Engineering. He has authored
or coauthored more than 80 papers in international journals and conference
proceedings. He is the holder of 10 Korean patents. His current research
interests include fabrication, modeling, characterization, and measurement of
CMOS/CMOS-compatible semiconductor devices and nanoelectromechanical
memory cells.
Prof. Choi was the recipient of the Humantech Thesis Prize from Samsung
Electronics in 2005 and the Doyeon Paper Award from the Inter-University
Semiconductor Research Center, Seoul National University.
Woojun Lee was born in Seoul, Korea, in 1984. He
received the B.S. degree in electronic engineering in
2009 from Sogang University, Seoul, Korea, where
he is currently working toward the M.S. degree in
electrical engineering with the Department of Electrical Engineering.
His current research interests include CMOS and
CMOS-compatible novel device modeling.