Indian Journal of Engineering & Materials Sciences
Vol. 17, June 2009, pp. 175-178
High input impedance first-order allpass, highpass and lowpass filters with
grounded capacitor using single DVCC
Jiun-Wei Horng*
Department of Electronic Engineering, Chung Yuan Christian University, Chung-Li, 32023, Taiwan
Received 5 January 2010; accepted 4 May 2010
A voltage-mode high input impedance first-order allpass, highpass and lowpass filters using one differential voltage
current conveyor (DVCC), one grounded capacitor and two resistors is presented. The allpass, highpass and lowpass signals
can be obtained simultaneously from the circuit configuration. The simulation results confirm the theoretical analysis.
Keywords: Current conveyor, First-order, Allpass filter, Analog signal processing
Current conveyors (CCs) and current feedback
amplifiers (CFAs) are receiving much attention for
their potential advantages such as inherent wider
signal bandwidths, simpler circuitry and larger
dynamic range. Considering these advantages of CCs
and CFAs, several current1 and voltage-mode2-19 firstorder allpass filters using various active components
have been reported. This paper proposes a new
voltage-mode first-order allpass, highpass and
lowpass filters.
Voltage-mode active filters with high input
impedance are of great interest because they can be
directly connected in cascade to implement higher
order filters19, 20. On the other hand, the use of only
grounded capacitor is beneficial from the point of
view of integrated circuit fabrications21. Several
voltage-mode first-order allpass filters using various
active components have been reported. Some circuits
use two active components to realize such a firstorder allpass filter function2-5. However, the active
components they used are not canonical. Some
circuits use one active component and three or more
passive components6-11. However, the capacitors they
used are not grounded. Some circuits use one secondgeneration current conveyor (CCII), one grounded
capacitor and two or three resistors12,13. However,
these circuits have not the advantage of high input
impedance. Several researchers14-17 proposed one
voltage-mode first-order allpass filter using one
differential difference current conveyor (DDCC), one
——————
* E-mail: jwhorng@cycu.edu.tw
capacitor and one resistor. However, these circuits
still have not the advantage of high input impedance.
Metin and Cicekoglu18 proposed a first-order allpass
filter with high input impedance using one modified
CCII, two resistors and one grounded capacitor.
Biolek and Biolkova19 proposed a first-order allpass
filter with high input impedance using one voltage
differencing-differential input buffered amplifier and
one grounded capacitor.
In this paper, a new voltage-mode first-order
allpass, highpass and lowpass filters using one
differential voltage current conveyor (DVCC), one
grounded capacitor and two resistors is presented.
The proposed circuit has the advantage of high input
impedance. With respect to the previous first-order
allpass filters2-19, the proposed circuit employs only
one active component, grounded capacitor and has the
advantage of high input impedance, and two more
filter types (highpass and lowpass) can be
simultaneously
obtained
from
the
circuit
configuration.
The Proposed Circuit
The DVCC22,23 can be characterized by
0
 i y1   0 0
i  0 0
0
 y2  = 
 v x  1 − 1 0
  
 i z  0 0 ± 1
0  v y1 
0 v y 2 
0  i x 
 
0  i z 
… (1)
The CMOS implementation of DVCC is shown in
Fig. 1, which is obtained from Fig. 5 of Elwan and
INDIAN J. ENG. MATER. SCI., JUNE 2010
176
Soliman23. The multiple current outputs can be easily
implemented by adding output branches. The
proposed voltage-mode first-order allpass, highpass
and lowpass filters using one DVCC, one grounded
capacitor and two resistors is shown in Fig. 2. The
voltage transfer functions can be expressed as
Vo1
sC
=
Vin sC + G1
Vo 2
G1
=
Vin sC + G1
R
− sC 2 + G1
Vo 3
R1
=
Vin
sC + G1
… (2)
… (3)
… (4)
From Eqs (2)-(4) it can be seen that a first-order
highpass response is obtained from Vo1, a first-order
lowpass response is obtained from Vo2, and if R2 = R1,
a first-order allpass response is obtained from Vo3.
Because the input terminal of the proposed first-order
allpass filter is connected directly to the y1 terminal
of the DVCC, the input terminal has the advantage of
high input impedance.
Fig. 1—The CMOS realization of DVCC
Sensitivities Analysis
Taking into consideration the DVCC nonidealities, the port relations in Eq. (1) can be
expressed as
v x = β1v y1 − β 2 v y 2 and izk = ±α k ix … (5)
where β j = 1 − ε vj and α k = 1 − ε ik for j = 1, 2 and k
= 1, 2, 3. Here ε vj ( εvj <<1) denotes the voltage
Fig. 2—The proposed DVCC based first-order highpass, lowpass
and allpass filters
tracking errors of the DVCC and ε ik ( εik <<1)
denotes the current tracking error from the x terminal
to the kth z terminal of the DVCC. Reanalysis of the
filter circuit in Fig. 2 yields the following modified
transfer function of Vo2:
Table 1–TSMC SPICE parameters for level 3, 0.35 µm CMOS process
Parameters
NMOS
.MODEL MbreakN NMOS (LEVEL=3 TOX=7.9E-9 NSUB=1E17
+ GAMMA=0.5827871 PHI=0.7 VTO=0.5445549 DELTA=0
+ UO=436.256147 ETA=0 THETA=0.1749684 KP=2.055786E-4
+ VMAX=8.309444E4 KAPPA=0.2574081 RSH=0.0559398
+ NFS=1E12 TPG=1 XJ=3E-7 LD=3.162278E-11 WD=7.046724E-8
+ CGDO=2.82E-10 CGSO=2.82E-10 CGBO=1E-10 CJ=1E-3
+ PB=0.9758533 MJ=0.3448504 CJSW=3.777852E-10
+ MJSW=0.3508721)
PMOS
.MODEL MbreakP PMOS (LEVEL=3 TOX=7.9E-9 NSUB=1E17
+ GAMMA=0.4083894 PHI=0.7 VTO=-0.7140674 DELTA=0
+ UO=212.2319801 ETA=9.999762E-4 THETA=0.2020774
+ KP=6.733755E-5 VMAX=1.181551E5 KAPPA=1.5
+ RSH=30.0712458 NFS=1E12 TPG=-1 XJ=2E-7 LD=5.000001E-13
+ WD=1.249872E-7 CGDO=3.09E-10 CGSO=3.09E-10
+ CGBO=1E-10 CJ=1.419508E-3 PB=0.8152753 MJ=0.5
+ CJSW=4.813504E-10 MJSW=0.5)
HORNG: HIGH INPUT IMPEDANCE FILTERS USING DVCC
177
Vo 2
G1β1 (α1 + α 2 − α 3 )
… (6)
=
Vin sC + G1β 2 (α1 + α 2 − α 3 )
The cutoff frequency is obtained by
β (α + α 2 − α 3 )
… (7)
ωc = 2 1
CR1
The active and passive sensitivities are low and
obtained as
α1
α1 + α 2 − α 3
− α3
α2
ωc
=
; Sα 3 =
;
α1 + α 2 − α 3
α1 + α 2 − α 3
SCω,cR1 = −1 ;
Sαω2c
Sαω1c =
;
S βω2c = 1
Simulation Results
The first-order filters in Fig. 2 were simulated
using HSPICE. The DVCC was realized by the
CMOS implementation in Fig. 1 whereas the aspect
ratios of the NMOS and PMOS transistors are W/L =
3.5 µ /0.7 µ and W/L = 7 µ /0.7 µ , respectively,
using 0.35 µ m MOSFET from TSMC (the model
parameters are given in Table 1). Figures 3(a), (b) and
(c) represent the magnitude and phase responses of
the first-order highpass, lowpass and allpass
responses, respectively, designed with fc = 1.59 MHz:
C = 10 pF and R1 = R2 = 10 k Ω . The power supply
was ± 1.65 V. The bias voltages are Vb1 = -0.25 V
and Vb2 = 0.5 V.
Conclusions
A new voltage-mode first-order filter configuration
using one DVCC, one grounded capacitor and two
resistors is presented. The allpass, highpass and
lowpass filters can be simultaneously obtained from
the same circuit configuration. The proposed circuit
has the advantage of high input impedance. The
simulation results confirm the theoretical analysis.
Acknowledgment
The authors would like to thank the anonymous
reviewers for their constructive criticisms to improve
the manuscript.
References
Fig. 3—Simulation results of the proposed circuit (a) Highpass
filter, (b) Lowpass filter and (c) Allpass filter
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