626
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 4, JULY 2000
Power Factor Correction Converter Using Delay
Control
Kyu-Chan Lee, Student Member, IEEE, Hang-Seok Choi, and Bo Hyung Cho, Senior Member, IEEE
Abstract—A low cost universal input voltage single-controller
power factor correction converter for a 200 W power supply is proposed. It consists of the PFC part followed by a dc-dc converter as
in a conventional two-stage scheme. However a single PWM controller is used as in a single-stage PFC scheme. The switch in the
PFC part is synchronized with the switch in the dc-dc converter
and has a fixed frequency. Employing an adaptive delay scheme,
the PFC switch is controlled to limit the capacitor voltage within a
desired range for optimum efficiency and to reduce input current
harmonic distortion. The design procedures of the delay scheme,
the feedback loop, and experimented results are presented to verify
the performance.
Index Terms—Delay control, personal computer power supply,
single controller power factor correction converter.
I. INTRODUCTION
R
ECENTLY the suppression on line current harmonics and
power factor requirements were being imposed to lower
power level applications. In particular, 200–300 W power supplies in PC’s belong to the IEC-1000-3-2 class D. For the last
several years a great deal of effort has been made to develop efficient and cost effective power factor correction (PFC) schemes.
A number of single-stage schemes were proposed [1]–[4] in
order to improve efficiency and to reduce cost from conventional
two stage schemes, which employ a PFC pre-regulator followed
by a dc–dc converter.
These types of converters operate in discontinuous conduction mode (DCM), which offer inherent capability of the power
factor correction. Because the single switch is controlled by a
conventional PWM control scheme, an additional control circuitry for PFC can be eliminated. However, one of the major
problems in this type of converter is their high capacitor voltage,
which forces the use of the high voltage rating switching device. To reduce the capacitor voltage, a frequency modulation
technique can be employed [5]. In this scheme, the operating
frequency varies over a wide range, and the converter efficiency
is deteriorated. This is particularly true for the power supplies
which have an universal input voltage (90–264 V) and a wide
range of load current specification. Also the switch of the singlestage converter has a large current stress because it carries both
the boost current operating in DCM, and dc–dc converter current. This results in using two or more switches in order to limit
the current stress on the device above 100 W applications.
Manuscript received September 4, 1998; revised December 5, 1999. Recommended by Associate Editor, K. Smedley.
The authors are with the Electrical Engineering Department, Seoul National
University, Seoul 151-742, Korea (e-mail: lkc@plaza1.snu.ac.kr).
Publisher Item Identifier S 0885-8993(00)05565-4.
Also, since the proposed PFC converter operates in DCM, it
has a lower efficiency in comparison with CCM operated PFC
converter. However proposed converter is targeted for PC power
supply, in which the cost should be the most critical factor while
meeting the minimum efficiency requirements. With this constraint, five different PFC converters are used for comparison.
Conventional PFC scheme used boost converter in CCM is excluded due to expensive PFC control IC. First and second converters are single stage PFC converters which are integration
of boost converter in DCM and forward converter, and halfbridge converter in CCM respectively. Third, fourth and fifth
converters are all two stage PFC converters. Third converter is
consisted of the boost converter in critical conduction mode with
frequency control and forward converter in CCM. Fourth converter has the boost converter in DCM with an additional PWM
controller. Fifth proposed converter has a proposed single controller using delay control. The results of trade-off study are
shown in Table I.
This trade-off study shows that a single stage, single-switch
scheme is not a good candidate for the 200 W power supply in a
Personal Computer in terms of efficiency and cost [6]. In order
to overcome the above mentioned problems in single switch circuits, a two switch scheme with a single PWM controller is
proposed. It resembles conventional two stage schemes. However a single PWM controller with an adaptive delay scheme
drives the switches for both the PFC part and the dc–dc converter
part differently to keep the capacitor voltage within the optimal
range and to reduce the input current distortion. In Section II,
the proposed scheme is described and its operating principle is
explained. The design procedure of the delay control scheme
and the loss analysis is summarized in Section III. Section IV
presents the design of the feedback loop for the proposed PFC
converter taking into consideration of the second harmonics of
the input voltage and the input current distortion. In Section V,
selected experimental verifications are presented.
II. OPERATING PRINCIPLES
The circuit diagram of the proposed SC PFC converter employing the delay control is shown in Fig. 1. The converter has
a PFC switch, Q1 synchronized with the switch, Q2 of the cascaded forward converter. The switch, Q2 is controlled to regulate the dc output voltage by PWM controller. The switch, Q1 is
controlled to keep the capacitor voltage within a desired range,
depending on the operating condition and to reduce input current harmonic distortion. As can be seen in Fig. 1 the inputs
of the delay controller are the gate drive signal for Q2 (GS2),
0885–8993/00$10.00 © 2000 IEEE
LEE et al.: POWER FACTOR CORRECTION CONVERTER USING DELAY CONTROL
627
TABLE I
RESULTS OF TRADE-OFF STUDY
Fig. 1.
Circuit diagram of the proposed SC PFC converter
the error amplifier output voltage
.
voltage
and the rectified input
The delay controller adds turn-on delay
and turn-off
to the gate drive signal of Q2(GS2) as can be seen
delay
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 4, JULY 2000
value of error amplifier output voltage where the
Taylor series expansion is done;
and
are constants.
From equation (1)–(3) the boost switch duty ratio is given by
(4)
Fig. 2.
Gate signals for Q1 and Q2
in Fig. 2. The relation between forward duty ratio
can be expressed as
duty ratio
where
control.
is a constant and
is the gain of the turn-off delay
and boost
B. Turn off Delay
(1)
the capacitor voltage can
By controlling turn-on delay
be kept within a desired range, and by controlling turn-off delay
the input current distortion can be reduced.
Also, since the gate signals of the Q1 and Q2 are synchronized, the switch Q1 is protected automatically when the forward converter is protected by alarm signals such as over current
and over voltage. Synchronized operation of the two switches
happens at the no-load condition and the start-up condition.
Therefore the PFC part of the proposed converter does not need
an additional protection scheme and soft start-up circuit which
can reduce the cost and complexity.
A. Turn on Delay
For the DCM boost converter, the boost gain (the ratio of the
bulk capacitor voltage to the peak of the line voltage) should be
kept relatively high in order to make a more sinusoidal current.
The boost gain should be greater than 1.29 to achieve power
factor greater than 0.95 [7]. In that case the capacitor voltage
could be higher than 480 V for universal line voltage. This imposes high voltage stress on the bulk capacitor for high power
factor. So far, some techniques to reduce input current distortion
using variable frequency control or variable duty-ratio control
have been proposed. However, the variable frequency control
method requires wide range of frequency variation and the variable duty-ratio control method needs another PWM controller
and complex control circuit [8].
The line current of the PFC part is expressed as
(5)
Though the boost PFC part operates in DCM for an inherent
PFC capability, if the two switches, Q1 and Q2 operate with
the same duty ratio, the bulk capacitor voltage will increase as
the load current decreases and/or line voltage increases as in a
conventional single-stage PFC converter. For the efficient and
optimum design of the transformer, such a large variation of the
capacitor voltage is undesirable. To keep the capacitor voltage
should
within a desired range, the boost switch duty ratio
be modulated according to the capacitor voltage. By introducing
turn-on delay proportional to the capacitor voltage to the gate
without using
drive signal of S2, it is possible to control
another PWM controller.
In the proposed control method, the error amplifier output
is used as an input of the
voltage of the PWM controller
delay controller instead of the capacitor voltage since the capacitor voltage is given by
is line voltage (instantaneous value) and
is
where
switching frequency.
From equation (5), to make the input current sinusoidal the
duty-ratio of the boost should be
(6)
is a constant. The exact implementation of equawhere
tion (6) requires complex control circuit because it involves the
by
and the square-root function. However,
division of
in the proposed control scheme the bulk capacitor voltage
can be controlled around the peak of the maximum line voltage
in equation (6) can be considered as a
(about 400 V), and
of equation (6) can be approximated as ;
constant. Then,
(7)
(2)
(3)
where
turn ratio of the transformer;
output voltage;
amplitude of ramp of PWM controller;
is the gain of the turn-off delay control. Fig. 3 shows
where
of equation (6) and (7) as a function of rectified line voltage.
As can be seen the plot generated using equation (6) can be
approximated with the linear equation of equation (7) and the
control law of equation (7) can be simply implemented by introducing the turn-off delay proportional to the line voltage. The
can be expressed as
overall control law of
(8)
LEE et al.: POWER FACTOR CORRECTION CONVERTER USING DELAY CONTROL
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TABLE II
SPECIFICATIONS OF THE POWER SUPPLY IN PC
Fig. 3.
D
TABLE III
LOSS BREAKDOWN OF THE PROPOSED 200 W PFC POWER SUPPLY
as a function of line voltage
III. DESIGN PROCEDURES
From the input–output power quasibalance, the design expression for the bulk capacitor voltage can be approximated as
(9)
where
input voltage in rms;
load current;
transformer turns ratio;
inductance;
estimated efficiency.
Using the delay control scheme as shown in Fig. 2,
minimum input voltage with a full load. is given by
at the
(10)
is the minimum variable delay duty ratio by the
where
is the maximum duty ratio for the
delay controller and
optimal efficiency. In order to ensure the DCM operation for all
conditions, it needs to be designed at the minimum input voltage
with full load case, and the DCM condition must be satisfied at
the peak of the input voltage. The condition for ensuring the
DCM operation is satisfied if
(11)
where
is given by
(12)
is the maximum duty ratio for the forward converter at
low input voltage with a full load.
is selected, the desired
Once the value of the product
can be calculated for the DCM condition at the
minimum
minimum input voltage with a full load using
(13)
where
Using equation (13) and the loss analysis, the optimum
and
can be determined. The maximum value of
and corresponding
can be calculated and the
can
at the
be determined by equation (12). For the maximum
and
high input voltage and minimum load, the minimum
can be calculated using equations (9) and
the maximum
(10).
In order to design the proposed converter for optimal efficiency, a loss analysis is performed according to the design specifications shown in Table II. Table III shows the loss analysis
results of 200 W PFC converter at various input voltage.
and affect
, the
As discussed earlier, the values of
peak current in Q1, and efficiency. Fig. 4(a) shows the efficiency
.
at 90 V input with a 200 W load as a function of the
Fig. 4(b) shows the capacitor voltage and the PFC switch Q1
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 4, JULY 2000
(a)
Fig. 6.
Proposed PFC converter model
rectified input voltage and linearizing the square function [10],
which can be expressed as
(14)
(b)
Fig. 4. Simulated efficiencies V dc and Q1 peak current
where
: equivalent load resistance of the forward
converter.
This equation is valid only at harmonic frequencies of the
input voltage. The second harmonic ripples appeared at the
output voltage due to the duty ratio and the input voltage at the
harmonic frequencies can be expressed as
(15)
Fig. 5.
Simulated capacitor voltage at different load
peak current. From the results of the loss analysis in Fig. 4, the
switching frequency is chosen at 62 kHz, and the inductance is
105 uH for the optimal efficiency at 90 V input with a full load.
The resulting capacitor voltage at different loads can be analyzed and the capacitor voltage is between 300 V and 410 V as
shown in Fig. 5.
IV. FEEDBACK LOOP DESIGN CONSIDERATIONS
Fig. 6 shows the proposed Single Controller PFC converter
considering the feedback loop.
In PFC converters with the rectified AC voltage, there exists
voltage ripples of the bulk capacitor at harmonic frequencies
of the input voltage [9]. The amplitude of the ripple voltage can
be calculated by the linearized input-to-output transfer function.
This function can be derived by the fourier transformation of the
is the duty ratio to the output voltage transfer funcwhere
is the input voltage to the output voltage transfer
tion and
function.
In order to regulate the output voltage within the specified
at second harmonic frelimit, the required feedback gain
quency is shown as
(16)
(17)
is the regulation specifiwhere is the line frequency and
cation.
As shown in equation (16), the higher the feedback gain is
selected, the lower the output ripples become. This makes the
duty ratio fluctuated at second harmonic frequency with a large
amplitude. This affects the PFC converter performances such as
the DCM condition and the input current distortion. Using the
harmonic analysis, the instantaneous capacitor voltage and the
duty ratio are approximated as shown in equation (18) taking
the dominant second harmonic component.
(18)
LEE et al.: POWER FACTOR CORRECTION CONVERTER USING DELAY CONTROL
631
Fig. 7. Relations of the feedback loop gain and boundary of the DCM
conditions
where
The reset duty ratio
shown as
of the DCM Boost converter is
(19)
In order to ensure the DCM operation, (20) should be satisfied:
(20)
Fig. 8.
where
Control to output transfer function and loop gain T
results, feedback loop gain and the smallest capacitor size can
be designed. Fig. 8 shows the control to output transfer function
uF and a feedback gain of 0.55.
and loop gain using C1
V. EXPERIMENTAL VERIFICATIONS
Harmonics of the input current of the SC PFC converter with
the feedback loop closed are described in
(21)
Total harmonic distortion (THD) of the line current can be
calculated by the fourier transformation of equation (21). As
shown in equation (20) and (21), DCM condition and THD are
affected by the capacitor size and feedback loop gain.
Fig. 7 shows the relations of the feedback loop gain at second
harmonic frequency and the boundary of the DCM conditions
and THD’s with respect to the capacitor. Using these simulation
A engineering prototype hardware included all auxiliary
circuits is built for the 200 W power supply in a PC which is implemented with the following major components: Q1-IRFP450,
Q2-2SK1217, D1-MUR860, C1-450 V 100 uF, L-105 uH
V secondary
(PQ3220), and TR (EER35 primary 70 turns,
V secondary 9 turns).
4 turns,
The delay control is implemented using one CMOS IC4011,
two transistors, and one op amp as shown in Fig. 9. The inputs of
the delay controller are the gate drive signals for Q2(GS2), and
the output of the feedback control voltage, . As the capacitor
decreases and
increases. The amount
voltage increases,
is thus inversely proportioned to . T1, R1 and T2, R2
of
act as a voltage controlled current source that makes the variable
and turn off delay,
respectively. The op
turn-on delay,
sets the gain of the delay controller.
amp and
632
Fig. 9.
Fig. 10.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 4, JULY 2000
Circuit implementation of proposed delay scheme
Measured capacitor voltages of SC PFC converter
(a)
(b)
Fig. 11.
Measured efficiencies of SC PFC converter
Fig. 10 shows the measured capacitor voltage as a function of
the output power and input voltage. As compared to simulation
results as shown in Fig. 6, the experimental results match well.
Fig. 11 shows the measured efficiencies which satisfy the
specifications as shown in Table II.
Fig. 12. Line current and output voltage ripples (current 5 A/div, output
voltage ripple 50 mV/div).
Fig. 12 shows the rectified line current and output voltage
ripples. As shown in Fig. 12, output voltage ripples and noises
can be maintained within 42 mV which satisfy the specifications
of PC power supply.
LEE et al.: POWER FACTOR CORRECTION CONVERTER USING DELAY CONTROL
633
[7] K. H. Liu and Y. L. Lin, “Current waveform distortion in power factor
correction circuits employing discontinuous-mode boost converter,”
in Proc. IEEE Power Electron. Specialists Conf. (PESC) Record, June
1989, pp. 825–829.
[8] J. Lazar and S. Cuk, “Open loop control of a unity power factor, discontinuous conduction mode boost rectifier,” in Proc. INTELEC’95, 1995,
pp. 671–677.
[9] K.-C. Lee and B. H. Cho, “Design of feedback loop for single controller
power factor correction converter,” in Proc. IEEE PESC’98, May 1998,
pp. 899–904.
[10] M. Nagao, etc., “Analysis of high power factor ac–dc boost converter,”
T. IEE Jpn., vol. 114-D, no. 11, pp. 1139–1148, 1994.
Fig. 13.
Input harmonic current at a high line with a full load.
Fig. 13(a) shows the input harmonic current at a high line with
a full load. Fig. 13(b) shows that proposed power supply is able
to meet the requirements of IEC1000-3-2 Class D.
VI. CONCLUSION
Due to the high current and voltage stresses, a single stage,
single switch PFC converter is not suitable for a 200 W power
supply in a PC in view of the efficiency and the cost requirements. In the proposed converter, the PFC switch and the dc–dc
converter switch are separated for optimum device selection.
The adaptive delay control scheme limits the capacitor voltage
within the optimum range and it reduces the input current harmonic distortion. It is shown that the proposed converter can
reduce the cost compared to the conventional two-stage scheme
meeting all specifications including the IEC 1000-3-2.
REFERENCES
[1] I. Takahasi and R. Y. Igarashi, “A switching power supply of 99% power
factor by the dither rectifier,” in Proc. INTELEC ’91, 1991, pp. 714–719.
[2] M. Madigan et al., “Integrated high quality rectifier-regulators,” in Proc.
PESC’92 Record, 1992, pp. 1043–1051.
[3] R. Red, L. Balogh, and N. O. Sokal, “A new family of single-stage isolated power-factor correctors with fast regulation of the output voltage,”
in Proc. PESC’94, 1994, pp. 1137–1144.
[4] M. Daniele, P. Jain, and G. Joos, “A single stage single switch power
factor corrected ac/dc converter,” in Proc. PESC’96, 1996, pp. 216–222.
[5] M. M. Jovanovic et al., “Reduction of voltage stress in integrated
high-quality rectifier-regulators by vailable-frequency control,” in
Proc. APEC’94, 1994, pp. 569–575.
[6] K. C. Lee and B. H. Cho, “Low cost power factor correction(PFC)
converter using delay control,” in Proc. PCC-Nagaoka’97, 1997, pp.
335–340.
Kyu-Chan Lee (S’97) was born in Seoul, Korea, in
1964. He received the B.S. and M.S. degrees in electrical engineering from Seoul National University in
1987 and 1989, respectively, where he is currently
pursuing the Ph.D. degree.
From 1989 to 1999, he was a Research Engineer
with Hyosung Industries, Co., Ltd., Korea, developing and designing the power electronics system
such as AGV driving system, high power converter
and inverter systems. His research interests include
developing and designing converter topologies and
control methods, power factor corrections, electronics ballast for metal halid
discharge lamp, neon lamp, and CCFL lamp.
Hang-Seok Choi was born in Korea in 1970. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Seoul,
Korea, in 1997 and 1999, respectively, where he is
currently pursuing the Ph.D. degree.
His research interests are in power factor correction converters and soft switching techniques.
Bo Hyung Cho (M’89–SM’95) received the B.S. and
M.E. degrees from the California Institute of Technology, Pasadena, and the Ph.D. degree, from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, all in electrical engineering.
Prior to his research at Virginia Tech, he worked
for two years as a Member of Technical Staff, Power
Conversion Electronics Department, TRW Defense
and Space System Group, where he was involved
in the design and analysis of spacecraft power
processing equipment. From 1982 to 1995, he was
a Professor in the Department of Electrical Engineering, Virginia Tech. He
joined the School of Electrical Engineering, Seoul National University, Seoul,
Korea in 1995, where he is an Associate Professor. His main research interests
include power electronics, modeling, analysis and control of spacecraft power
processing equipment, power systems for space station and space platform,
and distributed power systems.
Dr. Cho received the 1989 Presidential Young Investigator Award from the
National Science Foundation. He is a member of Tau Beta Pi.