ELEC 518: RF/Microwave Circuit Design and Measurement
Lab2: Amplifier Design, Part I
1.0 Overview
This lab combines matching network and some basic amplifier design skills into a
single laboratory. You will use lumped-element components to perform an RF
amplifier design in the 200MHz-1GHz frequency range. Here’s what you’ll be doing:
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Design a single-stage one-port input matching network to the NE68133 BJT
amplifier in schematic. Learn how to tradeoff the bandwidth and gain of the
amplifier.
Learn how to design bias networks for the amplifier.
Learn to include the effects of pad parasitics in the amplifier design.
Create a synchronized layout of the amplifier.
Fabricate and measure the amplifier.
Improve amplifier performance so that it agrees with the original design.
2.0 Design
Group#
1,6
2,7
3,8
4,9
5,10
Amplifier matching network specifications
200-400MHz, S11<-18dB, S21>15dB, (Ic=7mA)
400-500MHz, S11<-20dB, S21>15dB, (Ic=20mA)
500-700MHz, S11<-18dB, S21>12dB, (Ic=10mA)
700-900MHz, S11<-15dB, S21>9dB, (Ic=20mA)
900-1000MHz, S11<-20dB, S21>8dB, (Ic=10mA)
1. Obtain your lab assignment from above Table. The assignment contains
specifications you need to meet when designing the amplifier.
Figure 1. Architecture of the single-stage amplifier.
1
The single-stage amplifier shown in Figure 1 consists of a BJT transistor
NEC68133 for power amplification, input and output matching networks to meet
the design specification, resistors for base and collector biasing and dc-decoupling
capacitors to isolate dc bias of the amplifier from outside world.
2. Open up a new ‘Schematic Window’. Obtain the NEC S-parameters for the BJT
transistor we’re using, the NE68133, from “Component Library” icon.
3. Plot the S-parameters of the NE68133. There are several different files of Sparameters for the same device, but using different bias currents.
Figure 2. An example of ADS simulation schematic for S-parameter of NE68133.
4.
Stability and Gain Analysis:
Before the design of matching networks, stability and maximum available gain
(Gmax) are considered. For an amplifier to be unconditionally stable, the following
conditions should be satisfied:
1 -|S11|2 -|S22|2+|∆|2
K = ------------------------------- > 1
2|S12S21|
2
(1)
|∆| = |S11S22-S12S21| < 1
(2)
where K is stability factor and |∆| is stability measure.
Open up a new ‘Data Display Window’. Type in the following three equations
and plot the simulation results.
Eqn: K=stab_fact(S) ; Stab_measure=stab_meas(S) ; Gmax=max_gain(S)
5. Select a lumped-element matching network topology and complete design of an
input matching network by hand (using a combination of Smith chart and
equations.) Leave the output connected to 50Ω (do not match the output port).
Use the following guidelines when choosing your topology:
a. You should avoid putting parallel (shunt) elements directly next to the
transistor base (input). This is because it is difficult to mount and solder
components very close to the device.
b. You should not put shunt inductors across the base of the transistor. This
will prevent you from biasing the base. Think carefully about how DC
biasing will enter the transistor.
c. Be sure you select discrete values for capacitors which can be synthesized
using parallel or series combinations of our existing capacitor libraries.
Consult the TA and Lab technician for available values.
d. Do not use more than 3 capacitors in combination. The inductance value
can be tuned continuously.
e. Use values of inductances less than 20nH and capacitors less than 100pF.
6. Simulate the design
a. Adjust the design to make it optimally-matched at the design (center)
frequency.
b. First, optimize the input matching network for gain S21 within the
bandwidth and input match specified.
c. Secondly, optimize the input matching network for matching S11 within
the bandwidth and gain specified.
d. You can try the “Optimization” function in ADS (fig. 3).
e. Check for the ‘Stability’ of the network matching.
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Figure 3.
ADS simulation schematic for input matching network by “Optimization”.
3.0 Bias Network and Layout
Because this is the first time you’ve done this, you will separately layout the circuit,
and then add the parasitics of the layout into the schematic manually.
1. Ensure that the PCB parameters you are using are accurate. These parameters
include ε, loss tangent, PCB thickness, and metal thickness.
2. You need to include a length of 5mm pad to solder the components together. Use
εA
the approximate
equation to model the pad capacitance, but multiply by 3 to
d
roughly account for the edge effects.
3. Also leave space for via holes, which are holes you will drill in the PCB to
connect components to ground. Include a parasitic inductance from you Lab 1
measurements to model the via hole wire connection.
4. Include a section of lead transmission line at least 3cm connecting the input and
output of your circuit.
5. Include the SMA connector model from Lab 1 on both ends.
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3.1 Bias network
1. In the middle of the lead transmission lines (both input and output!), attach a
resistor in series with an RF inductor with an impedance greater than j150Ω at the
lower end of the design frequency. For the base bias, use a 1kΩ resistor, and for
the collector, use a 200Ω resistor.
2. Include a gap and pad for the resistor, and a gap for the inductor. Include
parasitics for the pads in your schematic. Attach one end of the resistor to the
transmission line, and one end to first pad, and then attach the inductor in series,
using the first and second pads. On the second pad, solder SIX bypass capacitors
which are connected to ground.
3. Re-simulate your design, including the bias tees and pads. Adjust the component
values to accommodate the effects of the pad. Adjust the bias to account for the
base resistor.
4. Generate a layout file. Follow procedure given by the TA.
Reference:
Total gain of the amplifier = GTO = G S GO G L
Where G S =
1 − ΓS
2
1 − S11ΓS
2
2
, GO = S 21 , G L =
1 − ΓS
2
1 − S 22 ΓS
Unilateral design, assume S12 = 0 , ΓIN = S11 +
S12 S 21ΓL
= S11
1 − S 22 ΓL
Maximum gain of GS : when ΓS = S11*
*
Maximum gain of G L : when ΓL = S 22
1
1
2
S 21
Conjugate matching, GTO =
2
1 − S11
1 − S 22
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2
2