California Eastern Laboratories
AN82901-1
APPLICATION NOTE
Application of Microwave GaAs FETs
9/82
INTRODUCTION
The history of converting microwave communications, as
well as other communications technologies, to solid state
electronics is a long one. Early advances were first made in
receivers, and then in transmitters. Progress in bipolar transistor technology and the production of new semiconductor
crystals during the 1960’s made possible the development of
such new microwave diodes as the GUNN and the IMPATT
(impact avalanche and transit time). For this reason, the
decade might well be called the renaissance of microwave
semiconductor devices. A series of microwave communications amplifiers appeared in the first half of the 1970’s which
used GUNN and IMPATT diodes. They played a leading
role in the trend toward solid state technology. In the middle
of the same decade, a commercially feasible gallium arsenide
field effect transistor (GaAs FET) appeared, and the uses of
this device are still increasing. In the latter half of the 1970’s,
demands grew for systems more reliable than those using
IMPATT and GUNN diodes. Users were demanding greater
reliability, and those engaged in research and development
began working toward this goal. The work is still going on
today.
The demands of the industry turned the emphasis away from
creating new devices to developing competition among manufacturers of semiconductors to produce devices of higher performance and greater reliability. Commercialization of GaAs
field effect transistors led to lower energy consumption and
smaller microwave components and systems. These are still
major concerns today. With new developments in infor
mation, communications and applied microwave systems,
the GaAs FET has become an indispensable item.
1. THE FIELD EFFECT TRANSISTOR (FET)
In 1952, Shockley conceived the structure of the field effect
type transistor and pointed out that it could be used for amplifier devices. Due to manufacturing difficulties, particularly in production technology, the field effect transistor was
little known until the early 1960’s. The level of technology
at the time made it very difficult for people to understand the
importance of the FET. But with the development of planar
technology, the micro wave semiconductor industry grew with
explosive rapidity.
There are three major types of FETS. The simplest of the
three is the junction FET (JFET). Because of its simplicity
and ease of manufacture, the JFET was the earliest to be
produced commercially. It was put on the market about the
same time as the first microwave bipolar transistor.
With the development of semiconductor manufacturing technology and the need for lower energy consumption, the metal
oxide semiconductor FET (MOSFET) appeared. The
MOSFET, like the JFET, was first developed for applications in circuits that demanded high impedance, such as input circuits in analytical instruments. Field effect transistors, particularly the MOSFET, became widely known for
their use as discrete devices in UHF band communications.
However, having focused solely on performance for many
years, nothing in the microwave band appeared on the market which was superior to the bipolar transistor.
Around the time silicon reached its peak as a transistor material, Schottky barrier type FETs made of gallium arsenide
appeared and quickly gained popularity by demonstrating
their high theoretical performance. This new device, known
as the Gallium Arsenide Metal Semiconductor FET (GaAs
MESFET) showed performance far superior to the bipolar
transistor.
This new device provided lower noise and higher gain in
established solid state applications. It also provided high
frequency characteristics previously unavailable from bipolar transistors. It is made by using gallium arsenide (group
III-V); one of the semiconductor com pounds which has been
researched continually since the latter half of the 1960’s.
The electron mobility of gallium arsenide is five to seven
times that of silicon.
Gallium arsenide crystal technology was used to produce
the GUNN, varactor and Schottky diodes, and proved to be
far better than silicon in high frequency performance. A
GUNN diode made of silicon would be inconceivable, so the
appearance of the contemporary GaAs FET contributed
greatly to developing and commercializing the GUNN diode. The reason for this is that even though the GaAs
MESFET is a three terminal device, it is simple in structure
and its performance depends only on the crystal quality.
Advances in crystal technology have made the commercialization of FETs possible.
The GaAs FET is what is generally referred to as a “normally ON” type device. Its basic difference from the
MOSFET is the use of a Schottky barrier at the gate instead
of an oxide layer. This is an extremely important point. In
other words, almost no GaAs FET gates are insulated from
the channels in terms of direct current. Thus, even though
GaAs FETs are called “normally ON” type devices, the maximum gate voltage must be zero. It does not use a dielectric
like the MOSFET, so if a positive voltage is applied at the
AN82901-1
gate, direct current flows through it. Since the gate is a very
small piece of metal (0.5,µ—1.Oµ—2.0µ), the gate electrodes
will fuse completely in almost all cases.
Figure 1 shows the properties of a GaAs MESFET. In almost all cases, a linear amplifier circuit biases the GaAs
MESFET. This applies to other circuits as well, but considering gate bias alone, the range must be from IDSS, i.e.,
VG = 0 V, to IDS = 0 (at pinch off, VG = VP). In this range, the
voltage VDS between the drain and the source has little effect
on the current IDS flowing through the channels. By changing the gate voltage, VG, the drain to source (channel) current can be controlled. Figure 2 shows the transfer characteristics of a GaAs FET with n channels. This FET transfer
characteristic is an important basic parameter in circuit design because it sets the bias conditions and operating point.
The operating point line in Figure 2 is directly related to the
mutual conductance, gm.
Mutual conductance is defined as the ratio of the change in
direct current to the minor change in voltage between gate
sources. This is generally described as the square-law characteristic and is shown in the equation for ID in Figure 2.
1-
ID = IDSS
V GS
VP
2
(1)
When ID in expression (1) is differentiated with
respect to VGS, the result is
dID
2IDSS
=dVGS
VP
1-
V GS
VP
= gm
(2)
and the mutual conductance for each value of VGS can be
obtained.
II. GaAs FET BIAS AND OPERATING POINT
DRAIN CURRENT ( ID )
VG=0
VG = -1 V
-2 V
-3 V
The most important characteristic to consider when designing a bias circuit for small signal GaAs FETs is the previously mentioned transfer characteristic. Generally, two methods can be used to bias a GaAs FET.
1. Dual Power Source Method
Figure 3 shows a bias circuit which uses the dual power
source method. Since the condition
VP < VGS < 0
DRAIN TO SOURCE VOLTAGE ( VDS )
must always apply to a GaAs FET, VGS can be derived from
expression (1)
Figure 1. Typical GaAs FET DC Characteristics
ID
I D = I DSS
V GS
VP
1
2
VGS
=
VP 1 -
ID
I DSS
(3)
2. Self Bias Method (Auto-Bias)
Figure 4 shows the most universal method for reducing
electrical potential between a gate and the source when there
is only one power source. If the source resistance is RS, and
the operating current is ID, then the drop in electric potential caused by RS will be
ID x RS
The actual electrical potential between the gate
and the source will be
VGS = -ID . RS
VP
V P /2
VG
Figure 2. Square-Law Characteristic
0
(4)
AN82901-1
which is negative, so the FET can be turned on. The value
RS is obtained by combining expressions (3) and (4).
RS
=-
VGS
ID
=-
VP
ID
ID
1-
(5)
I DSS
Therefore, these are the basic bias principles.
inductance and care must be exercised when using them at
higher frequencies. Types D and E in Figure 5 require only
one power source. They are compatible with the previously
described method. An advantage of this method is that if
the source voltage should increase for any reason, that increase will be proportionate to the drop in potential caused
by RS, which is connected in series with the source,
RS X ∆ID
BIAS ORDER
IDSS
(a)
VG
BIAS POLARITY
(1) VG
NEGATIVE
VG
(2) VD
POSITIVE
VD
(1) VS
POSITIVE
VS
(2) VD
POSITIVE
VD
(1) VG
NEGATIVE
VG
(2) VS
NEGATIVE
VS
ONLY POSITIVE
VD
ONLY NEGATIVE
VG
VD
ID
VP
0
VGS
VGS
VD
VS
(b)
Figure 3. Dual Source Bias Method
(c)
VS
VG
I DSS
RS = b
a
ID
VD
b
RS
a
RS
ID
VD
(d)
VP
VG
V GS
I D X RS
(e)
VG
Figure 4. Self (Auto) Bias Method
Figure 5. GaAs FET Bias Circuits
Figure 5 shows the five general bias types: A, B, C, D, and
E. Type A is the previously described dual power source
bias method appropriate for use in the higher frequencies.
When directly connecting the source to the ground terminal,
source inductance can be made relatively small. By using
this method, higher gain can be obtained and a lower noise
factor anticipated in the higher frequencies.
All other bias methods insert a bypass capacitor into the
source. Even if the high frequency performance of the bypass capacitors can be guaranteed, there will always be a
loss (tan δ) resulting from the material’s dielectric properties. Even with chip capacitors, there is always some
Here, ∆ID is the increment in drain current caused by the
increment in source voltage.
Drain current increase will be automatically suppressed, due
to the proportionate negative bias on the gate. Generally, if
a single source type (self biasing type) is selected, D is used;
if the only available source is a negative one, then E should
be selected.
Figure 5 shows the order for adding bias when a dual power
source is used. This is to prevent, as much as possible, a
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large current from flowing through the FET. The GaAs FET
being discussed here generally has a high mutual conductance, giving it excellent frequency characteristics. If the
gate voltage is near zero, gm is at a maximum and oscillation
may occur. For this reason, a bias scheme should be adopted
that first applies a negative bias to the gate and then turns on
the drain with a positive bias. There are slight differences
between a bias circuit for a small signal GaAs FET and one
for a power GaAs FET, but the above methods can be considered for both.
Moving one step further, let’s examine a practical bias circuit. It is important to:
1. Obtain the necessary operating voltage and operating
current, and
2. Ensure a high level of stability.
at the center of the bias line and wanders off in some direction, the wave form will be distorted. Also, the amplification
operation will be degraded, and DC will flow through the
gate. In a similar manner, the maximum variation in voltage
between the gate and the source when there is no signal is
∆VGSQ = VGSQ(max) - VGSQ(min)
IQ is a function of both the temperature, T, and VGSQ
IQ = f (T, VGSQ )
If, with a variation in temperature of δT, IQ changes by only
δTQ .
δIQ = ∂IQ . δT+ ∂IQ . δVGSQ
∂T
∂VGSQ
RD
=
and from this
RS
∂IQ . δT - gmδIQ R. S
∂T
I DSS(max)
δIQ (1 + gmRS) =
I DSS(min)
RS
∂IQ .
δT
∂T
is obtained.
If RS = 0, that is, if there is no series resistance, then
I Q(max)
I Q(min)
V P(min)
V P(max)
VGS(max)
VGS(min)
∂IQ . δT = δI (0)
Q
∂T
represents the drift. The bias stability coefficient is defined
as
Figure 6. Possible Bias Points
S=
Figure 6 shows the bias graph, indicating all possible bias
points. Bias will be in the range determined by
VGSQ = IQRS
Given the bias range, the operating point for the maximum
amplitude value, P, and the operating point where there is
no signal, Q can be obtained. The change in IQ from point P
to point Q, or ∆IQ, becomes
∆IQ = IQ(max) - IQ(min)
This shows that with a variation in IQ, the drain voltage will
change only as RD . ∆IQ. If the signal midpoint is not fixed
=
Fluctuation in IQ with respect to RS
Fluctuation in IQ with independent of RS
δ IQ
δIQ (0)
=
1
1 + gmRS
(6)
This means that fluctuation in the entire circuit is reduced by
means of negative feedback due to RS. This effect is particularly important when using small signal FETs.
Figure 7 gives an example of a bias circuit. Since IDSS and
VP often vary between devices, it is important that the bias
circuit can absorb such variation, the optimum operating point
can always be established, and operation is stable regardless
of ambient temperatures. The circuit in Figure 7 is basically
a fixed bias circuit and not a self bias circuit.
AN82901-1
Feedback is applied to the circuit by the insertion of RS into
the source.
If there is no signal, the drain current ID is
i D = IDSS
1
-
vgs
2
(7)
Vp
L1
VR
Vout
+Vcc
C1
RF
Vin
VDD
RS
Rs
KF=
IM=
Figure 7. A Low Cost, Stable Bias Circuit
As stated previously, since the voltage between the gate and
the source is VGS = -IDRS in a self bias circuit, and if ID is
known, RS can be readily determined. In such a fixed bias
circuit as the previously mentioned dual source type, the gate
voltage is selected independently of RS and ID. Thus, it is
understood that the value RS can be higher than that when
using a self-bias circuit, and the stability coefficient S can
therefore be improved.
III.
GaAs FET CHARACTERISTICS AND
APPLICATIONS
In this section, examples and explanations of GaAs FET
applications will be given. The first issue is the argument as
to whether or not the FET is better than the bipolar transistor because of the FET’s cross modulation characteristic.
Discussion will then turn to applications of the small signal
FET and the large signal or power FET.
1. Distortion Factor
The transfer characteristic of a GaAs FET can be approximated using a quadratic equation, as was shown in expression (1). If the transfer characteristic could be perfectly represented by such an equation, then the second harmonic will
increase to its maximum and will actually include the higher
order harmonic components. To determine the value of the
second harmonic for a basic frequency, substitute the total
input voltage and total output current into the equation.
V
4(VGSQ PP)(1+gmRF)
V1V2
2(VGSQ VP)(V12+V22) 1/2(1+gmRF)
Figure 8. Improving the Distortion Factor
Using a Series Feedback Resistance RF
Adding a simple sine wave voltage (Vsin wt) to the nonsignal voltage results in
υgs = VGSQ + Vsin wt
If the expression is rearranged and substituted into the following, then the harmonic distortion KF is
KF =
Relative value of second harmonic
Relative value of fundamental harmonic
=
V
4(VGS - VP)
(8)
V is the maximum amplitude of the signal.
As expression (8) shows, the distortion factor approaches its
minimum as VGSQ approaches zero. However, as the input
signal increases and enters the realm of forward gate bias,
quite naturally the distortion factor increases.
Next, we will consider what happens to the cross modulation (intermodulation) produced when two sine wave signals are amplified at the same time. That is
VGS = VGSQ + VI sin wt + V2 sin wt
Since the output current includes the sum and difference
components of two sine waves, crossmodulation
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+2
.0
6
z
4
+3
3
11
+4
+5
Z Fopt 2
+0.
7
2
10
2.0
0.4
8
0.6
8 GHz
9
11
0
7
6
0
-2.
3
-0.8
-0.6
5
7
8
2
4
.4
9
3
-0
-3
10
2
-0.2
-4
2. Small Signal FET Applications
The first practical and commercially available GaAs FET
was introduced around 1973. Since then, many small signal
amplifying devices with 1µm gate lengths and smaller have
been marketed.
The greatest advantages for these devices are found in the
higher frequency bands. Compared to the silicon bipolar
transistors and tunnel diodes, GaAs FETs are far better
+1.5
5
S2
2
GH
1
12
S11 GHz
2
+0
.4
+0.
6
By applying feedback to the circuit, both the distortion factor
and the bandwidth can be improved. The value of RF will
reduce the total gain only by its relative portion. It is possible to have a wide-band amplifier with a low distortion factor by initially designing the amplifier for high gain and tuning the gain to its optimum level by using feedback.
5
V1V2
(11)
2
2
2(VGSQ VP)(V1+V2) 1/2(1+gmRF)
-1.5
IM=
(10)
(12)
NF is the amplifier noise factor.
G is the amplifier gain.
In single-stage amplifiers, the general procedure for matching input circuits is to mimimize the noise factor, NF; for
matching output circuits, the gain is maximized.
From observations of the input-output impedances of a GaAs
FET, it is noted that there is generally a difference in impedance between maximum gain and minimum NF. This difference is particularly apparent at lower frequencies. As the
frequencies go higher, the difference seems to decrease. The
noise factor, which is a function of device gain, will be low
when the gain is maximized at high frequencies. However,
of the commercially available GaAs FETs having characteristics which allow a gain of 8 to 10 dB or more, there is still
a difference between the impedance at maximum gain and
the impedance at miminum NF. This difference will be seen
until the frequency range approaches the X band.
+1.0
V
KF= 4(VGSQ VP)(1+gmRF)
NF - 1
1 - (1/G)
M+1=1+
1.0
Even here, we see that the distortion factor decreases as bias
is brought closer to VGSQ = 0. The main cause of the distortion is the curve (non linearity) in the transfer characteristic
line, but there are other causes as well.
Distortion can also be caused by the change in output conductance, gd, related to the operating point and the drain
voltage, VDS. To improve distortion, carefully select gm and
gd, which to a certain degree work to reverse this effect.
Another point to consider is that since distortion can be produced internally, KF and IM can both be improved by applying feedback to the circuit.
As shown in Figure 8, by adding a resistance, RF, in series
with the source resistance, the distortion factor for the nonbypass feedback is calculated, using expressions (10) and (11).
6
(9)
4
V1V2
2(VGSQ VP)(V12+V22) 1/2
-1.0
=
+0.8
cross modulation component
fundamental harmonic
0.8
Relative value of
IM = Relative value of
in terms of noise, gain and output-power saturation characteristics. Other than their primary use in ultra-high frequency amplifiers, such as those for electronic countermeasures (ECM), most small signal FET applications are in lownoise amplifiers. They are used in both line-of-sight and
over-the-horizon microwave communications, and in earth
stations communicating with satellites.
A low noise amplifier is designed by minimizing the noise
measure, M, shown in expression (12).
-5
(intermodulation) distortion, IM, is defined as follows:
Figure 9. Frequency Characteristics Of S1l, S22,
and ZFopt in the NE24406
AN82901-1
For these bandwidths, the NF can be reduced to its lowest
absolute value. If the widest possible bandwidth is the objective, then reduction of the NF to its absolute minimum is
not possible throughout the band. In the former amplifier,
the most important consideration is reducing, as much as
possible, the loss in the impedance matching circuit. The
Tchebycheff filter type impedance matching circuit in Figure 10(a) uses a large number of components and is not well
suited for obtaining a low loss matching network.
As Figure 9 shows, both S11 and S22 go from capacitive to
inductive with increasing frequencies. Consequently, S11
and S22 can use the circuit in Figure 10(b) for frequencies
which exhibit a capacitive response, or the circuit of Figure
10(c) for the frequencies which exhibit an inductive response.
In Figure 10(b), for frequencies slightly higher than the
amplifier’s center frequency, the GaAs FET input or output
has a resonance of either L1 or L2 (with a reactance of 0),
which is then matched to the desired impedance by the λ/4
impedance conversion circuit. This is only one of the countless possible impedance matching circuits. However, this is
a very effective design method for low noise amplifiers requiring a band ratio of 10 to 15 percent when the amplifier’s
center frequency is 4 GHz or greater.
Figure 9 shows S11 and S22, indicating input output impedance for the NE24406 and the signal source impedance when
the noise factor, NF, is minimized. Circuits can be matched
using these impedances. As mentioned previously, input
circuit matching is accomplished by matching to ZFopt; and
output circuit matching is accomplished by matching to S22.
In the design of a multi-stage amplifier, the first and second
stages are designed so that (M + 1) will be minimized, and
the third and subsequent stages are made in such a way that
their gain is maximized. Or, alternately, the amplifier can
be designed according to the characteristics determined by
the frequency and the device.
One impedance matching circuit, shown in Figure 10(a), is
the well known Tchebycheff filter type multi-stage impedance matching circuit. The distinctive feature of this circuit
lies in its applicability to the input/output circuits of wideband amplifiers. In many cases, the circuit is used in amplifiers covering the band range 8 GHz to 12 GHz and above.
Although this type of matching network was originally applied to comparatively narrow bands (such as a 500 MHz
bandwidth at 4 GHz), the matching circuits shown in Figure
10(b) and (c) are now believed to be best suited for bands
having approximately a 10 to 15 percent ratio to the
amplifier’s center frequency.
ADMITTANCE
INVERTER
IMPEDANCE
INVERTER
λ/4
λ/4
_ l 34
IMPEDANCE
INVERTER
_ l 23
_ l 34
l
_ l 12
_ l 23
_ l 12
jX12
jX 34
(a)
l2
l1
λ/4
C2
λ/4
λ/4
(b)
Figure 10. GaAs FET Matching Networks
C1
(c)
λ/4
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0.8 mm thickness teflon glass fiber substrate and transistor
leads with lumped constant inductance. Figure 12 shows
the schematics. Figure 13 shows the gain and noise factor
normally obtained using this circuit.
3. Low Noise Amplifiers in the 4 GHz Band
Figure 11 is an example of a two-stage low-noise amplifier
for the 3.7 to 4.2 GHz band using either the NE21889 or the
NE72089. The matching circuit in Figure 11 is based on the
same idea as Figure 10(b). It uses a microstrip with an
THRU HOLES FOR
NE72089 SOURCE LEADS
4 PLACES
CEL
3.7-4.2 GHz LNA
10 pF
10 pF
10 pF
IN
28.0 mm
OUT
69.6 mm
1000 pF
4 PLACES
SHIM STOCK TO GROUND
ALL 4 SOLDER PADS
Parts List: NE72089 FET (2 ea.) California Eastern Laboratories
10 pF Chip Capacitors (3 ea.) ATC #100A-100-J-P-X-50 or equivalent
1000 pF Chip Capacitors (4 ea.) Johanson #50R11W102KP or equivalent
1500 pF Feed-through Capacitors (4 ea.) Erie #2425-003-W5U0153AA or equivalent
Ferrite Beads (4 ea.) Fairrite #2643001301 or equivalent
Figure 11. PCB Layout of a 2-Stage Amplifier in the 3.7 GHz-4.2 GHz Band
Z0
λ/4
TRL2(Z0)
TRL1
Z0
TRL3
C2
λ/4
λ/4
C1
λ/4
λ/4
C4
C5
SST1
C6
C7
λ/4
SST3
SST2
C8 C9 C10 C11 C12
SST4
C13 C14 C15
Vd2
Vg1
Vd1
Figure 12. Schematics for a 3.7 GHz-4.2 GHz Band 2- Stage Amplifier
Vg2
C3
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4.0
3.0
G
20
2.0
NF
3.5
3.7
3.9
4.1
4.3
1.0
4.5
NOISE FACTOR, NF (dB)
GAIN, G (dB)
25
FREQUENCY (GHz)
Figure 13. Frequency Characteristic of NF and G for the
NE72089 2-Stage Amplifier
This two-stage amplifier uses the inductance in the first stage
input section to produce resonance. Then, using the λ/4
impedance transformer, it forms a matching circuit for the
50Ω characteristic impedance. Since there is a relatively
small difference in values between S11and S22, the intermediate stage matches impedance by the simple means of a
transmission line.
Output matching is done in the same way as in the first step,
i.e., the matching circuit shown in Figure 10(b) is used. Figure 11 is a full-scale pattern showing lines and open stubs
inserted in parallel. Although these are not necessary for
the ideal design, they are included to correct impedance
matching problems caused by the printed circuit board connectors (microstrip to coaxial connection) and the DC blocking chip capacitors. They are inserted after the design is
completed.
4. Low Noise Amplifiers in the 1 GHz Band
Figure 14 shows a PCB layout for an amplifier designed for
low noise operation in the 1 to 1.4 GHz band. Since the
microstrip lines used are very thin, the diagram shown here
is twice the actual size. During the design, it should be drawn
four times the actual size and then reduced.
Figure 15 shows the equivalent circuit. In the design of this
circuit, a band ratio of 10 to 15 percent was not obtained as
with the previous amplifier. Instead, emphasis has shifted
to making the band as wide as possible and the noise factor
as low as possible. Since it is in the relatively low-frequency
1 GHz band, the loss due to the reactance elements (including the microstrip) was not given much concern. The
Tchebycheff filter type multi-stage impedance matching circuit could have been used. However, considering the frequencies involved and the large physical size of such a circuit, a method was chosen that gives the transmission line
as high an impedance as possible for input and output, and
which would gradually match to the characteristics impedance of 50Ω. Figure 16 shows the typical performance characteristics of this amplifer.
77 Ω
70 Ω
70Ω
120 Ω
120 Ω
2SK281
4 pF
70 Ω
70 Ω
85 Ω
1.8 pF
94 Ω
74 Ω
Figure 15.
70 Ω
60 Ω
Equivalent Circuit for a NE72089
Low-Noise Amplifier
4.625 cm
GAIN,G (GHz)
OUT
IN
G
4
20
3
16
2
12
8
1.1
NF
1.2
1.3
1
1.4
1.5
NOISE FACTOR, NF
24
THROUGH-HOLES
FREQUENCY (GHz)
0.85 cm
MATERIAL 0.8 mm THICK TEFLON GLASS
Figure 14. PCB Layout for 1.0-1.4 GHz Amplifier
Figure 16. NE72089 Low-Noise Amplifier
When this amplifier was designed, a 4 pF blocking chip capacitor was used as part of the matching circuit, as shown in
Figure 15. The input matching circuit was designed chiefly
AN82901-1
to obtain matching for the noise factor. The data used for
the NE72089 is shown below:
f
1 GHz
1.3 GHz
ΓFopt*
Fmin
G
0.59<32.5
0.6dB
17.5 dB
0.65<47.0
0.6 dB
15.0 dB
VDS = 3 V, IDS = 10 mA
NF @ 50 Ω
1.73 dB
1.74 dB
*(I' Fopt signifies the reflection coefficient obtained when comparing the
signal course impedance with 50 Ω when NF is minimized)
The bias circuit used to actuate this amplifier is shown in
Figure 17. The figure shows a bias circuit for a two-stage
amplifier. For a single stage amplifier, only one half of the
redundant portion of the circuit would be used. This circuit
is a constant voltage, constant current type bias circuit, one
of the most applicable examples of circuits for use in smallsignal amplifiers.
DUAL
5. Applications to Other Amplifiers
(A) A technique of attaining wide band performance by
inserting a source inductance.
L. Neven, et al., have proposed a type of feed back circuit for
relatively low frequency GaAs FET amplifiers. For amplifiers operating in the 1 GHz to 2 GHz range, these circuits
guarantee a low noise factor as well as good input-output
impedance.
Figure 18 shows what is considered the universal GaAs FET
equivalent circuit. In this circuit, drain noise current, Idn, is
referred to the input by the Vander-Ziel theory, then the gate
source resistances, Ri, becomes noiseless and, RS remains
noisy. The noise currents at the gate and drain have been
removed from the two-port. The circuit in Figure 18 is better handled by computers, where the noise and signal are
compared as a function of the externally added source inductance. In this instance, it is easier to consider the equivalent circuit shown in Figure 19.
2N3643
15V
15V
POWER
SUPPLY
330
330
1
R2
500
2 A1
(3V)
15V
R3
500
(3V)
100K
(3V)
100K
4.7µF
1
2 A1
4.3K
1
V DS2
100K
100K
10K
R1
500
(3V)
V DS1
V GS1
2 A2
6.8V
2 A2
4.3K
V GS2
6.8V
3.3K
.01µF
1
.01µF
3.3K
6.8V
2.2K
100K
100K
5.6K
A1 AND A2: 747 DUAL OP-AMP
ALL RESISTORS: 1/4 Watt
Figure 17. Two Stage GaAs FET LNA Bias Supply
LG
RG
Rd
Cgs
en
Ld
+
Ci
Ri
-
gd
g mV
I dn
IC
Cds
RS
Iu
NOISELESS
TWO-PORT
LS
LS '
EXTERNAL SOURCE INDUCTANCE
Figure 18. Universal GaAs FET Equivalent Circuit
EXTERNAL SOURCE INDUCTANCE
Figure 19. Cascade Connection of Device's Noise
and S-Parameter Circuits
AN82901-1
Figure 19 shows the cascade connections of the device’s noise
and S-parameter equivalent circuits. The circuit should be
10.6 nH
10 nH
0.13
pF
NOISE FACTOR, NF (dB)d GAIN, G (dB)
1.5 nH
11.4
nH
0.8 pF
13
G
12
11
SWR
8
ISWR
6
2
1
1.0
NF
4
2
OSWR
1.2
1.4
1.6
designed so that matching is obtained for the input-output
impedance given to this equivalent circuit. After the design
goals have been chosen, the noise figure, NF, and impedance
matching networks are calculated. The circuits and characteristics of an amplifier designed by this method are shown
in Figures 20(a) and 20(b).
1.8
(B) Ultra-wide band amplifiers using GaAs FETs.
The method normally used to achieve wide-band amplification involves applying negative feed back to the transistor.
This method improves the VSWR and dynamic range characteristics and also ensures very flat gain response. Another
method for achieving wide-band amplification involves using a balanced amplifier design which ensures good VSWR.
This method is widely used in applications that cover frequency ranges of one to several octaves in the higher frequency bands. However, it is difficult to obtain a very wide
band using a 3 dB, 90° coupler while also trying to ensure
good input-output VSWR in ranges exceeding 10 octaves, or
in the low frequency ranges. Figure 21 shows an equivalent
circuit for the balanced amp.
2.0
FREQUENCY (GHz)
(a)
IN
3 dB, 90˚
3 dB, 90˚
Figure 20(a). Lumped Element Matching Network
Zo
AMPS (BOTH ARE
THE SAME)
λ 4 @ 1.5 GHz
60 Ω
10 n H
10 n H
Zo
GAIN, G (dB)
1.5 n H
Figure 21. Balanced Amplifier Allowing
Wide-Band Amplification
15
14
G
13
4
ISWR
SWR
NOISE FACTOR, NF (dB)
12
3
2
OSWR
2
0
1.3
1
NF
1
1.4
1.5
OUT
1.6
1.7
FREQUENCY (GHz)
(B)
Figure 20(b). Transmission Line Matching Network
The use of GaAs FETs with negative feedback is an effective
method of ensuring low cost and simplicity for bandwidths
exceeding 10 octaves.
Figure 22 shows the basic circuit for negative feedback amplifiers. For the sake of simplicity, the DC bias circuit and
the coupling capacitors have been omitted. If the characteristics of the GaAs FET to be used are suitable at frequencies
of 10 MHz to 2 GHz, the device’s parasitic elements will be
small in size, and the equivalent circuit can be simplified to
that shown in Figure 23. The simplified equivalent circuit
shown in Figure 24 is obtained by adding the negative feedback resistor shown in Figure 22 to the circuit in Figure 23.
The S-parameters may now be calculated for this situation.
AN82901-1
2
gmZ 0
S 11 = 1 1 ∆
R 2(1 + gmR1 )
R2
OUT
IN
(14)
2
gmZ 0
S 22 = 1 1 ∆
R2 (1 + gmR1 )
R1
S12 = 1
∆
Figure 22. Basic Feedback Amplifier Circuit
2Z0
R2
(15)
(16)
-2gm Z0
2R0
S21 = 1
+
∆ 1 + gm R1
R2
(17)
DRAIN
GATE
2
gm Z 0
2Z0
+
∆ =1+
R2 (1 + gm R1)
R2
gm V gs
V gs
SOURCE
Assuming that a negative feedback amplifier must improve
VSWR, the input and output reflection coefficient must be
0, then expressions (14) and (15) become
Figure 23. Equivalent Circuit for GaAs at Low Frequency
S11 = S22 = 0
The admittance matrix can be determined by using the
following expression.
From this, the following expression can be derived:
1 + = g m R1 =
I1
=
I2
I1
1
R2
1
R2
gm
1 + gmR1
1
R2
(13)
(18)
S21 =
Z 0 — R2
Z0
(19)
S12 =
Z0
R2 + Z 0
(20)
Then, using expression (18), R1 is obtained as follows
Vg
Vg
R2
When expression (18) is substituted into expressions (16)
and (17), the following results are obtained
I2
R2
gm
V1
1
R2
V1
V2
g m Z 02
2
V2
R1 =
Z0
–
R2
1
gm
(21)
R1
Figure 24. Simplified Feedback Amplifier
Equivalent Circuit
If at this time, the input-output for Figure 24 is terminated
at Z0, the S matrix can be easily obtained by using expression (13).
Since the transconductance, gm, in a GaAs FET is not usually large enough, the equation S11 = S22 = 0 will not be
satisfied. However, the range of the gm values needed to
satisfy the expression can be calculated. If R1= 0 then
S21 = I - gmZo
(22)
AN82901-1
is obtained, and thus
300
(23)
250
For example, consider the design of an amplifier with 10 dB
gain. Logically, if we take the input output VSWR as a low
value and the characteristic impedance, Z0, as 50Ω, when
S11 = S22 = 0, then substituting this in expression (23) yields,
1 - (-3.16)
50
= 0.082 S
It will therefore be acceptable if gm⊕83mS. Figure 25 shows
the characteristics of an ultra wide band amplifier designed
using this method.
NOISE TEMPERATURE, T (K)
gm| min = 1 - S21
Zo
200
12GHz
150
100
4GHz
50
0
100
150
200
250
300
350
GaAs FET OPERATING TEMPERATURE, Ta (K)
GAIN, G (dB)
8
Figure 26. Te vs. Ta for the NE67383/NE71083
6
4
2
0.01
0.1
10
1
FREQUENCY (GHz)
Figure 25. GaAs FET Feedback Amplifier
6.
Relation of Ambient Temperature, Frequency
and Noise Temperature in GaAs FETs
Up to this point, only the applications of GaAs FETs in amplifiers have been examined. Now, the discussion will turn
to the relationship between ambient temperature and noise
temperature.
Noise in a GaAs FET is chiefly thermal noise. Since there is
rarely shot noise, the noise temperature in an amplifier
changes greatly in response to the ambient temperature. Figure 26 shows the relationship of operating temperature and
the noise temperature for the NE67383/NE71083. The noise
temperature, Te and ambient operating temperature, Ta, can
be shown to correspond to the following:
Te = K
ωCgs
TA
gm
(24)
Figure 26 shows the linearity in the relationship between the
ambient operating temperature and the noise temperature.
By taking advantage of this characteristic, a super low-noise
amplifier can be produced by cooling the amplifier with carbonic gas, liquid nitrogen or liquid helium.
7. Power GaAs FET Applications
For the small signal GaAs FETs discussed so far, we have
covered only those signal levels in the range in which operating characteristics are not dependent on signal voltage or
signal current. In other words, each terminal’s voltage and
current was in a range which satisfied a linear relationship.
As the signal level increases, this relation- ship is no longer
satisfied and we have a situation known as large signal operation. Of course, even if the element is in non-linear operation, the electrophysical quantity of the signal frequency
is still in a linear relationship if non-linearity is small. Thus,
the S-parameter relationship in a GaAs FET can be determined for small signal operation.
Because the voltage and current-to-terminal conditions which
define each parameter are not fixed for large signal operation, it is difficult to determine parameters indicating a linear relationship.
Figure 27 is a simplified diagram showing the small and
large signal operation of a Class A GaAs FET. Load lines A
and B indicate the optimum conditions for maximum input
and output when the input gate signal voltage is VGA and
VGB.
The optimum load for small signal operation is equal to the
drain conductance (∂IDS /∂VD). In large signal operation,
however, the input signal level will increase and gate voltage, VG, will enter the nonlinear zone. The output current,
which is the drain current, ID, will then reach its upper limit
and the load line gradient must increase to increase the output power. Therefore, when designing a circuit, it is necessary to use data which takes all factors into consideration.
AN82901-1
I DS
VG =0
B
iD
i DB
A
P
i DA
VGB
VGB
t
t1
VDS
t1
VD
VDA
VDB
t
Figure 27. Simplified Load Line for a Class A GaAs FET in Small and Large Signal Operation
8. Operating Methods for Power GaAs FETs
taken at this time since the amount of gate current has a
bearing on whether or not the FET will be destroyed.
10
5
0
5
30
20
1.3
1.2
1.1
10
20
DRAIN CURRENT (mA)
OUTPUT, Pout (dBm)
10
GATE CURRENT (mA)
(A) Introduction
An important factor to consider when working with Power
GaAs FETs is power GaAs FETs are basically a group of
small signal GaAs FETs connected in parallel so that they
can handle a large power source. Therefore, they have an
extremely high transconductance. Another important and
necessary factor to consider is at which bias point operation
takes place. Consideration must be given as to whether there
is adequate bias resistance to suppress the gate current. As
mentioned previously, Schottky gates are used in a GaAs
FET, and there is the possibility that the operating point will
cause an excessive current to flow across the gate.
The gate structure in a GaAs FET is very delicate, with a
typical gate length of 0.5/µm to 1.0µm. In some cases, just
a slight current flow across the gate will have a current density of 106A/cm2. With such high current density, the gate
will eventually fail.
Figure 28 shows the change in input-output characteristics
due to the increasing gate current. Here, the operating drain
voltage is constant, but direct current begins to flow in the
opposite direction at the gate when the input signal level is
increased sufficiently. When the input signal power increases,
the Schottky gate is biased in the forward direction and gate
current begins to flow in that direction. Caution must be
30
INPUT, Pin (dBm)
Figure 28. Relationship of Input-Output Characteristics to
Increasing Gate Current
AN82901-1
One thing that is very basic when biasing power GaAs FETs
is the need for increased impedance of the gate bias circuit.
The example in Figure 29 shows a type of feedback circuit
incorporating a resistor in series with the bias circuit which
produces a drop in potential when the current across the gate
begins to increase, and adds to the gate series bias. By inserting a low pass filter, such as an RFC or capacitor, unnecessary oscillation or phase shift will be prevented.
Another important factor is the order in which bias is applied. It is generally disadvantageous, both thermally and
electrically, to self-bias a power GaAs FET. Therefore, a
positive and negative dual power source should be used to
bias the drain and gate separately. For a GaAs FET, maximum current will flow when the gate voltage is at zero. With
a high output level FET, IDSS is sometimes greater than several amps and since typical gm is extremely high, oscillation
will occur and the FET will be destroyed either thermally or
electrically. For this reason, any appreciable flow of high
current must be prevented from reaching the drain. The
bias method used must be one whereby negative voltage is
applied to the gate first, after which positive voltage is applied to the drain. The following is a detailed example of
this method.
(1) Add a negative potential to the gate which is
close to -5V or to the pinch off voltage.
(2) Specify the drain voltage in such a way that
it moves as rapidly and smoothly as possible from zero volts
to the preset VD. If there is no possibility of a surge voltage
being produced and the drain voltage is completely stable,
add the preset voltage instantaneously.
Figure 30 gives three recommended bias circuits for biasing
power FETS. Figure 30(a) is an excellent bias circuit because there are no limitations requiring that either positive
or negative voltage be applied to the circuit first. Drain voltage, VD, will reach its preset value according to the time
(B) Bias Circuits
Table 1 shows the maximum allowable gate current for
each of NEC’s high power GaAs FETS. Care should be
taken at all times when planning bias circuits and input power
to ensure that these values are not exceeded.
NE8001
NE8002
NE8004
NE8008
NE3716
NE9000
NE9001
NE9002
NE9004
NE9008
NE8681
NE8682
NE8684
NE8688
NE8691
NE8692
NE8694
3.0 mA
6.0 mA
10.0 mA
15.0 mA
20.0 mA
0.5 mA
1.3 mA
2.6 mA
5.0 mA
8.0 mA
3.0 mA
6.0 mA
10.0 mA
15.0 mA
1.3 mA
2.6 mA
5.0 mA
Table 1: Maximum Allowable Gate Currents for the NEC
Power GaAs FET Series
R 1000 pF
V
1
µF
RFC
TO GATE
4.7 pF
VR
Figure 29. Example of a Gate Bias Circuit
VD
V
STABILIZED
V
VD
STABILIZED
V
V G STABILIZED
V
VD
V
-
R
+
D1
C
VG
VG
V
(a)
Figure 30. Power GaAs FET Bias Circuits
(b)
(c)
AN82901-1
Q3
.1 2W
A
VDS
+
S1A
2A
+
4
9
5V
2K
R1
20K
Q2
1K
.0003
47µF
S1B
330
+
.001
7
8
22
10
2.4K
.01µF
6
7
5
8
3
10µF
10µF
+
5
IC1
6.8K 2
POWER
SUPPLY
Q1 - SK3448
Q2 - 2N706
Q3 - 2N3771
IC1- MC1469
IC2-LM304
6
100
Q1
10µF
DUAL
±15V
3
1
IC2
R2 R3
500 33
2
.0003
1
9
+ 47µF
VGS
2.5K
NOTE: 1) Ammeter is optional.
2) Q3 is mounted on external heat sink.
3) R1, R2 and R3 are mounted externally.
4) All resistors are 1\4 watt unless otherwise noted.
Figure 31. Power GaAs FET Regulated Bias Supply
constant determined by C and R. When the power source is
OFF, the electrical charge will pass through diode D1, and
return quickly to the power source side, thus the FET can
then be safely biased.
Figure 31 shows a bias circuit recommended for biasing a
multistage (5 stages) power GaAs FET amplifier.
9. Examples of C-Band Application Circuits Using NEC’s
Power GaAs FET Series
With the exception of the devices with the 96 package, NEC’s
C-Band GaAs FET series using multiple chips contain internal matching network (IMN) circuits within the packages.
The IMNs are not intended to match the devices to 50Ω but
to facilitate and reduce the external matching networks. The
GaAs FET series which are in 98 packages have both input
and output matching circuits close to VSWR, 1:2.5. The
devices in 95 and 98 packages which have internal matching circuits are identified by the numbers -4, -5, (-5H), -6,
-7, (-7H), and -8. Each of these numbers indicates the
center frequency at which the IMN circuit is optimized and
tested. For example, -4 is at 4 GHz (3.5-4.5 GHz) and -6 is
at 6 GHz (5.5-6.5 GHz).
Figures 32 to 68 relate typical characteristics and illustrate application circuits using an 0.8mm thick teflon glass
circuit board. The units used in these charts are millimeters
(mm). Figure 69 gives AM-PM conversions for NE800,
NE371, and NE868 series. This data is particularly effective when designing a PCM transmitter. Figure 70 gives the
standard characteristics for the third order intermodulation
of NE800898-7H and NE868898-6.
This brief report explains current GaAs FET technology.
Improvement of device characteristics is a major goal for
both applied technology and research in electronics. GaAs
FET reliability has already been confirmed and there is little
doubt that FETs will eventually be used at frequencies of 40
GHz and higher.
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
28
P in = 18 dBm
20.0
20.0
3.0
4.0
26
Pout (dBm)
2.1
17.0
3.0
3.0
3.0
f = 5.5GHz
24
22
20
12
14
16
4.9
5.0
5.1
18
20
Pin (dBm)
22
24
5.4
5.5
Figure 32. NE800196, 5 GHz Circuit
5.2
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
5.3
28
= 18 dBm
P in
IN
OUT
26
20.0
2.0
4.0
2.1
17.0
f = 6.5 GHz
24
22
4.0
4.0
9.0
Pout (dBm)
4.0
20.0
20
12
14
16
18
20
22
24
6.3
6.4
6.5
Pin (dBm)
6.0
5.9
6.2
6.1
Figure 33. NE800196, 6 GHz Circuit
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
30
28
Pout (dBm)
OUT
IN
20.0
20.0
3.0
f = 6.5GHz
26
24
2.0
5.0
4.0
2.1
17.0
P in = 22 dBm
2.0
22
4
16
20
18
22
24
26
6.3
6.4
6.5
24
26
28
4.0
4.1
4.2
Pin (dBm)
5.9
6.0
6.1
6.2
f (GHz)
Figure 34. NE800296 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
34
32
IN
20.0
20.0
4.0
f=4.2GHz
30
28
2.1
3.0
26
3.0
5.0
4.0 2.0
17.0
Pout (dBm)
OUT
P in=25 dBm
24
16
18
20
22
Pin (dBm)
3.6
3.7
3.8
3.9
f (GHz)
Figure 35. NE800495-4 Circuit
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
34
P in = 25 dBm
OUT
IN
32
20.0
Pout (dBm)
20.0
3.0
30
f = 5.5 GHz
28
26
4.0
4.0
17.0
2.1
4.0
4.0
5.0
24
16
18
20
22
Pin (dBm)
24
26
28
4.4
4.5
4.6
4.7
f (GHz)
4.8
4.9
5.0
Figure 36. NE800495-5 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
34
OUT
IN
P in = 26 dBm
20.0
20.0
32
30
f = 6.5 GHz
28
17.0
2.1
4.0
3.0
Pout (dBm)
5.0
3.0
26
24
16
5.9
Figure 37. NE800495-6 Circuit
18
20
6.0
6.1
22
24
Pin (dBm)
26
28
6.3
6.1
6.3
6.2
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
34
OUT
IN
11.0
2.0
3.0
f = 7.2 GHz
28
3.0
26
Figure 38. NE800495-7 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
24
16
18
20
6.6
6.7
6.8
24
22
Pin (dBm)
26
28
7.0
7.1
7.2
22
24
Pin (dBm)
26
28
8.2
8.3
8.4
6.9
f (GHz)
34
OUT
20.0
32
20.0
4.0
Pout (dBm)
Pin = 26 dBm
30
f = 8.4GHz
28
2.1
8.0
4.0
4.0
8.0
3.0
4.0
17.0
30
2.1
17.0
3.0
P in = 26 dBm
2.0
3.0
Pout (dBm)
5.0
4.0
5.0
3.0
2.0
32
20.0
20.0
26
Figure 39. NE800495-8 Circuit
24
16
18
20
7.8
7.9
8.0
8.1
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
38
P in = 29 dBm
OUT
IN
14.0
5.0
10.0
Pout (dBm)
3.0
34
2.1
f = 4.2GHz
32
4.0
17.0
36
20.0
4.0
20.0
3.0
30
22
24
26
28
30
32
34
4.1
4.2
4.3
Pin (dBm)
Figure 40. NE800898-4 Circuit
3.7
3.9
3.8
4.0
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
38
P in
OUT
IN
36
20.0
6.0
3.0
11.3
34
3.0
3.0
32
2.1
17.0
f = 5 GHz
Pout (dBm)
4.0
20.0
1.0
3.0 6.0
= 29 dBm
30
22
26
24
28
30
32
34
4.8
4.9
5.0
30
32
34
5.4
5.5
5.6
30
32
34
6.3
6.4
6.5
Pin (dBm)
4.4
Figure 41. NE800898-5 Circuit
4.6
4.5
4.7
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
20.0
Pout (dBm)
17.0
10.0
36
2.0
=29.5 dBm
34
32
1.0
4.0
2.1
2.0
P in
f = 5.5 GHz
2.1
3.0
2.0
20.0
5.0
17.0
38
OUT
IN
30
22
1.0
24
26
28
Pin (dBm)
Figure 42. NE800898-5H Circuit
5.0
5.1
5.2
5.3
f (GHz)
MATERIAL -TEFLON GLASS
38
THICKNESS: 0.8mm
IN
OUT
20.0
36
Pout (dBm)
2.0
34
f = 6.4 GHz
2.1
2.0
1.0
2.0
17.0
P in = 29.5 dBm
20.0
32
30
22
24
26
28
Pin (dBm)
Figure 43. NE800898-6 Circuit
5.9
6.0
6.1
6.2
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
38
OUT
IN
3.0
Pout (dBm)
7.0
9.0
34
f = 7.2 GHz
32
2.1
17.0
P in = 29.5 dBm
36
20.0
2.0
20.0
6.0
30
28
22
26
24
Figure 44. NE800898-7 Circuit
28
30
32
34
7.0
7.1
7.2
Pin (dBm)
6.6
6.7
6.8
6.9
f (GHz)
OUT
IN
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
38
20.0
P IN = 30 dBm
36
Pout (dBm)
5.0
2.0
2.0
2.0
3.0
5.0
2.0
2.0
20.0
1.5
34
f = 7.4 GHz
2.1
3.0
17.0
32
30
22
24
26
28
Pin (dBm)
30
32
34
7.2
7.3
7.4
7.5
f (GHz)
7.6
7.7
7.8
Figure 45. NE800898-7H Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
38
IN
OUT
36
20.0
3.0
20.0
3.0 4.0
Pin = 30.5dBm
3.0
2.0
34
f = 8.4GHz
32
2.1
17.0
Pout (dBm)
10.0
30
28
22
Figure 46. NE800898-8 Circuit
24
28
26
30
32
34
8.2
8.3
8.4
Pin (dBm)
7.8
7.9
8.0
8.1
f (GHz)
IN
OUT
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
40
P in
20.0
38
Pout (dBm)
3.0
12.0
36
f = 4.2 GHz
34
5.0
2.1
5.0
4.0
7.0
4.0
17.0
3.0
= 31.5 dBm
20.0
32
24
26
28
30
32
34
36
4.1
4.2
4.3
Pin (dBm)
Figure 47. NE371698-4 Circuit
3.7
3.8
3.9
4.0
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
40
OUT
IN
Pout (dBm)
f = 5.5GHz
36
34
32
2.0
3.0
2.1
17.0
38
3.0
10.0
3.0
7.0
P in = 32 dBm
20.0
3.0 3.0 4.0
20.0
30
24
26
28
30
32
34
36
5.3
5.4
5.5
Pin (dBm)
3.0
10.0
4.9
5.0
5.1
5.2
f (GHz)
Figure 48. NE371698-5H Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
40
OUT
P in = 32 dBm
3.0
4.0
3.0
f = 6.5 GHz
36
34
2.1
17.0
38
Pout (dBm)
7.0
8.0
5.0
20.0
3.0 3.0
4.0
20.0
32
30
24
26
28
30
32
34
36
6.3
6.4
6.5
32
34
36
7.0
7.1
7.2
32
34
36
7.5
7.6
7.7
Pin (dBm)
Figure 49. NE371698-6 Circuit
5.9
6.0
6.1
6.2
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
40
OUT
P in = 32.5 dBm
20.0
3.0
38
3.0
2.1
17.0
4.0
Pout (dBm)
7.0
5.0
20.0
4.0
f = 7.2 GHz
36
34
32
30
24
26
28
30
Pin (dBm)
Figure 50. NE371698-7 Circuit
6.6
6.7
6.8
6.9
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
OUT
20.0
40
P in = 32.5 dBm
20.0
38
Pout (dBm)
4.0
36
f = 7.7 GHz
34
2.1
17.0
2.0
2.0
3.0
4.0
3.0
32
30
24
26
28
30
Pin (dBm)
Figure 51. NE371698-7H Circuit
7.1
7.2
7.3
7.4
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
30
Pin = +17 dBm
IN
30
14
3.5 3 4 3.8
6
10.5
21
5
2
9
Pout (dBm)
OUT
20
f = 4 GHz
10
0
Figure 52. NE868196, 4 GHz Circuit
3.5
10
Pin
20
(dBm)
4.5
4
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
30
P in =17 dBm
20
8.5
20
f = 5 GHz
10
6.5
2
15
7
3
Pout (dBm)
3.5
10
Figure 53. NE868196, 5 GHz Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
0
10
4.5
5
5.5
P in = +17 dBm
8.4
4
Pout (dBm)
2.6
6.5
6.8
5.2
2
15
f (GHz)
30
20
8.3
20
Pin (dBm)
f = 6 GHz
20
10
0
10
20
Pin (dBm)
5.5
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
11.5
20
f = 7.2 GHz
VDS = 9 V
ID = 125 mA
6
Pout (dBm)
Pin =+ 17 dBm
3.5
3
5
2
15
6.5
30
20
10.5
6
f (GHz)
Figure 54. NE868196, 6 GHz Circuit
10
0
10
20
Pin (dBm)
6.5
Figure 55. NE868196 Test Circuit (6.5 GHz and 7.5 GHz)
7
7.5
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
OUT
8.5
6.5
2
11.5
2
30
Pin = 22 dBm
6
9.5
2
4
15
9
Pout (dBm)
30
21
40
f = 4 GHz
20
10
20
30
Pin (dBm)
Figure 56. NE868296, 4 GHz Circuit
4
3.5
4.5
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
3.5 3
8.5
5
9
9.5
6
30
5.5
5
10
2
21
20
30
4
Pout (dBm)
IN
40
Pin = 22 dBm
f = 5 GHz
20
10
20
30
Pin (dBm)
Figure 57. NE868296, 5 GHz Circuit
4.5
5
5.5
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
OUT
6.5
2.5
2
7.5
2
30
Pin = 22 dBm
5
6
2
4
2
Pout (dBm)
20
15
40
f = 6.5 GHz
4
20
10
20
30
Pin (dBm)
Figure 58. NE868296, 6 GHz Circuit
5.8
6
6.2
6.4
6.6
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN
3
30
4
8.7
6.5
2.7
6.7
2
3
Pout (dBm)
OUT
20
3 4.5
15
40
Pin = 22 dBm
f = 7.2 GHz
20
10
20
30
Pin (dBm)
Figure 59. NE868296 Test Circuit (6.5 GHz and 7.5 GHz)
6.5
7
f (GHz)
7.5
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
40
VDS = 9.0 V
OUT
28.5
2.5
Pout (dBm)
IN
28.5
1.5
3
18.0
Pin = 25 dBm
30
f = 4.0 GHz
9.5
7.5
10.5
4.5
2 2
20
10
20
30
Pin (dBm)
4.0
3.5
Figure 60. NE868495-4 Circuit
4.5
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
30
2.5
3.5
12.7
6
2.5
5
2.5
2.1
7.7
3.7
8.5
2.1
21.5
2.2
Figure 61. NE868495-5 Circuit
IN
OUT
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
40
VDS = 9.0 V
18.5
18.5
3
2
6
6.5
7.0
3.5
2.5
Pout (dBm)
14
9.5
Pin = 26 dBm
30
f = 6.5 GHz
20
10
20
30
Pin (dBm)
6.0
6.5
7.0
Figure 62. NE868495-6 Circuit
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
40
OUT
IN
9.0
9.0
1.9
5.2
2.0
f = 7.0 GHz
30
Pin = 26 dBm
2.1
6.7
4.7
15.0
2.1
1.9
Pout (dBm)
11.0
20.0
VDS = 9.0 V
20
10
20
30
Pin (dBm)
Figure 63. NE868495-7 Circuit
6.5
7.0
f (GHz)
7.5
AN82901-1
IN
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
20
6.2
2
2.1
3.3
5
7
3.5
2.6
4.5
1.5
2.1
15
2
11
2.4
2
Figure 64. NE868495-8 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
15
30
4.5
4
4
4.3
2.1
21.5
5
2.1
5
Figure 65. NE868898-5 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
40
25
25
13.5
VDS = 9.0 V
13.5
9.8
5.5
4.0
Pout (dBm)
9.0
7.8
Pin = 29 dBm
30
f = 6.0 GHz
20
10
20
30
Pin (dBm)
5.5
6.0
6.5
f (GHz)
Figure 66. NE868898-6 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
OUT
IN
VDS
40
25
25
= 9.0 V
14.5
P in= 29 dBm
30
8.8
2
3.6
12
Pout (dBm)
3.5
f = 7.2 GHz
20
10
20
30
Pin (dBm)
6.5
Figure 67. NE868898-7 Circuit
7.0
f (GHz)
7.5
AN82901-1
IN
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
2
3
2.1
3.7
4.8
15
1.5
2.1
f = 8 GHz
Pout (dBm)
OUT
20
35
Pin = 30 dBm
30
20 dBm
25
VDS = 9 V
20
10
15
20
30
Pin (dBm)
7.5
8.0
8.5
f (GHz)
Figure 68. NE868898-8 Circuit
6
6
NE371698-4
NE800898-4
4
PHASE (deg.)
PHASE (deg.)
4
2
2
0
0
-2
-2
20
24
22
28
26
22
30
24
6
NE868495
NE868898
4
2
0
-2
4
PHASE (deg.)
PHASE (deg.)
PHASE (deg.)
4
2
0
-4
15
Pin (dBm)
20
25
-4
10
2
0
-2
-2
10
32
6
NE868196
(NE868199)
5
30
Pin (dBm)
6
0
28
26
Pin (dBm)
15
20
25
30
Pin (dBm)
Figure 69. AM-PM Conversion for the NE800, NE371 and NE868 Series
35
-4
10
15
20
25
Pin (dBm)
30
35
AN82901-1
50
40
10
Pout
45
0
30
-10
20
f = 7.7 GHz, ∆f = 10 MHz
VDS = 9 V
IDS = 1.0 A
40
30
-30
Pout, IM3 (dBm)
-20
IM3 (dB)
Pout (dBm)
Pout
35
IM3
10
0
IDS = 1.2A,Pin =30 dBm
IDS = 0.8A,Pin =30 dBm
IM3
25
NE800898-7H
20
15
15
20
25
30
-40
-10
-50
-20
-60
-30
10
35
NE868898-6
20
30
Pin (dBm)
40
Pin (dBm)
Figure 70. Third Order Intermodulation Distortions for the NE800898-7H and NE868898-6
References
[1]
Masuo Fukuda, et. al.,
”Low Noise GaAs FET Ampliliers,” MW77-21.
[5]
L. Nevin, et. al., “L-Band GaAs FET
Amp.,” Microwave Journal, Apr. 1979.
[2]
Charles A Liechti, et. al., MTT-22, No. 5, May 1974
[6]
Eric Ulrich, “Use Negative Feedback to Slash
Wideband VSWR,” Microwaves, Oct. 1978.
[3]
Herman Sfatz, et. al., ED-21, No. 9, Sept. 1974.
[7]
[4]
P. Bura, Electronics Letters, Vol. 10, No. 10, p.
181-,16th, May 1974.
K. Honjo, et. al., “Broadband Internal Matching of
Microwave Power GaAs MES FETs.,” IE3, Trans,
Mit. Jan. 1979.
[8]
Y. Takayama, “A New Load-Pull Characterization
Method for Microwave Power Transistors,”
1976 MTT-S, Digest, p. 218-220, June 1976.
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© California Eastern Laboratories 01/23/2003