New Silicon Carbide Schottky-gate Bipolar
Mode Field Effect Transistor (SiC SBMFET)
without PN Junction
M. Jagadesh Kumar, Senior Member, IEEE, and Harsh Bahl
Abstract-- The Bipolar Mode Field Effect Transistors
(BMFETs) using P+ gates on N-type Silicon substrate are the
most commonly used power devices for high-current mediumpower switching applications and as optically controlled switches
11,21. These are dual gate devices with deep P+ gate junctions,
which require large thermal cycles for diffusion. In this paper,
we propose a novel Schottky-gate BMFET (SBMFET) using Ptype 4H Silicon-Carbide 13,41, a wide bandgap material, in which
the PN junction gates are replaced by the Schottky gates. We
have studied the characteristics of this device using twodimensional numerical simulation 1[1. Our results demonstrate
for the first time that the P-SiC Schottky-gate BMFET has very
low ON voltage drop, good output characteristics, a reasonable
current gain and a blocking voltage greater than 1000 V.
Index Terms- Schottky contact, Bipolar, Silicon Carbide,
Field effect transistor, Simulation.
I.
INTRODUCTION
TH E BMFET operates in bipolar mode when the gate PN
Metal Gate
Source
Metal Gate
I~~~~~~ >
Hiafmium
((D ..=3 .9V)
d (31 gm)>l
W (Channel length)
P - Drift region
P+ Substrate
Drain
Fig. 1. Schematic corss-section of P-SiC SBMFET with Schottky gates.
II. DEVICE STRUCTURE AND PARAMETERS
For an N-SiC SBMFET, the gate metal should have its
work function ((Dm) such that when the gate is forward biased,
the valence band electrons from N-SiC are injected into the
metal which is equivalent to the metal injecting holes into the
N-SiC drift region. Unless the forward biased Schottky gate
resistance. This is the main attraction of a BMFET. However, injects holes into the N-drift region, a plasma cannot be
such deep diffusions required for the gate cannot be done on a formed in the drift region. However, our study shows that a
SiC wafer since most dopants in SiC have negligible diffusion gate Schottky contact that can inject holes could not be
coefficients. Therefore, a SiC BMFET can be formed only if established with the available metals. Even the use of a metal
the PN junction gates are replaced by a Schottky gate. For a P- with the highest work function (Selenium with (Dm=5.9 V) for
type drift region, the Schottky gate has to inject electrons into the gate Schottky contact results in a resistive behavior in the
the drift region to form the electron-hole plasma. On the other output characteristics of the N-SiC SBMFET as shown in
hand, for an N-type drift region, the Schottky gate has to inject Fig.2 and therefore our study points to the fact that a Scohttky
holes into the drift region and is difficult with the available gate BMFET cannot be realized in N-type SiC.
metals that are commonly used in microelectronics. Therefore,
Junction is forward biased with respect to the source. This
results in a significant minority carrier injection by the gate
into the drift region. The hole-electron plasma in the drift
region leads to a substantial conductivity modulation resulting
in a negligible saturation voltage and, hence, a small ON
demonstrate for the first time that while an N-SiC
SBMFET cannot be realized, a P-SiC SBMFET (Fig. 1)
without the gate PN junction is feasible. SiC power devices
have proved to be very useful in advanced and high
temperature military and nuclear applications.
we
The authors are with Department of Electrical Engineering, Indian
Institute of Technology, Hauz Khas, New Delhi 110 016, India (e-mail:
mamidala 0ieee.org (M.J. Kumar)).
1-4244-0370-7/06/$20.00 C 2006 IEEE
III. RESULTS AND DISCUSSION
However, in the case of P-SiC SBMFET (Fig. 1), the
Schottky gate injects electrons into the P-drift region when
forward biased. To maintain charge neutrality, the hole
concentration also matches with the electron concentration
forming a plasma region. When the negative drain voltage is
increased, the electrons will be pushed towards the source
region as shown in Fig. 3 creating a depletion region near the
drain. This causes the electric field near the drain region to be
larger than in the conductivity modulated drift region as
6-
-44
--
-
30
IG= 1 gA/tm
i -20
-
a)
D
-1 0
C)
0
a)
a 2-
.
0
n
t
J
0
-1
-2
-3
-4
-5
Drain-to-Source Voltage (V)
5
4
Drain-to-Source Voltage (V)
Fig. 4. Output characteristics of P-SiC SBMFET for different gate currents.
Fig. 2. Output characteristics ofN-SiC SBMFET using Selenium ((Fm=5.9 V)
as gate metal.
250-
1 018
200-
E0
-6
VDS= -5 V
.= 150D
A. _
0
100-
U)
c:
50-
0
0
(a)
0-
0
0
cJ
L-
-10 -20 -30 -40 -50 -60
Drain current (pA/Irm)
Distance from Source to Drain (gim)
IG= -1 AItm
cJ
U-1
a)
0-
0
(b)
L-
A.0
a)
uJ
30
(b)
5
10
15
20
25
Fig. 3. (a): Injected electron profile and (b) Electric field profile in the
channel for different drain voltages.
shown in Fig. 3(b). Both these results confirm the phenomena
of conductivity modulation due to plasma formation in the PSiC drift region. Although SiC is a wide bandgap material
(3.9 eV), this plasma formation and its modulation by the
drain voltage are responsible for the extremely good output
characteristics with low ON voltage drop as shown in Fig. 4
for different gate currents.
50
Epilayer Thickness (urn)
30
Distance from Source to Drain (pim)
40
Fig. 5. Current gain
SiC SBMFET.
versus
(a) drain current and (b) epilayer thickness of P-
The current gain variation with drain current for the P-SiC
SBMFET is shown in Fig. 5(a). The gain variation with
epilayer thickness is shown in Fig. 5(b). It is clearly seen that
the P-SiC SBMFET has a reasonable current gain. Most
reported BMFETs on silicon have a similar range of current
gain.
The blocking voltage variation with epilayer thickness is
shown in Fig. 6. In order to obtain the correct blocking
voltage, the Schottky gate is reverse biased at +10 V to ensure
-5000
V
Reverse Characteristics," IEEE Trans. on Electron Devices,
Vol.48, pp.2695-2700, Dec. 2001.
[4] T. Hatakeyama, J. Nishio, C. Ota and T. Shinohe, "Physical
Modeling and Scaling Properties of 4H-SiC Power Devices,"
Proceedings of the International Conf on Simulation of
Semiconductor Processes and Devices, 2005, SISPAD'05, 0103 Sep. 2005, pp.171-174
[5] MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto CA,
=10 V
> -4000
a)
> -3000
1997.
[6] ATLAS User's Manual, Silvaco, Ca, 2005.
-( -2000
0
0
-1000l
20
30
40
50
Epilayer Thickness (gim)
Fig. 6. Blocking voltage variation of P-SiC SBMFET
thickness.
versus
epilayer
that the drift region between the gates is completely pinched
off and the device is in OFF state. As can be seen in Fig. 6, the
P-SiC SBMFET has a very high blocking voltage (1200 V at a
epilayer thickness of 20 ptm) and the blocking voltage
increases with epilayer drift region thickness.
IV. CONCLUSION
SiC is the most promising material for power devices
because its dielectric breakdown field is six times greater than
that of silicon, it can be used at high temperatures, it has a
high thermal conductivity, and it can be manufactured using
the same process technology that is used for silicon. Our
simulation study using MEDICI shows that N-SiC SBMFET
is not a feasible device due to the fact that the Schottky metal
gate cannot inject holes into the drift region which is essential
for the plasma formation and hence the conductivity
modulation of the drift region.
We have, however,
demonstrated for the first time that a P-SiC Schottky gate
BMFET (SBMFET) can be easily realized if a gate metal with
appropriate work function is chosen. Our study demonstrates
that although SiC is a wide bandgap material, the P-SiC
SBMFET exhibits very low ON voltage drop, good output
characteristics, a reasonable current gain and a high blocking
voltage. This device is expected to result in significant
improvements in a variety of switching applications. Since
the proposed device is devoid of any PN junctions, the thermal
budget required for the fabrication of the proposed device will
be less resulting in lower fabrication costs.
V.
[1]
[2]
[3]
REFERENCES
S. Ryu, S. Bellone, A. Carnuso, P. Spirito, and G. Vitale "A
Quasi one dimensional analysis of vertical FET devices operated
in the bipolar mode," Solid State Electronics, Vol. 26, pp.403413, 1983..
A. Caruso, P. Spirito, G. Vitale, G Busatto, G. Ferla and S. Musumeci,
"Performance analysis of a bipolar mode FET (BMFET) with normally
off characteristics," IEEE Trans. on Power Electronics, Vol.3, pp.810814, 1988.
Y. Singh and M. J. Kumar, "A New 4H-SiC Lateral Merged
Double Schottky (LMDS) Rectifier with Excellent Forward and
M. Jagadesh Kumar (SM'1999) was born in
Mamidala, Nalgonda District, Andhra Pradesh,
India. He received the M.S. and Ph.D. degrees in
electrical engineering from the Indian Institute of
Technology, Madras, India. From 1991 to 1994, he
performed post-doctoral research in modeling and
processing of high-speed bipolar transistors with the
Department of Electrical and Computer Engineering,
University of Waterloo, Waterloo, ON, Canada. While with the University of
Waterloo, he also did research on amorphous silicon TFTs. From July 1994 to
December 1995, he was initially with the Department of Electronics and
Electrical Communication Engineering, Indian Institute of Technology,
Kharagpur, India, and then joined the Department of Electrical Engineering,
Indian Institute of Technology, Delhi, India, where he became an Associate
Professor in July 1997 and a Full Professor in January 2005. His research
interests are in Silicon Nanoelectronics, VLSI device modeling and
simulation, integrated-circuit technology, and power semiconductor devices.
He has published extensively in the above areas with more than 110
publications in refereed journals and conferences. His teaching has often been
rated as outstanding by the Faculty Appraisal Committee, IIT Delhi.
Dr. Kumar is a Fellow of Institution of Electronics and Telecommunication
Engineers (IETE), India and a Senior Member of IEEE. He is on the editorial
board of Journal of Nanoscience and Nanotechnology and also on the
Editorial Board of IETE Journal of Research as a subject area Honorary
Editor for Electronic Devices and Components. He has reviewed extensively
for different journals including IEEE Trans. on Electron Devices, IEEE
Trans. on Device and Materials Reliability and IEEE Electron Device Letters.
He was Chairman, Fellowship Committee, The Sixteenth International
Conference on VLSI Design, January 4-8, 2003, New Delhi, India. He was
Chairman of the Technical Committee for High Frequency Devices,
International Workshop on the Physics of Semiconductor Devices, December
13-17, 2005, New Delhi, India.
Harsh Bahl was born in Ghaziabad, Uttar Pradesh,
India. He received his BE degree in Electronics from
Shivaji University, Kohlapur, India in 1990. He has
been working as an Aircraft Maintenance Engineer
with the Indian Air Force since then. He received his
MBA degree in Operations Management from Indira
Gandhi National Open University, New Delhi, India in
2001. He is also an Associate member of the Institute of Electronics and
Telecommunication Engineers (IETE) of India. He is presently pursuing M
Tech degree in Integrated Electronics and Circuits from the Department of
Electrical Engineering, Indian Institute of Technology, Delhi, India.
His research areas include simulation of Power Semiconductor Devices
with a focus on BMFETs. His other interests include simulation of SiliconCarbide devices.