D a t a S h e e t , V 2. 0 , D e c . 2 00 7
B G F 10 8
7 C h a n n el L C D F i l t er A r r a y w i t h E S D P r ot e c t i o n
S m a l l S i g n a l D i s c r et e s
Edition 2007-12-10
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
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be endangered.
BGF108
BGF108
Revision History: 2007-12-10, V2.0
Previous Version: 2006-12-14, V1.4
Page
Subjects (major changes since last revision)
All
Preliminary status removed
5
Table 1 and Table 2 updated
6
Line capacitance, Insertion Loss and Analog Cross Talk curves updated
7
Package and tape drawing updated
Data Sheet
3
V2.0, 2007-12-10
BGF108
7 Channel LCD Filter Array with ESD Protection
7 Channel LCD Filter Array with ESD Protection
Feature
• 7 channel integrated RC filter array
• ESD protection according to IEC61000-4-2
up to 15 kV contact discharge on all IOs
• Wafer Level Package with SnAgCu solder balls
• 400 µm solder ball pitch
• RoHS and WEEE compliant package
WLP-18-1-N-3D
A4
A1
R1, 70Ω
A5
A2
R2, 70Ω
B5
B1
R3, 70Ω
C4
C1
R4, 70Ω
C5
C2
R5, 70Ω
D4
D1
R6, 70Ω
D5
D2
R7, 70Ω
A3
Figure 1
B3
C3 D3
Bgf108_schematic.vsd
Schematic
Description
The BGF108 is a 7 channel RC filter array to provide EMI attenuation of undesired signals in the 800 - 2000 MHz
range. All pins are protected against ESD up to 15 kV according to IEC61000-4-2 (contact discharge). The wafer
level package is a green package with a size of only 1.68 mm x 2.02 mm and a total height of 0.60 mm.
Type
Package
Marking
Chip
BGF108
WLP-18-1
BGF108
N0715
Data Sheet
4
V2.0, 2007-12-10
BGF108
7 Channel LCD Filter Array with ESD Protection
Table 1
Maximum Ratings
Parameter
Symbol
Values
Min.
VP
Operating temperature range
TOP
TSTG
Storage temperature range
Summed up input power for all pins
PIN
Electrostatic discharge according to IEC61000- VE
Voltage at all pins to GND
Typ.
Unit
Max.
0
5
V
-40
+85
°C
-65
+150
°C
60
mW
15
kV
-15
Note /
Test Condition
TS < 70 °C
4-21) at all pins
1) Contact discharge
Electrical Characteristics1)
Table 2
Parameter
Symbol
Series Resistors R1... R10
Leakage current of each line to GND
Breakdown voltage of each line to GND
Line capacitance of each line to GND
Values
Unit
Min.
Typ.
Max.
R
IR
56
70
84
Ω
1
2
100
1000
nA
V(BR)
CT
7
8.2
27
17
Note /
Test Condition
VR = 3 V
VR = 5 V
I(BR) = 1 mA
VR = 0 V
VR = 3 V
V
30
pF
1) at TA = 25 °C
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Figure 2
Data Sheet
Capacitance of one line to GND versus DC voltage
5
V2.0, 2007-12-10
BGF108
7 Channel LCD Filter Array with ESD Protection
,QVHUWLRQ/RVV%*)
G%
(
(
(
(
(
(
IUHTXHQF\>+]@
Figure 3
Typical filter characteristics of on channel (ZS = ZL = 50 Ω, VR = 0 V)
&URVVWDON%*)
6>G%@
Y
(
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(
(
(
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Figure 4
Data Sheet
Typical cross talk between two channels (ZS = ZL = 50 Ω, VR = 0 V)
6
V2.0, 2007-12-10
BGF108
7 Channel LCD Filter Array with ESD Protection
2.02 ±0.05
Pin A1
Corner Index Area 2)
D2
D3
D4
D5
C1
C2
C3
C4
C5
B1
B3
A1
A2
A4
A5
18x
ø0.05 M A B
0.25 ±0.04 1)
C
A3
B5
0.08 C
18x
COPLANARITY
A
1.68 ±0.05
D1
0.4
0.4
0.1 C
3 x 0.4 = 1.2
SEATING PLANE 3)
0.2 ±0.05
STANDOFF
(0.24 ±0.05)
0.6 ±0.05
(0.24 ±0.05)
(0.21±0.05)
B
(0.21±0.05)
4 x 0.4 = 1.6
1) Dimension is measured at the maximum solder ball diameter, parallel to primary datum C
2) Pin A1 corner identified by marking
3) Primary datum C and seating plane are defined by the spherical crowns of the balls
WLP-18-1-N-PO V01
Package WLP-18-1
4 ±0.1
Pin 1
Corner Index Area
Figure 6
Data Sheet
8 ±0.1
2.14 ±0.05
0.25
1.78 ±0.05
3˚±2˚
Figure 5
0.71±0.05
WLP-18-1-N-TP V01
Tape of WLP-18-1
7
V2.0, 2007-12-10