IEEE International Symposium on Industrial Electronics (ISIE 2009)
Seoul Olympic Parktel, Seoul, Korea July 5-8, 2009
Active-Clamping Quad-Flyback Converter
Lin, B.-R., Chiang, H.-K. and Tsao, F.-P.
Department of Electrical Engineering,
National Yunlin University of Science and Technology
Yunlin 640, Taiwan
proposed to achieve zero voltage switching (ZVS) for all
power switches. The secondary sides of quad-flyback
converter are connected in parallel to share the load
current. Thus, the transformer copper losses and the
conduction losses on the output diodes are reduced. Activeclamping part including one auxiliary switch and one
clamp capacitor can release the energy stored in the
magnetizing and leakage inductances such that the voltage
stress of main switch is clamped and main/auxiliary
switches can be turned on at ZVS. In the proposed circuit,
the constant switching frequency with asymmetrical PWM
waveform is generated to realize the ZVS turn-on of
switches at the transition interval between main and
auxiliary switches. Thus, the switching losses and thermal
stresses of the semiconductors are reduced. The operation
principle, system analysis and design consideration of the
proposed converter are discussed in detail. Finally, a
prototype of the proposed converter is implemented by
200V input voltage, 48V output voltage, 480W output
power and 90kHz switching frequency to verify the
theoretical analysis and the effectiveness of the proposed
converter.
The active-clamping circuit can absorb the surge energy stored
in the leakage inductance and limit the voltage stress on power
switch. Based on the resonant behavior by the output
capacitances of power switches and leakage inductance of
transformer during the transition interval, main and auxiliary
switches in active-clamping flyback converter can achieve
ZVS turn-on. To increase the power capability, parallel flyback
converters with ZVS techniques shown in Fig. 1(b) have been
presented in [6-9] However the drawback of the parallel
flyback converters is too many power switches in the circuit.
In this paper, an active-clamping quad-flyback converter is
presented. The proposed converter includes main circuit (four
flyback converters in parallel with the same power switches) to
transfer energy and active clamp circuit. Thus the proposed
converter has the following advantages: (1) low current
stresses of the rectifier diodes due to parallel connection of
four flyback converters to achieve high power applications, (2)
low conduction losses due to ZVS turn-on of power switches,
(3) the voltage stresses of main and auxiliary switches are
clamping to the clamp voltage, and (4) small size of power
converter. The circuit configuration, mathematical analysis and
design consideration are presented in detail. Finally,
experiments based on a 480W laboratory prototype are
presented to verify the circuit performance.
I. INTRODUCTION
II. CIRCUIT CONFIGURATION
Switching mode power supplies with flyback converters
have been used in low-power applications for its simplicity and
less components. The transformer in flyback converters is
operated to achieve electric isolation and energy storage.
However, the shortcomings of flyback converters are low
power capability, low efficiency, high switching losses and
current stresses on power semiconductors. Generally the
converter with high switching frequency is always adopted to
reduce the size and weight of converter. However the high
switching frequency will result in high switching losses and
increase the electromagnetic interference. The PWM
converters with soft-switching technology have been
developed to improve this drawback. Zero voltage switching
(ZVS) flyback converters with the quasi-resonant techniques
[1-2] have been proposed to reduce the switching losses on
active switch. However, the voltage stress in quasi-resonant
flyback converters is too high, especially for the high input
voltage. The high voltage or current stress on switches will
increase the extra conduction losses. Active-clamping
converter [3-5] is one kind of soft switching converters to
realize zero voltage switching (ZVS). Fig. 1(a) shows the
circuit configuration of an active-clamping flyback converter.
Fig. 1(c) shows the circuit configuration of the proposed
active-clamping quad-flyback converter. In the proposed
converter, four flyback cells are connected in parallel at the
secondary side and connected in series at the primary side.
These four flyback cells share the same main and auxiliary
switches such that the switch counts are reduced compared
with the conventional parallel flyback converters. Basically
there are two converter modules in the proposed converter. The
circuit components in module 1 include Vin, T1, T2, S1, S2, C1,
Cr1, Cr2, D1, D1 and Co. In the same way, the circuit
components in module 2 are C2, T3, T4, S1, S2, C1, Cr1, Cr2, D3,
D4 and Co. Vin and Vo are input and output voltages
respectively. Auxiliary switch S2 and clamp capacitor C1 are
used to limit the voltage spike by the leakage inductances of
T1~T4 and the voltage stresses of S1 and S2 are clamped to vC1.
Cr1 and Cr2 are the resonant capacitances. The resonant
capacitances Cr1 and Cr2 and inductances of T1~T4 are resonant
during the transition interval between the main and auxiliary
switches. Thus both switches S1 and S2 can be turned on at
ZVS and the switching losses and thermal stresses of the
semiconductors and transformers are reduced.
Abstract—An active-clamping quad-flyback converter is
978-1-4244-4349-9/09/$25.00 ©2009 IEEE
1592
(a)
(b)
Fig. 2 Key waveforms of proposed converter.
(c)
Fig. 1 (a) Active clamp flyback converter (b) parallel active clamp flyback
converter (c) proposed active clamp bi-flyback converter.
III. PRINCIPLE OF OPERATION
The main waveforms of the proposed converter are shown
in Fig. 2. Based on the on/off states of switches S1 and S2, the
operation behaviors during one switching cycle are divided
into five operation modes. Fig. 3 gives the equivalent circuit in
each operation mode. The following assumptions are made
before the analysis of the operation modes.
• All semiconductors are ideal;
• The average voltage of capacitor C2 is equal to the input
voltage in steady state, vC2=Vin;
• The turns ratio of transformers T1~T4 is given as
n1=n2=n3=n4=Np/Ns≡n;
• Capacitances of C1 and C2 are much larger than the
capacitances of Cr1 and Cr2;
• The leakage inductances of transformer T1~T4 are
Llk1=Llk2=Llk3=Llk4≡Lr are less than the magnetizing
inductances Lm of transformers T1~T4;
• The energy stored in the leakage inductances Lr1~LLk4 is
greater than energy stored in the resonant capacitances
Cr1 and Cr2 to achieve ZVS.
Mode 1 (t0≤t<t1): In this mode, S1 and S2 are on and off,
respectively. The primary side voltages of each transformer are
equal to half of input voltage Vin/2. The secondary side
voltages of transformers T1~T4 are negative. Thus the rectifier
diodes D1~D4 are all off. The primary currents ip1 and ip2 are
both increase with the slope of Vin/(2Lr+2Lm). The input power
is stored in the magnetizing inductances of T1~T4 Thus, no
power is delivered to output load in this mode. The drain
voltages of S1 and S2 are equal to 0 and vC1, respectively. The
switch currents iS1=ip1+ip2 and iS2=0. This mode ends at time t1
when main switch S1 is turned off. The primary currents ip1 and
ip2 and switch currents iS1 and iS2 at time t1 are expressed as:
i p1 ( t 1 ) = i Lm,T1 ( t 1 ) = i Lm,T 2 ( t 1 ) = i Lm,T1 ( t 0 ) +
Vin
( t 1 − t 0 ) (1)
2L m + 2L r
i p 2 ( t 1 ) = i Lm,T3 ( t 1 ) = i Lm,T 4 ( t 1 ) = i Lm,T3 ( t 0 ) +
v C2
( t 1 − t 0 ) (2)
2L m + 2L r
i S1 ( t 1 ) = i p1 ( t 1 ) + i p 2 ( t 1 ) = i Lm,T1 ( t 0 ) + i Lm,T3 ( t 0 )
(3)
Vin + v C 2
(t 1 − t 0 )
2L m + 2L r
Mode 2 (t1≤t<t2): Main switch S1 is turned off at time t1. Since
the switch current iS1 is positive, capacitor Cr1 is charged from
0V to vC1 and capacitor Cr2 is discharged from vC1 to 0V.
i p1 ( t 1 ) + i p 2 ( t 1 )
v Cr1 ( t ) ≈
(t − t1 )
(4)
2C r
i p1 ( t 1 ) + i p 2 ( t 1 )
v Cr 2 ( t ) ≈ v C1 −
(t − t1 )
(5)
2C r
1593
+
where Cr1=Cr2=Cr. The primary side voltages of T1~T4 are
decreased. Since the transformer secondary side voltages are
still less than output voltage, diodes D1~D4 are in the off-state.
Since Cr1 and Cr2, the primary currents ip1 and ip2 are almost
constant in this mode. In this interval, the voltage vCr1 is less
than vC1 such that the body diode of auxiliary switch S2 is
blocked. This mode ends at time t2 when the capacitor voltage
vCr1=vC1 and vCr2=0. The time interval of this mode is
expressed as:
2C r v C1
(6)
Δt 12 = t 2 − t 1 ≈
i p1 ( t 1 ) + i p 2 ( t 1 )
(a)
Mode 3 (t2 ≤t<t3): At time t2, the capacitor voltages vCr1=vC1
and vCr2=0. The secondary side voltages are all equal to -vo and
D1~D4 are conducting. Since ip1(t2)+ip2(t2) is positive, the antiparallel diode of S2 is conducting. Switch S2 can be turned on at
ZVS before iS2 is positive. The energy stored in the
magnetizing inductances of T1~T4 is delivered to output load.
The magnetizing currents of T1~T4 decrease linearly with the
slope of -nVo/Lm. If the resonant frequency by leakage
inductance Lr and the clamp capacitance C1 is much less than
the switching frequency, the clamp capacitor voltage is almost
constant and the primary currents ip1 and ip2 are expressed as:
v − 2nVo − Vin
(7)
i p1 ( t ) = i p1 ( t 2 ) − C1
(t − t 2 )
2L r
v − 2nVo − v C 2
(8)
i p 2 ( t ) = i p 2 ( t 2 ) − C1
(t − t 2 )
2L r
The rectifier diode currents at the secondary side are given as:
i D1 ( t ) = n (i Lm,T1 ( t ) − i p1 ( t ))
(9)
i D 2 ( t ) = n (i Lm,T 2 ( t ) − i p1 ( t ))
(10)
i D3 ( t ) = n (i Lm,T3 ( t ) − i p 2 ( t ))
(11)
i D 4 ( t ) = n (i Lm,T 4 ( t ) − i p 2 ( t ))
(12)
iD1
D1
iD2
D2
T1
ip1
Vin vC1
S2
iD3
iD4
D3
T2
iS2
C1
S1
Cr2
T3
i'o
D4
io
Vo
Co R
T4
ip2
Cr1
vC2
C2
iS1
(b)
(c)
This mode ends at time t3 when the auxiliary switch S2 is
turned off.
Mode 4 (t3≤t<t4): At time t4, switch S2 is turned off. Since the
magnetizing current is still greater than the primary current
such that the secondary currents are still positive and diodes
D1~D4 are conducting. The transformer secondary and primary
voltages are equal to -Vo and -nVo respectively. Thus the
magnetizing currents of T1~T4 decrease linearly in this mode.
Since the current ip1+ip2 is negative at time t3 such that the
capacitor Cr1 is discharged and the capacitor Cr2 is charged.
i p1 ( t 3 ) + i p 2 ( t 3 )
v Cr1 ( t ) ≈ v C1 +
(t − t 3 )
(13)
2C r
i p1 ( t 3 ) + i p 2 ( t 3 )
v Cr 2 ( t ) ≈ −
(t − t 3 )
(14)
2C r
To ensure the ZVS turn-on of S1, the energy stored in the
leakage inductances of T1~T4 must be greater than the energy
stored in Cr1 and Cr2. Thus, we can obtain the minimum
leakage inductance to achieve ZVS turn-on of S1.
(d)
(e)
Fig. 3 Equivalent circuits of the proposed converter during one switching cycle
(a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5.
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L r > C r v C2 1 /[i 2p1 ( t 3 ) + i 2p 2 ( t 3 )]
≈ C r [Vin /(1 − δ)] 2 /[i 2p1 ( t 3 ) + i 2p 2 ( t 3 )]
(15)
This mode ends at time t4 when vCr1=0. At this instant, the body
diode of switch S1 is conducting.
Mode 5 (t4≤t<T+t0): After time t5, the voltage vCr1=0 and the
anti-parallel diode of S1 is conducting. Before iS1 is positive,
switch S1 must be turned on to achieve ZVS. In this mode, the
magnetizing current is still greater than the primary current
such that the secondary winding currents are positive and the
rectifier diodes are conducting. Thus, the magnetizing currents
decrease with the slope of -nVo/Lm. The primary currents ip1(t2)
and ip2(t2) increase with the slope of (Vin+nVo)/2Lr. This mode
ends at time t0+T when the primary current equals the
magnetizing current. The secondary winding currents are zero
and the rectifier diodes are off. Then, the circuit operation in
one switching cycle is completed.
The transition and delay times in modes 2 and 4 from Fig. 2
are much fast. Thus these two modes are neglected in the
following to derive the voltage conversion ratio of the
proposed converter. In modes 1 and 5, the voltage applied on
the primary side of T1 and T2 is equal to Vin. In mode 3 the
primary side voltage of T1 and T2 is Vin-VC1. Based on the
voltage-second balance of the primary side of T1 and T2, the
average clamp voltage VC1 is given as:
V
(16)
VC1 = in
1− δ
where δ is the duty ratio of main switch S1. Based on the
voltage-second balance across the primary side voltage of T3
and T4, the average capacitor voltage VC2 can obtain as:
VC2=Vin
(17)
The secondary winding voltages of T1~T4 are equal to -Vo in
modes 3 and 5. In mode 1 the secondary winding voltages of
T1~T4 are equal to Vin*Lm/[2n(Lm+Lr)]. Based on the voltagesecond on the transformer secondary winding, we can obtain
the output voltage Vo.
(δ − δ loss )Vin
(δ − δ loss )Vin
Lm
Vo =
*
≈
(18)
1 − δ + δ loss
2n (L m + L r ) 2n (1 − δ + δ loss )
wherer δloss is the duty cycle loss of S1 in mode 5. Thus the
voltage conversion ratio M of the proposed converter is
expressed as:
V
δ − δ loss
Lm
δ − δ loss
M= o =
*
≈
(19)
Vin 1 − δ + δ loss 2n (L m + L r ) 2n (1 − δ + δ loss )
IV. DESIGN CONSIDERATION
The design process of the proposed quad-flyback converter
is considered in this section. We assumed that the maximum
effective duty cycle of S1 is δmax,eff=δmax-δloss. The turns ratio of
T1~T4 is given as:
N p Vin ,min * δ max,eff
(20)
n=
≈
N s 2Vo (1 − δ max,eff )
where Vin,min is the minimum input voltage. Each flyback
converter delivers one fourth of output power. Thus the stored
energy in each magnetizing inductance of T1~T4 is greater than
Po/4. The ripple current on magnetizing inductance is given as:
Vin ,min δ max,eff
Δi Lm ≈
(21)
Lmf
where f is the switching frequency. If the allowed ripple current
ΔiLm is given, then the minimum magnetizing inductance is
given as:
Vin ,min δ max,eff
L m ,min =
(22)
Δi Lm f
Based on the current-second balance on capacitor C2, we can
obtain the average magnetizing current of transformers T3 and
T4.
I
I Lm3 = I Lm 4 = o
(23)
4n
Based on the power balance between the input and output sides,
we can obtain the average magnetizing current of transformers
T1 and T2.
δ max,eff I o
I
(24)
I Lm1 = I Lm 2 = o +
4n 2n (1 − δ max,eff )
The maximum primary currents ip1 and ip2 can be expressed as:
i p1, max = I Lm1 +
δ max,eff I o
Vin ,min δ max,eff
Δi Lm1 I o
(25)
=
+
+
2
4n 2n (1 − δ max,eff ) 4(L m + L r )f
Δi Lm3 I o Vin ,min δ max,eff
=
+
(26)
2
4 n 4( L m + L r ) f
The minimum primary currents ip1 and ip2 can be expressed as:
δ max,eff I o
I
i p1, min = i p1,max − i D1, max ≈ o +
4n 2n (1 − δ max,eff )
(27)
Vin ,min δ max,eff
Io
+
−
4( L m + L r ) f
2n (1 − δ max,eff )
i p 2, max = I Lm3 +
i p 2, min = i p 2,max − i D3,max ≈
I o Vin ,min δ max,eff
Io
(28)
+
−
4n 4(L m + L r )f
2n (1 − δ max,eff )
Thus the maximum switch current iS1,max can be given as:
i S1, max = i p1,max + i p 2,max =
δ max,eff I o
Vin ,min δ max,eff
Io
(29)
+
+
2n 2n (1 − δ max,eff ) 2(L m + L r )f
The average switch current iS2,av is equal to zero and the
maximum and minimum current of S2 can be given as:
Io
I
− o
i S2, max = −(i p1,min + i p 2, min ) ≈
n (1 − δ max,eff ) 2n
(30)
δ max,eff I o
Vin ,min δ max,eff
−
−
2n (1 − δ max,eff ) 2(L m + L r )f
i S2, min = −(i p1,max + i p 2,max )
≈−
Vin ,min δ max,eff
δ max,eff I o
Io
−
−
2n 2n (1 − δ max,eff ) 2(L m + L r )f
(31)
The root-mean-square (rms) current of power switches S1 and
S2 is given as:
δ max,eff I o
I
(32)
) δ max,eff
i S1, rms ≈ ( o +
2n 2n (1 − δ max,eff )
1595
i S1, rms ≈
(i S22,min + i S22,max + i S2,min i S2,max )(1 − δ max,eff )
(33)
3
If the ripple voltage on clamp capacitance C1 in mode 3 can be
neglected, the voltage stresses of main and auxiliary switches
are given as:
V
(34)
v S1,stress = v S2,stress = VC1 = in
1− δ
The voltage stresses of S1 and S2 are related to the input voltage
Vin and the duty cycle δ. The voltage stresses of the diodes
D1~D4 can be obtained in mode 1 when switch S1 is in the onstate.
Vin , max
v D1,stress = v D 2,stress = v D3,stress = v D 4,stress ≈
+ Vo (35)
2n
The average, rms and maximum currents of the rectifier diodes
are given as:
I
(36)
i D1,av = i D 2,av = i D3,av = i D 4,av ≈ o
4
Io
(37)
i D1,rms = i D 2,rms = i D3,rms = i D 4,rms ≈
2 3(1 − δ max,eff )
i D1,max = i D 2,max = i D3,max = i D 4,max ≈
Io
(38)
2(1 − δ max,eff )
Basically the ZVS of auxiliary switch S2 is naturally achieved
by the energy stored in the leakage inductances. The ZVS
condition of main switch S1 is determined from (15) with
ip1(t3)=ip1,min and ip2(t3)=ip2,min.
(39)
L r > C r [Vin /(1 − δ)] 2 /(i 2p1,min + i 2p 2,min )
and PWM IC is UCC2893. Fig. 5 shows the gate and drain
voltages of main and auxiliary switches at light load
(Po=100W). On the same manner, the gate and drain voltages
of S1 and S2 at full load (Po=100W) are given in Fig. 6. It can
been seen in Figs. 5 and 6 that the ZVS of both switches are
achieved clearly since the drain voltages are decreased to zero
voltage before the switches are turned on. Figs. 7 and 8 are the
measured waveforms of gate voltage, transformer primary
currents and switch currents at light and full load respectively.
Before the switches S1 and S2 are turned on, the switch currents
flow in the opposite direction. Thus the ZVS of both switches
are achieved. When S1 is on, the primary currents ip1 and ip2
increase and the switch current iS1 also increases. When S1 is
off and S2 is on, the primary currents ip1 and ip2 decrease and
the switch current iS2 increases. However, the average value of
switch current iS2 is zero to maintain the constant clamp
voltage VC1. Fig. 9 shows the measured waveforms of vS1,gs,
diode currents iD1~iD4, load current io and output voltage Vo at
full load (Po=480W). When S1 is in the on-state in mode 1, the
diodes D1~D4 are all off such that the diode currents iD1~iD4 are
all zero ampere. When S1 is in the off-state in mode 3, the
rectifier diodes D1~D4 are all conducting and the diode currents
iD1~iD4 increase. It can be seen that all measured waveforms
shown in Figs. 5~9 well coincide with the theoretical analysis
in section 3.
Table 1: components list
Input ac voltage vac
Input dc voltage Vin
Output voltage Vout
Bridge diodes BD
PFC switch S
PFC boost inductor L
PFC boost diode D
PFC boost capacitor C
PFC switching frequency
DC-DC switching frequency
Turns ratio Np:Ns (T1~T4)
Clamp capacitor C1、C2
Magnetizing inductance Lm (T1~T4)
Leakage inductance Lr (T1~T4)
Resonant capacitor Cr1、Cr2
Main and auxiliary switches S1、S2
Rectifier diodes D1~D4
Output capacitor Co
From the waveforms shown in Fig. 2, the half of resonant
period by leakage inductance and clamp capacitance is much
greater than turn-off time in mode 3. Thus the clamp
capacitance can be given as:
(1 − δ min,eff ) 2
(40)
C1 >>
2L r π 2 f 2
The capacitance C2 is equal to C1 in the proposed converter.
90-130Vrms
200V
48V
D10XB60
IRFP22N60KPBF
0.4mH
LQA08TC600
330μF/400V
70k Hz
90kHz
54:30
0.1μF
0.4mH
3uH
700pF
FS14SM-16A
S20LC20U
2200μF
Fig. 4 Circuit configuration of the prototype converter.
V. EXPERIMENTS
A 480W prototype of the proposed converter with power
factor pre-regulator has been constructed (Fig. 4) and the
parameters are listed in Table 1. The experimental results of
the proposed converter are presented for the nominal input ac
voltage vac=110Vrms, input dc voltage Vin=200V and output
voltage Vo=48V. The adopted PFC control IC is ICE1PCS02
Fig. 5 Measured waveforms of gate voltages and drain voltages of switches S1
and S2 at light load (Po=100W).
1596
the current stresses on the rectifier diodes can be reduced.
Additionally both switches are shared by two converter
modules such that the power components are reduced
compared with the components in the conventional parallel
flyback converter. Finally, the experiments based on a 480W
prototype are provided to verify the theoretical analysis and the
effectiveness of the proposed converter. Based on the
experimental tests, the measured results agree with the
theoretical waveforms in the proposed converter.
Fig. 6 Measured waveforms of gate voltages and drain voltages of switches S1
and S2 at full load (Po=480W).
Fig. 9 Measured waveforms of gate voltage vS1,gs, diode currents iD1~iD2, load
current io and output voltage vo at full load (Po=480W).
Fig. 7 Measured waveforms of the gate voltage vS1,gs, primary side currents ip1
and ip2, and switch currents iS1 and iS2 at light load (Po=100W).
VII.
ACKNOWLEDGMENT
This project is supported by the National Science Council
of Taiwan under Grant NSC 97-2221-E-224-064-MY2.
REFERENCES
Fig. 8 Measured waveforms of the gate voltage vS1,gs, primary side currents ip1
and ip2, and switch currents iS1 and iS2 at full load (Po=480W).
VI. CONCLUSIONS
In this paper, the active-clamping quad-flyback converter
has been proposed to achieve zero-voltage switching and share
the load current. The ZVS turn-on of both switches are
achieved at the transition interval due to the resonance such
that the switching losses are reduced. Two transformers are
connected in series in each converter module such that the load
current can be equally distributed in each rectifier diode. Thus
[1] M. Nakaoka, G. Yu, A. Chibani, H. Yonemori, H. Ueda, and Y. Ogino, Y.,
“Resonant flyback switched-mode DC-DC converters using static induction
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pp. 1066 – 1071, 1998.
[3] B.-R. Lin, C.-E. Huang, K. Huang, and D. Wang, “Design and
implementation of zero-voltage-switching flyback converter with
synchronous rectifier”, IEE Proc. – Electrical Power Applications, vol.
153, pp. 420-428, 2006.
[4] N.P. Papanikolaou and E. C. Tatakis, “Active voltage clamp in flyback
converters operating in CCM mode under wide load variation”, IEEE Trans.
Ind. Electron., vol. 51, pp. 632 – 640, 2004.
[5] R. Watson, G. C. Hua and F. C. Lee, “Characterization of an active clamp
flyback topology for power factor correction applications”, IEEE Trans.
Power Electron., vol. 11, pp. 191 – 198, 1996.
[6] F. Forest, E. Laboure, T. A. Meynard and J. J. Huselstein, “Multicell
Interleaved Flyback Using Intercell Transformers”, IEEE Trans. Power
Electron., vol. 22, pp. 1662-1671, 2007.
[7] Q. Ting, and B. Lehman, “Coupled Input-Series and Output-Parallel Dual
Interleaved Flyback Converter for High Input Voltage Application”, IEEE
Trans. Power Electron., vol. 23, pp. 88-95, 2008.
[8] H. Wang, C. Gong, H. Ma and Y. Yan, “Research on a Novel Interleaved
Flyback DC/DC Converter”, in Proc. IEEE ICIEA’06, vol. 1, pp. 1-5, 2006.
[9] J. Zhao, H. Zhao and F. Dai, “A Novel ZVS PWM Interleaved Flyback
Converter”, in Proc. IEEE ICIEA’07, vol. 1, pp. 337-341, 2007.
1597
國立雲林科技大學碩士班研究生出席國際會議報告
98 年
報告人姓名
曹灃繽
就讀系所及年級
自 98 年 7 月 5 日至
會議/競賽
98 年 7 月 8 日
期間及地點
補助項目及金額
韓國、首爾
7
月
10
日
電機工程研究所碩士班
■機票費
□註冊費
總金額新台幣 14000 元
會議/競賽
(中文) IEEE 工業電子國際研討會(IEEE ISIE 2009)
名稱
(英文) IEEE International Symposium on Industrial Electronics (IEEE ISIE 2009)
論文題目或
(中文)主動箝位多組並聯反馳式轉換器
競賽項目
(英文)Active-Clamping Quad-Flyback Converter
一、 參加會議或競賽經過
2009 年 IEEE-ISIE 國際研討會為全世界有關 Computer, Advanced Control Systems, and
Intelligent Control、Power Electronics and Electrical Drives、Sensors, Actuators and Systems
Integration、Signal and Image Processing、Industrial Informatics、Robotics, and
Telecommunications 相關研究方面重要會議之一。此次會議於 2009 年 7 月 5 日至 7 月 9 日
在首爾 Olympic Parktel 舉行。研討會議議程包含廣泛，此次會議共有來自世界各個共 45 國
家超過 625 篇文章投稿，而經大會審查結果共有約 413 篇論文被接受，並於三天內分為 71
個 session 進行發表。而學生被安排在於此 7 月 8 日上午九點整發表論文，另外學生欲增廣
個人研究視野，亦利用會議期間參與了與個人目前研究領域相關地研究議程，如 Advances in
DC-DC Converters (Ⅰ), Advances in DC-DC Converters (Ⅱ), High Performance DC-DC
Converters, Control Techniques in DC-AC Converters, 等四個相關議程。在學生報告的議程間
及其他議程認識了國外的一些學者與學生因此非常感謝本校予以補助，使得學生能參與此次
國際研討會並與國際接軌。
參加會議行程簡介
98 年 7 月 5 日:斗六-台北-首爾,長榮航空
98 年 7 月 6 日:參加 IEEE- ISIE2009 參加研討會(完成報到及領取相關資料 )
98 年 7 月 7 日:參加 IEEE- ISIE2009 參加研討會並發表論文
98 年 7 月 8 日:參加 IEEE- ISIE2009 參加研討會
98 年 7 月 9 日:首爾-台北-斗六,長榮航空
二、 與會心得
IEEE-ISIE 國際研討會為全世界有關 Computer, Advanced Control Systems, and Intelligent
Control、Power Electronics and Electrical Drives、Sensors, Actuators and Systems Integration、
Signal and Image Processing、Industrial Informatics、Robotics, and Telecommunications 相關研
究方面重要會議之一，而此次會議總發表稿件約有 413 篇文章，其中不乏來自台灣學者的研
究。而雖然目前台灣在電力電子、以及控制以及訊號處理等相關研究上具有重要的地位，但
大陸學者今年亦有多篇文章發表。此次是學生第一次在這麼大型的國際研討會上發表研究成
果，為了能充分表達自己所做之成果，故就所發表的內容反覆地練習，並且經過指導教授不
厭其煩地再三修正投影片內容與英文報告之錯誤，以期達到表達的正確性。
學生在國內亦參與了多次的國內的研討會，但畢竟僅只於國內舉辦，外國的研究學者出
席的機率不高，因此僅侷限國內重點地研究領域發表。而在我經過這三天參與了此研討會，
發現國外學者那種針對問題不徇私、熱烈討論、提出精闢見解以及無時無刻都在學習的熱
誠，真是令人欽佩。
三、 建
議
IEEE-ISIE 國際研討會為全世界有關 Computer, Advanced Control Systems, and
Intelligent Control、Power Electronics and Electrical Drives、Sensors, Actuators and Systems
Integration、Signal and Image Processing、Industrial Informatics、Robotics, and
Telecommunications 相關研究方面重要會議，且其所發表文章亦皆相當嚴謹並具有創新性。
會議中所發表之論文對工業升級及高科技之發展皆具相當能力之影響力，因此非常感謝雲林
科技大學能夠補助學生參與此次國際研討會之註冊、機票以及生活費用，使得在參與此次會
議後深感成果非常豐碩，視野也增進不少。此外，希望國內亦應該多多舉辦此類國際性研討
會，藉由資訊與研究成果交流下，促進國內研究環境蓬勃發展。
此會議至今已第 18 屆，係由韓國首爾承辦，且經由第 19 屆之邀稿文件得知係由義大
利來承辦，因此希望國內亦能爭取此研討會在國內舉辦，不僅可提高研究水準，亦可使國內
未獲經費補助之學者有機會在國內參與國際研討會並與國外學者互相切磋。
四、 攜帶資料名稱及內容
(1)註冊收據證明及大會議程手冊
(2)論文光碟片一張
(3)ISIE2010 Call for Paper
(4)ICIT2010 Call for Paper
【備註】報告請以 PDF 檔傳送國際事務處信箱 tdx@yuntech.edu.tw。
檔案命名方式：請以學生姓名學號＋傳送日期。